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-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-13/0001-LOCAL-Testsuite-builtins-tests-require-fpic-Signed-o.patch35
-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-13/0002-Quick-fail-g-.dg-opt-memcpy1.C-This-particular-testc.patch31
-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-13/0003-For-dejagnu-static-testing-on-qemu-suppress-warnings.patch35
-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-13/0004-Add-MicroBlaze-to-target-supports-for-atomic-buil.-..patch35
-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-13/0005-Update-MicroBlaze-strings-test-for-new-scan-assembly.patch36
-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-13/0006-Allow-MicroBlaze-.weakext-pattern-in-regex-match-Ext.patch67
-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-13/0007-Add-MicroBlaze-to-check_profiling_available-Testsuit.patch27
-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-13/0008-Fix-atomic-side-effects.-In-atomic_compare_and_swaps.patch67
-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-13/0009-Fix-atomic-boolean-return-value.-In-atomic_compare_a.patch40
-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-13/0010-Fix-the-Microblaze-crash-with-msmall-divides-flag-Co.patch35
-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-13/0011-Added-ashrsi3_with_size_opt-Added-ashrsi3_with_size_.patch48
-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-13/0012-Use-bralid-for-profiler-calls-Signed-off-by-Edgar-E..patch26
-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-13/0013-Removed-moddi3-routinue-Using-the-default-moddi3-fun.patch160
-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-13/0014-Add-INIT_PRIORITY-support-Added-TARGET_ASM_CONSTRUCT.patch90
-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-13/0015-Add-optimized-lshrsi3-When-barrel-shifter-is-not-pre.patch81
-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-13/0016-Add-cbranchsi4_reg-This-patch-optimizes-the-generati.patch146
-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-13/0017-Inline-Expansion-of-fsqrt-builtin.-The-changes-are-m.patch58
-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-13/0018-microblaze.md-Improve-adddi3-and-subdi3-insn-definit.patch63
-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-13/0019-Update-ashlsi3-movsf-patterns-This-patch-removes-the.patch75
-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-13/0020-8-stage-pipeline-for-microblaze-This-patch-adds-the-.patch177
-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-13/0021-Correct-the-const-high-double-immediate-value-with-t.patch58
-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-13/0022-Fix-internal-compiler-error-with-msmall-divides-This.patch31
-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-13/0023-Fix-the-calculation-of-high-word-in-a-long-long-64-b.patch36
-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-13/0024-this-patch-has-1.Fixed-the-bug-in-version-calculatio.patch373
-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-13/0025-Fixing-the-issue-with-the-builtin_alloc.-register-r1.patch44
-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-13/0026-Removed-fsqrt-generation-for-double-values.patch37
-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-13/0027-Intial-commit-of-64-bit-Microblaze.patch784
-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-13/0028-Intial-commit-for-64bit-MB-sources.-Need-to-cleanup-.patch2442
-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-13/0029-re-arrangement-of-the-compare-branches.patch268
-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-13/0030-previous-commit-broke-the-handling-of-SI-Branch-comp.patch28
-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-13/0031-Support-of-multilibs-with-m64.patch77
-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-13/0032-Fixed-issues-like-1-Interrupt-alignment-issue-2-Sign.patch70
-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-13/0033-fixed-below-issues-Floating-point-print-issues-in-64.patch304
-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-13/0034-Added-double-arith-instructions-Fixed-prologue-stack.patch135
-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-13/0035-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch37
-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-13/0036-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch256
-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-13/0037-extending-the-Dwarf-support-to-64bit-Microblaze.patch25
-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-13/0038-fixing-the-typo-errors-in-umodsi3-file.patch29
-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-13/0039-fixing-the-32bit-LTO-related-issue9-1014024.patch68
-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-13/0040-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch25
-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-13/0041-corrected-SPN-for-dlong-instruction-mapping.patch28
-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-13/0042-fixing-the-long-long-long-mingw-toolchain-issue.patch59
-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-13/0043-Fix-the-MB-64-bug-of-handling-QI-objects.patch47
-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-13/0044-We-will-check-the-possibility-of-peephole2-optimizat.patch87
-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-13/0045-fixed-typos-in-mul-div-and-mod-assembly-files.patch465
-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-13/0046-MB-64-removal-of-barrel-shift-instructions-from-defa.patch476
-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-13/0047-Added-new-MB-64-single-register-arithmetic-instructi.patch107
-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-13/0048-Added-support-for-64-bit-Immediate-values.patch43
-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-13/0049-Fix-Compiler-crash-with-freg-struct-return-This-patc.patch76
-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-13/0050-Add-TARGET_OPTION_OPTIMIZATION-and-disable-fivopts-b.patch50
-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-13/0051-Reducing-Stack-space-for-arguments.patch189
-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-13/0052-If-we-use-break_handler-attribute-then-interrupt-vec.patch72
-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-13/0053-Add-Zero_extended-instructions.patch58
-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-13/0054-Fix-failure-with-gcc.c-torture-execute-ashrdi-1.c-Os.patch42
-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-13/microblaze-mulitlib-hack.patch58
55 files changed, 8316 insertions, 0 deletions
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0001-LOCAL-Testsuite-builtins-tests-require-fpic-Signed-o.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0001-LOCAL-Testsuite-builtins-tests-require-fpic-Signed-o.patch
new file mode 100644
index 00000000..8b9c6177
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0001-LOCAL-Testsuite-builtins-tests-require-fpic-Signed-o.patch
@@ -0,0 +1,35 @@
1From 8beb2e85436c77db197ce22626c7b7037d41d595 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Wed, 11 Jan 2017 13:13:57 +0530
4Subject: [PATCH 01/54] LOCAL]: Testsuite - builtins tests require fpic
5 Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
6
7Conflicts:
8
9 gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
10---
11 gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp | 8 ++++++++
12 1 file changed, 8 insertions(+)
13
14diff --git a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
15index fa762d33232..ce8545fc460 100644
16--- a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
17+++ b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
18@@ -48,6 +48,14 @@ if { [istarget *-*-eabi*]
19 lappend additional_flags "-Wl,--allow-multiple-definition"
20 }
21
22+<<<<<<< HEAD
23+=======
24+if [istarget "microblaze*-*-linux*"] {
25+ lappend additional_flags "-Wl,-zmuldefs"
26+ lappend additional_flags "-fPIC"
27+}
28+
29+>>>>>>> 6ef6e5b... [LOCAL]: Testsuite - builtins tests require fpic
30 foreach src [lsort [find $srcdir/$subdir *.c]] {
31 if {![string match *-lib.c $src] && [runtest_file_p $runtests $src]} {
32 c-torture-execute [list $src \
33--
342.34.1
35
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0002-Quick-fail-g-.dg-opt-memcpy1.C-This-particular-testc.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0002-Quick-fail-g-.dg-opt-memcpy1.C-This-particular-testc.patch
new file mode 100644
index 00000000..94970e7b
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0002-Quick-fail-g-.dg-opt-memcpy1.C-This-particular-testc.patch
@@ -0,0 +1,31 @@
1From 4a2d958fe0d54c78b7a131b9cde1c74165533aaf Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Wed, 11 Jan 2017 14:31:10 +0530
4Subject: [PATCH 02/54] Quick fail g++.dg/opt/memcpy1.C This particular
5 testcase fails with a timeout. Instead, fail it at compile-time for
6 microblaze. This speeds up the testsuite without removing it from the FAIL
7 reports.
8
9Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
10---
11 gcc/testsuite/g++.dg/opt/memcpy1.C | 4 ++++
12 1 file changed, 4 insertions(+)
13
14diff --git a/gcc/testsuite/g++.dg/opt/memcpy1.C b/gcc/testsuite/g++.dg/opt/memcpy1.C
15index 3862756083d..db9f990f781 100644
16--- a/gcc/testsuite/g++.dg/opt/memcpy1.C
17+++ b/gcc/testsuite/g++.dg/opt/memcpy1.C
18@@ -4,6 +4,10 @@
19 // { dg-do compile }
20 // { dg-options "-O" }
21
22+#if defined (__MICROBLAZE__)
23+#error "too slow on mb. Investigate."
24+#endif
25+
26 typedef unsigned char uint8_t;
27 typedef uint8_t uint8;
28 __extension__ typedef __SIZE_TYPE__ size_t;
29--
302.34.1
31
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0003-For-dejagnu-static-testing-on-qemu-suppress-warnings.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0003-For-dejagnu-static-testing-on-qemu-suppress-warnings.patch
new file mode 100644
index 00000000..5b4466d8
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0003-For-dejagnu-static-testing-on-qemu-suppress-warnings.patch
@@ -0,0 +1,35 @@
1From 0b4ec0cbfc13f5a40a20663da9c074ac81c5ec3f Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Wed, 11 Jan 2017 15:46:28 +0530
4Subject: [PATCH 03/54] For dejagnu static testing on qemu, suppress warnings
5 about multiple definitions from the test function and libc in line with
6 method used by powerpc. Dynamic linking and using a qemu binary which
7 understands sysroot resolves all test failures with builtins
8
9Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
10---
11 gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp | 4 ----
12 1 file changed, 4 deletions(-)
13
14diff --git a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
15index ce8545fc460..72fd697d855 100644
16--- a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
17+++ b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
18@@ -48,14 +48,10 @@ if { [istarget *-*-eabi*]
19 lappend additional_flags "-Wl,--allow-multiple-definition"
20 }
21
22-<<<<<<< HEAD
23-=======
24 if [istarget "microblaze*-*-linux*"] {
25 lappend additional_flags "-Wl,-zmuldefs"
26- lappend additional_flags "-fPIC"
27 }
28
29->>>>>>> 6ef6e5b... [LOCAL]: Testsuite - builtins tests require fpic
30 foreach src [lsort [find $srcdir/$subdir *.c]] {
31 if {![string match *-lib.c $src] && [runtest_file_p $runtests $src]} {
32 c-torture-execute [list $src \
33--
342.34.1
35
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0004-Add-MicroBlaze-to-target-supports-for-atomic-buil.-..patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0004-Add-MicroBlaze-to-target-supports-for-atomic-buil.-..patch
new file mode 100644
index 00000000..87adeaf4
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0004-Add-MicroBlaze-to-target-supports-for-atomic-buil.-..patch
@@ -0,0 +1,35 @@
1From dcb106f7cb2fb68f3117677b12df2b01f3929f7b Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Wed, 11 Jan 2017 15:50:35 +0530
4Subject: [PATCH 04/54] Add MicroBlaze to target-supports for atomic buil. .tin
5 tests
6
7MicroBlaze added to supported targets for atomic builtin tests.
8
9Changelog/testsuite
10
112014-02-14 David Holsgrove <david.holsgrove@xilinx.com>
12
13 * gcc/testsuite/lib/target-supports.exp: Add microblaze to
14 check_effective_target_sync_int_long.
15
16Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
17---
18 gcc/testsuite/lib/target-supports.exp | 1 +
19 1 file changed, 1 insertion(+)
20
21diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
22index 40f71e9ed8b..32e29706fcd 100644
23--- a/gcc/testsuite/lib/target-supports.exp
24+++ b/gcc/testsuite/lib/target-supports.exp
25@@ -8947,6 +8947,7 @@ proc check_effective_target_sync_int_long { } {
26 && [check_effective_target_arm_acq_rel])
27 || [istarget bfin*-*linux*]
28 || [istarget hppa*-*linux*]
29+ || [istarget microblaze*-*linux*]
30 || [istarget s390*-*-*]
31 || [istarget powerpc*-*-*]
32 || [istarget cris-*-*]
33--
342.34.1
35
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0005-Update-MicroBlaze-strings-test-for-new-scan-assembly.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0005-Update-MicroBlaze-strings-test-for-new-scan-assembly.patch
new file mode 100644
index 00000000..9a8d0a86
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0005-Update-MicroBlaze-strings-test-for-new-scan-assembly.patch
@@ -0,0 +1,36 @@
1From 68bc05ae258334f591c336dbed6dc907969e90fc Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Wed, 11 Jan 2017 16:20:01 +0530
4Subject: [PATCH 05/54] Update MicroBlaze strings test for new scan-assembly
5 output resulting in use of $LC label
6
7ChangeLog/testsuite
8
92014-02-14 David Holsgrove <david.holsgrove@xilinx.com>
10
11 * gcc/testsuite/gcc.target/microblaze/others/strings1.c: Update
12 to include $LC label.
13
14Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
15---
16 gcc/testsuite/gcc.target/microblaze/others/strings1.c | 4 ++++
17 1 file changed, 4 insertions(+)
18
19diff --git a/gcc/testsuite/gcc.target/microblaze/others/strings1.c b/gcc/testsuite/gcc.target/microblaze/others/strings1.c
20index efaf3c660ea..347872360d3 100644
21--- a/gcc/testsuite/gcc.target/microblaze/others/strings1.c
22+++ b/gcc/testsuite/gcc.target/microblaze/others/strings1.c
23@@ -3,6 +3,10 @@
24 /* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),\\\$LC.*" } } */
25 /* { dg-final { scan-assembler "\lwi\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),*" } } */
26
27+/* { dg-final { scan-assembler "\.rodata*" } } */
28+/* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),\\\$LC.*" } } */
29+/* { dg-final { scan-assembler "\lwi\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),*" } } */
30+
31 #include <string.h>
32
33 extern void somefunc (char *);
34--
352.34.1
36
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0006-Allow-MicroBlaze-.weakext-pattern-in-regex-match-Ext.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0006-Allow-MicroBlaze-.weakext-pattern-in-regex-match-Ext.patch
new file mode 100644
index 00000000..c32a8bab
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0006-Allow-MicroBlaze-.weakext-pattern-in-regex-match-Ext.patch
@@ -0,0 +1,67 @@
1From 7b07ae9c8086973b7baa031b09889146057de8ab Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Thu, 12 Jan 2017 16:14:15 +0530
4Subject: [PATCH 06/54] Allow MicroBlaze .weakext pattern in regex match Extend
5 regex pattern to include optional ext at the end of .weak to match the
6 MicroBlaze weak label .weakext
7
8ChangeLog/testsuite
9
102014-02-14 David Holsgrove <david.holsgrove@xilinx.com>
11
12 * gcc/testsuite/g++.dg/abi/rtti3.C: Extend scan-assembler
13 pattern to take optional ext after .weak.
14 * gcc/testsuite/g++.dg/abi/thunk4.C: Likewise.
15
16Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
17
18Conflicts:
19
20 gcc/testsuite/g++.dg/abi/rtti3.C
21---
22 gcc/testsuite/g++.dg/abi/rtti3.C | 4 ++--
23 gcc/testsuite/g++.dg/abi/thunk3.C | 2 +-
24 gcc/testsuite/g++.dg/abi/thunk4.C | 2 +-
25 3 files changed, 4 insertions(+), 4 deletions(-)
26
27diff --git a/gcc/testsuite/g++.dg/abi/rtti3.C b/gcc/testsuite/g++.dg/abi/rtti3.C
28index 0cc7d3e79d0..f284cd9255c 100644
29--- a/gcc/testsuite/g++.dg/abi/rtti3.C
30+++ b/gcc/testsuite/g++.dg/abi/rtti3.C
31@@ -3,8 +3,8 @@
32
33 // { dg-require-weak "" }
34 // { dg-skip-if "Linkonce not weak" { *-*-mingw* *-*-cygwin } }
35-// { dg-final { scan-assembler ".weak\[ \t\]_?_ZTSPP1A" { target { ! { *-*-darwin* hppa*-*-hpux* } } } } }
36-// { dg-final { scan-assembler-not ".weak\[ \t\]_?_ZTIPP1A" { target { ! { *-*-darwin* } } } } }
37+// { dg-final { scan-assembler ".weak(ext)?\[ \t\]_?_ZTSPP1A" { target { ! { *-*-darwin* } } } } }
38+// { dg-final { scan-assembler-not ".weak(ext)?\[ \t\]_?_ZTIPP1A" { target { ! { *-*-darwin* } } } } }
39 // { dg-final { scan-assembler ".weak_definition\[ \t\]_?_ZTSPP1A" { target { *-*-darwin* } } } }
40 // { dg-final { scan-assembler-not ".weak_definition\[ \t\]_?_ZTIPP1A" { target { *-*-darwin* } } } }
41
42diff --git a/gcc/testsuite/g++.dg/abi/thunk3.C b/gcc/testsuite/g++.dg/abi/thunk3.C
43index f2347f79ecd..dcec8a771a1 100644
44--- a/gcc/testsuite/g++.dg/abi/thunk3.C
45+++ b/gcc/testsuite/g++.dg/abi/thunk3.C
46@@ -1,5 +1,5 @@
47 // { dg-require-weak "" }
48-// { dg-final { scan-assembler-not ".weak\[\t \]_?_ZThn._N7Derived3FooEv" { target { ! { *-*-darwin* } } } } }
49+// { dg-final { scan-assembler-not ".weak(ext)?\[\t \]_?_ZThn._N7Derived3FooEv" { target { ! { *-*-darwin* } } } } }
50 // { dg-final { scan-assembler-not ".weak_definition\[\t \]_?_ZThn._N7Derived3FooEv" { target { *-*-darwin* } } } }
51
52 struct Base
53diff --git a/gcc/testsuite/g++.dg/abi/thunk4.C b/gcc/testsuite/g++.dg/abi/thunk4.C
54index 6e8f124bc5e..d1d34fe1e4a 100644
55--- a/gcc/testsuite/g++.dg/abi/thunk4.C
56+++ b/gcc/testsuite/g++.dg/abi/thunk4.C
57@@ -1,6 +1,6 @@
58 // { dg-require-weak "" }
59 // { dg-skip-if "Linkonce not weak" { *-*-mingw* *-*-cygwin } }
60-// { dg-final { scan-assembler ".weak\[ \t\]_?_ZThn._N7Derived3FooEv" { target { ! { *-*-darwin* } } } } }
61+// { dg-final { scan-assembler ".weak(ext)?\[ \t\]_?_ZThn._N7Derived3FooEv" { target { ! { *-*-darwin* } } } } }
62 // { dg-final { scan-assembler ".weak_definition\[ \t\]_?_ZThn._N7Derived3FooEv" { target { *-*-darwin* } } } }
63
64 struct Base
65--
662.34.1
67
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0007-Add-MicroBlaze-to-check_profiling_available-Testsuit.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0007-Add-MicroBlaze-to-check_profiling_available-Testsuit.patch
new file mode 100644
index 00000000..5de0bfd8
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0007-Add-MicroBlaze-to-check_profiling_available-Testsuit.patch
@@ -0,0 +1,27 @@
1From 6de628ecccf3739891052a2fbaf97048384c6190 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Thu, 12 Jan 2017 16:34:27 +0530
4Subject: [PATCH 07/54] Add MicroBlaze to check_profiling_available Testsuite,
5 add microblaze*-*-* target in check_profiling_available inline with other
6 archs setting profiling_available_saved to 0
7
8Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
9---
10 gcc/testsuite/lib/target-supports.exp | 1 +
11 1 file changed, 1 insertion(+)
12
13diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
14index 32e29706fcd..47233563339 100644
15--- a/gcc/testsuite/lib/target-supports.exp
16+++ b/gcc/testsuite/lib/target-supports.exp
17@@ -804,6 +804,7 @@ proc check_profiling_available { test_what } {
18 || [istarget m68k-*-elf]
19 || [istarget m68k-*-uclinux*]
20 || [istarget mips*-*-elf*]
21+ || [istarget microblaze*-*-*]
22 || [istarget mmix-*-*]
23 || [istarget mn10300-*-elf*]
24 || [istarget moxie-*-elf*]
25--
262.34.1
27
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0008-Fix-atomic-side-effects.-In-atomic_compare_and_swaps.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0008-Fix-atomic-side-effects.-In-atomic_compare_and_swaps.patch
new file mode 100644
index 00000000..e554e660
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0008-Fix-atomic-side-effects.-In-atomic_compare_and_swaps.patch
@@ -0,0 +1,67 @@
1From cd3db73d253df229054863e5f920e59e60b84c45 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Thu, 12 Jan 2017 16:41:43 +0530
4Subject: [PATCH 08/54] Fix atomic side effects. In atomic_compare_and_swapsi,
5 add side effects to prevent incorrect assumptions during optimization.
6 Previously, the outputs were considered unused; this generated assembly code
7 with undefined side effects after invocation of the atomic.
8
9Signed-off-by: Kirk Meyer <kirk.meyer@sencore.com>
10Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
11
12Conflicts:
13 gcc/config/microblaze/microblaze.md
14---
15 gcc/config/microblaze/microblaze.md | 3 +++
16 gcc/config/microblaze/sync.md | 21 +++++++++++++--------
17 2 files changed, 16 insertions(+), 8 deletions(-)
18
19diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
20index 671667b537c..dfd7395432b 100644
21--- a/gcc/config/microblaze/microblaze.md
22+++ b/gcc/config/microblaze/microblaze.md
23@@ -43,6 +43,9 @@
24 (UNSPEC_TLS 106) ;; jump table
25 (UNSPEC_SET_TEXT 107) ;; set text start
26 (UNSPEC_TEXT 108) ;; data text relative
27+ (UNSPECV_CAS_BOOL 201) ;; compare and swap (bool)
28+ (UNSPECV_CAS_VAL 202) ;; compare and swap (val)
29+ (UNSPECV_CAS_MEM 203) ;; compare and swap (mem)
30 ])
31
32 (define_c_enum "unspec" [
33diff --git a/gcc/config/microblaze/sync.md b/gcc/config/microblaze/sync.md
34index c84bac94101..587f852b3a0 100644
35--- a/gcc/config/microblaze/sync.md
36+++ b/gcc/config/microblaze/sync.md
37@@ -18,14 +18,19 @@
38 ;; <http://www.gnu.org/licenses/>.
39
40 (define_insn "atomic_compare_and_swapsi"
41- [(match_operand:SI 0 "register_operand" "=&d") ;; bool output
42- (match_operand:SI 1 "register_operand" "=&d") ;; val output
43- (match_operand:SI 2 "nonimmediate_operand" "+Q") ;; memory
44- (match_operand:SI 3 "register_operand" "d") ;; expected value
45- (match_operand:SI 4 "register_operand" "d") ;; desired value
46- (match_operand:SI 5 "const_int_operand" "") ;; is_weak
47- (match_operand:SI 6 "const_int_operand" "") ;; mod_s
48- (match_operand:SI 7 "const_int_operand" "") ;; mod_f
49+ [(set (match_operand:SI 0 "register_operand" "=&d") ;; bool output
50+ (unspec_volatile:SI
51+ [(match_operand:SI 2 "nonimmediate_operand" "+Q") ;; memory
52+ (match_operand:SI 3 "register_operand" "d") ;; expected value
53+ (match_operand:SI 4 "register_operand" "d")] ;; desired value
54+ UNSPECV_CAS_BOOL))
55+ (set (match_operand:SI 1 "register_operand" "=&d") ;; val output
56+ (unspec_volatile:SI [(const_int 0)] UNSPECV_CAS_VAL))
57+ (set (match_dup 2)
58+ (unspec_volatile:SI [(const_int 0)] UNSPECV_CAS_MEM))
59+ (match_operand:SI 5 "const_int_operand" "") ;; is_weak
60+ (match_operand:SI 6 "const_int_operand" "") ;; mod_s
61+ (match_operand:SI 7 "const_int_operand" "") ;; mod_f
62 (clobber (match_scratch:SI 8 "=&d"))]
63 ""
64 {
65--
662.34.1
67
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0009-Fix-atomic-boolean-return-value.-In-atomic_compare_a.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0009-Fix-atomic-boolean-return-value.-In-atomic_compare_a.patch
new file mode 100644
index 00000000..617b10f3
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0009-Fix-atomic-boolean-return-value.-In-atomic_compare_a.patch
@@ -0,0 +1,40 @@
1From 7eca0d5cf7bc603c5a359b70521861c11faf6038 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Thu, 12 Jan 2017 16:45:45 +0530
4Subject: [PATCH 09/54] Fix atomic boolean return value. In
5 atomic_compare_and_swapsi, fix boolean return value. Previously, it contained
6 zero if successful and non-zero if unsuccessful.
7
8Signed-off-by: Kirk Meyer <kirk.meyer@sencore.com>
9Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
10---
11 gcc/config/microblaze/sync.md | 7 ++++---
12 1 file changed, 4 insertions(+), 3 deletions(-)
13
14diff --git a/gcc/config/microblaze/sync.md b/gcc/config/microblaze/sync.md
15index 587f852b3a0..230699bf280 100644
16--- a/gcc/config/microblaze/sync.md
17+++ b/gcc/config/microblaze/sync.md
18@@ -34,15 +34,16 @@
19 (clobber (match_scratch:SI 8 "=&d"))]
20 ""
21 {
22- output_asm_insn ("addc \tr0,r0,r0", operands);
23+ output_asm_insn ("add \t%0,r0,r0", operands);
24 output_asm_insn ("lwx \t%1,%y2,r0", operands);
25 output_asm_insn ("addic\t%8,r0,0", operands);
26 output_asm_insn ("bnei \t%8,.-8", operands);
27- output_asm_insn ("cmp \t%0,%1,%3", operands);
28- output_asm_insn ("bnei \t%0,.+16", operands);
29+ output_asm_insn ("cmp \t%8,%1,%3", operands);
30+ output_asm_insn ("bnei \t%8,.+20", operands);
31 output_asm_insn ("swx \t%4,%y2,r0", operands);
32 output_asm_insn ("addic\t%8,r0,0", operands);
33 output_asm_insn ("bnei \t%8,.-28", operands);
34+ output_asm_insn ("addi \t%0,r0,1", operands);
35 return "";
36 }
37 )
38--
392.34.1
40
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0010-Fix-the-Microblaze-crash-with-msmall-divides-flag-Co.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0010-Fix-the-Microblaze-crash-with-msmall-divides-flag-Co.patch
new file mode 100644
index 00000000..42b9d575
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0010-Fix-the-Microblaze-crash-with-msmall-divides-flag-Co.patch
@@ -0,0 +1,35 @@
1From 72cdba90d70131c092918c5d5c18eb800f0f9dfb Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Thu, 12 Jan 2017 16:50:17 +0530
4Subject: [PATCH 10/54] Fix the Microblaze crash with msmall-divides flag
5 Compiler is crashing when we use msmall-divides and mxl-barrel-shift flag.
6 This is because when use above flags microblaze_expand_divide function will
7 be called for division operation. In microblaze_expand_divide function we are
8 using sub_reg but MicroBlaze doesn't have subreg register due to this
9 compiler was crashing. Changed the logic to avoid sub_reg call
10
11Signed-off-by:Nagaraju Mekala <nmekala@xilix.com>
12
13Conflicts:
14 gcc/config/microblaze/microblaze.c
15---
16 gcc/config/microblaze/microblaze.cc | 3 +--
17 1 file changed, 1 insertion(+), 2 deletions(-)
18
19diff --git a/gcc/config/microblaze/microblaze.cc b/gcc/config/microblaze/microblaze.cc
20index 6df2c712cab..11e34b3fdae 100644
21--- a/gcc/config/microblaze/microblaze.cc
22+++ b/gcc/config/microblaze/microblaze.cc
23@@ -3719,8 +3719,7 @@ microblaze_expand_divide (rtx operands[])
24 mem_rtx = gen_rtx_MEM (QImode,
25 gen_rtx_PLUS (Pmode, regt1, div_table_rtx));
26
27- insn = emit_insn (gen_movqi (regqi, mem_rtx));
28- insn = emit_insn (gen_movsi (operands[0], gen_rtx_SUBREG (SImode, regqi, 0)));
29+ insn = emit_insn (gen_zero_extendqisi2(operands[0],mem_rtx));
30 jump = emit_jump_insn_after (gen_jump (div_end_label), insn);
31 JUMP_LABEL (jump) = div_end_label;
32 LABEL_NUSES (div_end_label) = 1;
33--
342.34.1
35
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0011-Added-ashrsi3_with_size_opt-Added-ashrsi3_with_size_.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0011-Added-ashrsi3_with_size_opt-Added-ashrsi3_with_size_.patch
new file mode 100644
index 00000000..8988e23b
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0011-Added-ashrsi3_with_size_opt-Added-ashrsi3_with_size_.patch
@@ -0,0 +1,48 @@
1From 41d8b3677d64bf9408925667c103a04b176050d5 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Thu, 12 Jan 2017 16:52:56 +0530
4Subject: [PATCH 11/54] Added ashrsi3_with_size_opt Added ashrsi3_with_size_opt
5 pattern to optimize the sra instructions when the -Os optimization is used.
6 lshrsi3_with_size_opt is being removed as it has conflicts with unsigned int
7 variables
8
9Signed-off-by:Nagaraju Mekala <nmekala@xilix.com>
10---
11 gcc/config/microblaze/microblaze.md | 21 +++++++++++++++++++++
12 1 file changed, 21 insertions(+)
13
14diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
15index dfd7395432b..4f20b8efe33 100644
16--- a/gcc/config/microblaze/microblaze.md
17+++ b/gcc/config/microblaze/microblaze.md
18@@ -1508,6 +1508,27 @@
19 (set_attr "length" "4,4")]
20 )
21
22+(define_insn "*ashrsi3_with_size_opt"
23+ [(set (match_operand:SI 0 "register_operand" "=&d")
24+ (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
25+ (match_operand:SI 2 "immediate_operand" "I")))]
26+ "(INTVAL (operands[2]) > 5 && optimize_size)"
27+ {
28+ operands[3] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
29+
30+ output_asm_insn ("ori\t%3,r0,%2", operands);
31+ if (REGNO (operands[0]) != REGNO (operands[1]))
32+ output_asm_insn ("addk\t%0,%1,r0", operands);
33+
34+ output_asm_insn ("addik\t%3,%3,-1", operands);
35+ output_asm_insn ("bneid\t%3,.-4", operands);
36+ return "sra\t%0,%0";
37+ }
38+ [(set_attr "type" "arith")
39+ (set_attr "mode" "SI")
40+ (set_attr "length" "20")]
41+)
42+
43 (define_insn "*ashrsi_inline"
44 [(set (match_operand:SI 0 "register_operand" "=&d")
45 (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
46--
472.34.1
48
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0012-Use-bralid-for-profiler-calls-Signed-off-by-Edgar-E..patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0012-Use-bralid-for-profiler-calls-Signed-off-by-Edgar-E..patch
new file mode 100644
index 00000000..46a8699a
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0012-Use-bralid-for-profiler-calls-Signed-off-by-Edgar-E..patch
@@ -0,0 +1,26 @@
1From 9dc1f7291c4c7abfe254ca4e86a6ba0975a74960 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Tue, 17 Jan 2017 10:57:19 +0530
4Subject: [PATCH 12/54] Use bralid for profiler calls Signed-off-by: Edgar E.
5 Iglesias <edgar.iglesias@gmail.com>
6
7---
8 gcc/config/microblaze/microblaze.h | 2 +-
9 1 file changed, 1 insertion(+), 1 deletion(-)
10
11diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
12index 0398902362b..49e7fbedd5a 100644
13--- a/gcc/config/microblaze/microblaze.h
14+++ b/gcc/config/microblaze/microblaze.h
15@@ -486,7 +486,7 @@ typedef struct microblaze_args
16
17 #define FUNCTION_PROFILER(FILE, LABELNO) { \
18 { \
19- fprintf (FILE, "\tbrki\tr16,_mcount\n"); \
20+ fprintf (FILE, "\tbralid\tr15,_mcount\nnop\n"); \
21 } \
22 }
23
24--
252.34.1
26
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0013-Removed-moddi3-routinue-Using-the-default-moddi3-fun.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0013-Removed-moddi3-routinue-Using-the-default-moddi3-fun.patch
new file mode 100644
index 00000000..26c24a49
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0013-Removed-moddi3-routinue-Using-the-default-moddi3-fun.patch
@@ -0,0 +1,160 @@
1From a2dbb662c573d2bf1a6a9192eb0d7f453ad20c59 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Thu, 12 Jan 2017 17:36:16 +0530
4Subject: [PATCH 13/54] Removed moddi3 routinue Using the default moddi3
5 function as the existing implementation has many bugs
6
7Signed-off-by:Nagaraju <nmekala@xilix.com>
8
9Conflicts:
10 libgcc/config/microblaze/moddi3.S
11---
12 libgcc/config/microblaze/moddi3.S | 121 --------------------------
13 libgcc/config/microblaze/t-microblaze | 3 +-
14 2 files changed, 1 insertion(+), 123 deletions(-)
15 delete mode 100644 libgcc/config/microblaze/moddi3.S
16
17diff --git a/libgcc/config/microblaze/moddi3.S b/libgcc/config/microblaze/moddi3.S
18deleted file mode 100644
19index b3e4bf6182e..00000000000
20--- a/libgcc/config/microblaze/moddi3.S
21+++ /dev/null
22@@ -1,121 +0,0 @@
23-###################################
24-#
25-# Copyright (C) 2009-2023 Free Software Foundation, Inc.
26-#
27-# Contributed by Michael Eager <eager@eagercon.com>.
28-#
29-# This file is free software; you can redistribute it and/or modify it
30-# under the terms of the GNU General Public License as published by the
31-# Free Software Foundation; either version 3, or (at your option) any
32-# later version.
33-#
34-# GCC is distributed in the hope that it will be useful, but WITHOUT
35-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
36-# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
37-# License for more details.
38-#
39-# Under Section 7 of GPL version 3, you are granted additional
40-# permissions described in the GCC Runtime Library Exception, version
41-# 3.1, as published by the Free Software Foundation.
42-#
43-# You should have received a copy of the GNU General Public License and
44-# a copy of the GCC Runtime Library Exception along with this program;
45-# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
46-# <http://www.gnu.org/licenses/>.
47-#
48-# modsi3.S
49-#
50-# modulo operation for 64 bit integers.
51-#
52-#######################################
53-
54-
55-/* An executable stack is *not* required for these functions. */
56-#ifdef __linux__
57-.section .note.GNU-stack,"",%progbits
58-.previous
59-#endif
60-
61- .globl __moddi3
62- .ent __moddi3
63-__moddi3:
64- .frame r1,0,r15
65-
66-#Change the stack pointer value and Save callee saved regs
67- addik r1,r1,-24
68- swi r25,r1,0
69- swi r26,r1,4
70- swi r27,r1,8 # used for sign
71- swi r28,r1,12 # used for loop count
72- swi r29,r1,16 # Used for div value High
73- swi r30,r1,20 # Used for div value Low
74-
75-#Check for Zero Value in the divisor/dividend
76- OR r9,r5,r6 # Check for the op1 being zero
77- BEQID r9,$LaResult_Is_Zero # Result is zero
78- OR r9,r7,r8 # Check for the dividend being zero
79- BEQI r9,$LaDiv_By_Zero # Div_by_Zero # Division Error
80- BGEId r5,$La1_Pos
81- XOR r27,r5,r7 # Get the sign of the result
82- RSUBI r6,r6,0 # Make dividend positive
83- RSUBIC r5,r5,0 # Make dividend positive
84-$La1_Pos:
85- BGEI r7,$La2_Pos
86- RSUBI r8,r8,0 # Make Divisor Positive
87- RSUBIC r9,r9,0 # Make Divisor Positive
88-$La2_Pos:
89- ADDIK r4,r0,0 # Clear mod low
90- ADDIK r3,r0,0 # Clear mod high
91- ADDIK r29,r0,0 # clear div high
92- ADDIK r30,r0,0 # clear div low
93- ADDIK r28,r0,64 # Initialize the loop count
94- # First part try to find the first '1' in the r5/r6
95-$LaDIV1:
96- ADD r6,r6,r6
97- ADDC r5,r5,r5 # left shift logical r5
98- BGEID r5,$LaDIV1
99- ADDIK r28,r28,-1
100-$LaDIV2:
101- ADD r6,r6,r6
102- ADDC r5,r5,r5 # left shift logical r5/r6 get the '1' into the Carry
103- ADDC r4,r4,r4 # Move that bit into the Mod register
104- ADDC r3,r3,r3 # Move carry into high mod register
105- rsub r18,r7,r3 # Compare the High Parts of Mod and Divisor
106- bnei r18,$L_High_EQ
107- rsub r18,r6,r4 # Compare Low Parts only if Mod[h] == Divisor[h]
108-$L_High_EQ:
109- rSUB r26,r8,r4 # Subtract divisor[L] from Mod[L]
110- rsubc r25,r7,r3 # Subtract divisor[H] from Mod[H]
111- BLTi r25,$LaMOD_TOO_SMALL
112- OR r3,r0,r25 # move r25 to mod [h]
113- OR r4,r0,r26 # move r26 to mod [l]
114- ADDI r30,r30,1
115- ADDC r29,r29,r0
116-$LaMOD_TOO_SMALL:
117- ADDIK r28,r28,-1
118- BEQi r28,$LaLOOP_END
119- ADD r30,r30,r30 # Shift in the '1' into div [low]
120- ADDC r29,r29,r29 # Move the carry generated into high
121- BRI $LaDIV2 # Div2
122-$LaLOOP_END:
123- BGEI r27,$LaRETURN_HERE
124- rsubi r30,r30,0
125- rsubc r29,r29,r0
126- BRI $LaRETURN_HERE
127-$LaDiv_By_Zero:
128-$LaResult_Is_Zero:
129- or r29,r0,r0 # set result to 0 [High]
130- or r30,r0,r0 # set result to 0 [Low]
131-$LaRETURN_HERE:
132-# Restore values of CSRs and that of r29 and the divisor and the dividend
133-
134- lwi r25,r1,0
135- lwi r26,r1,4
136- lwi r27,r1,8
137- lwi r28,r1,12
138- lwi r29,r1,16
139- lwi r30,r1,20
140- rtsd r15,8
141- addik r1,r1,24
142- .end __moddi3
143-
144diff --git a/libgcc/config/microblaze/t-microblaze b/libgcc/config/microblaze/t-microblaze
145index 96959f0292b..8d954a49575 100644
146--- a/libgcc/config/microblaze/t-microblaze
147+++ b/libgcc/config/microblaze/t-microblaze
148@@ -1,8 +1,7 @@
149-LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _moddi3 _mulsi3 _udivsi3 _umodsi3
150+LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3
151
152 LIB2ADD += \
153 $(srcdir)/config/microblaze/divsi3.S \
154- $(srcdir)/config/microblaze/moddi3.S \
155 $(srcdir)/config/microblaze/modsi3.S \
156 $(srcdir)/config/microblaze/muldi3_hard.S \
157 $(srcdir)/config/microblaze/mulsi3.S \
158--
1592.34.1
160
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0014-Add-INIT_PRIORITY-support-Added-TARGET_ASM_CONSTRUCT.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0014-Add-INIT_PRIORITY-support-Added-TARGET_ASM_CONSTRUCT.patch
new file mode 100644
index 00000000..9e4348ad
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0014-Add-INIT_PRIORITY-support-Added-TARGET_ASM_CONSTRUCT.patch
@@ -0,0 +1,90 @@
1From 40dd974a6cd608567f1746a934c9743b80ca1e3f Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Mon, 12 Sep 2022 20:20:00 +0530
4Subject: [PATCH 14/54] Add INIT_PRIORITY support Added TARGET_ASM_CONSTRUCTOR
5 and TARGET_ASM_DESTRUCTOR macros.
6
7These macros allows users to control the order of initialization
8of objects defined at namespace scope with the init_priority
9attribute by specifying a relative priority, a constant integral
10expression currently bounded between 101 and 65535 inclusive.
11
12Lower numbers indicate a higher priority.
13---
14 gcc/config/microblaze/microblaze.cc | 53 +++++++++++++++++++++++++++++
15 1 file changed, 53 insertions(+)
16
17diff --git a/gcc/config/microblaze/microblaze.cc b/gcc/config/microblaze/microblaze.cc
18index 11e34b3fdae..3fb402b87d4 100644
19--- a/gcc/config/microblaze/microblaze.cc
20+++ b/gcc/config/microblaze/microblaze.cc
21@@ -2640,6 +2640,53 @@ print_operand_address (FILE * file, rtx addr)
22 }
23 }
24
25+/* Output an element in the table of global constructors. */
26+void
27+microblaze_asm_constructor (rtx symbol ATTRIBUTE_UNUSED, int priority)
28+{
29+ const char *section = ".ctors";
30+ char buf[16];
31+
32+ if (priority != DEFAULT_INIT_PRIORITY)
33+ {
34+ sprintf (buf, ".ctors.%.5u",
35+ /* Invert the numbering so the linker puts us in the proper
36+ order; constructors are run from right to left, and the
37+ linker sorts in increasing order. */
38+ MAX_INIT_PRIORITY - priority);
39+ section = buf;
40+ }
41+
42+ switch_to_section (get_section (section, 0, NULL));
43+ assemble_align (POINTER_SIZE);
44+ fputs ("\t.word\t", asm_out_file);
45+ output_addr_const (asm_out_file, symbol);
46+ fputs ("\n", asm_out_file);
47+}
48+
49+/* Output an element in the table of global destructors. */
50+void
51+microblaze_asm_destructor (rtx symbol, int priority)
52+{
53+ const char *section = ".dtors";
54+ char buf[16];
55+ if (priority != DEFAULT_INIT_PRIORITY)
56+ {
57+ sprintf (buf, ".dtors.%.5u",
58+ /* Invert the numbering so the linker puts us in the proper
59+ order; constructors are run from right to left, and the
60+ linker sorts in increasing order. */
61+ MAX_INIT_PRIORITY - priority);
62+ section = buf;
63+ }
64+
65+ switch_to_section (get_section (section, 0, NULL));
66+ assemble_align (POINTER_SIZE);
67+ fputs ("\t.word\t", asm_out_file);
68+ output_addr_const (asm_out_file, symbol);
69+ fputs ("\n", asm_out_file);
70+}
71+
72 /* Emit either a label, .comm, or .lcomm directive, and mark that the symbol
73 is used, so that we don't emit an .extern for it in
74 microblaze_asm_file_end. */
75@@ -3985,6 +4032,12 @@ microblaze_starting_frame_offset (void)
76 #undef TARGET_ATTRIBUTE_TABLE
77 #define TARGET_ATTRIBUTE_TABLE microblaze_attribute_table
78
79+#undef TARGET_ASM_CONSTRUCTOR
80+#define TARGET_ASM_CONSTRUCTOR microblaze_asm_constructor
81+
82+#undef TARGET_ASM_DESTRUCTOR
83+#define TARGET_ASM_DESTRUCTOR microblaze_asm_destructor
84+
85 #undef TARGET_IN_SMALL_DATA_P
86 #define TARGET_IN_SMALL_DATA_P microblaze_elf_in_small_data_p
87
88--
892.34.1
90
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0015-Add-optimized-lshrsi3-When-barrel-shifter-is-not-pre.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0015-Add-optimized-lshrsi3-When-barrel-shifter-is-not-pre.patch
new file mode 100644
index 00000000..fac95b7b
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0015-Add-optimized-lshrsi3-When-barrel-shifter-is-not-pre.patch
@@ -0,0 +1,81 @@
1From d0f1a493d130e06816df4d11f31421a8691761e0 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Tue, 17 Jan 2017 15:23:57 +0530
4Subject: [PATCH 15/54] Add optimized lshrsi3 When barrel shifter is not
5 present, the immediate value is greater than #5 and optimization is -OS, the
6 compiler will generate shift operation using loop.
7
8Changelog
9
102013-11-26 David Holsgrove <david.holsgrove@xilinx.com>
11
12 * gcc/config/microblaze/microblaze.md: Add size optimized lshrsi3 insn
13
14ChangeLog/testsuite
15
162014-02-12 David Holsgrove <david.holsgrove@xilinx.com>
17
18 * gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c: New test.
19
20Signed-off-by:Nagaraju <nmekala@xilix.com>
21Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
22---
23 gcc/config/microblaze/microblaze.md | 21 +++++++++++++++++++
24 .../microblaze/others/lshrsi_Os_1.c | 13 ++++++++++++
25 2 files changed, 34 insertions(+)
26 create mode 100644 gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c
27
28diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
29index 4f20b8efe33..5d65ad84449 100644
30--- a/gcc/config/microblaze/microblaze.md
31+++ b/gcc/config/microblaze/microblaze.md
32@@ -1618,6 +1618,27 @@
33 (set_attr "length" "4,4")]
34 )
35
36+(define_insn "*lshrsi3_with_size_opt"
37+ [(set (match_operand:SI 0 "register_operand" "=&d")
38+ (lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
39+ (match_operand:SI 2 "immediate_operand" "I")))]
40+ "(INTVAL (operands[2]) > 5 && optimize_size)"
41+ {
42+ operands[3] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
43+
44+ output_asm_insn ("ori\t%3,r0,%2", operands);
45+ if (REGNO (operands[0]) != REGNO (operands[1]))
46+ output_asm_insn ("addk\t%0,%1,r0", operands);
47+
48+ output_asm_insn ("addik\t%3,%3,-1", operands);
49+ output_asm_insn ("bneid\t%3,.-4", operands);
50+ return "srl\t%0,%0";
51+ }
52+ [(set_attr "type" "multi")
53+ (set_attr "mode" "SI")
54+ (set_attr "length" "20")]
55+)
56+
57 (define_insn "*lshrsi_inline"
58 [(set (match_operand:SI 0 "register_operand" "=&d")
59 (lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
60diff --git a/gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c b/gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c
61new file mode 100644
62index 00000000000..32a3be7c76a
63--- /dev/null
64+++ b/gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c
65@@ -0,0 +1,13 @@
66+/* { dg-options "-Os -mno-xl-barrel-shift" } */
67+
68+void testfunc(void)
69+{
70+ unsigned volatile int z = 8192;
71+ z >>= 8;
72+}
73+/* { dg-final { scan-assembler-not "\bsrli" } } */
74+/* { dg-final { scan-assembler "\ori\tr18,r0" } } */
75+/* { dg-final { scan-assembler "addk\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0" } } */
76+/* { dg-final { scan-assembler "addik\tr18,r18,-1" } } */
77+/* { dg-final { scan-assembler "bneid\tr18,.-4" } } */
78+/* { dg-final { scan-assembler "\srl\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])" } } */
79--
802.34.1
81
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0016-Add-cbranchsi4_reg-This-patch-optimizes-the-generati.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0016-Add-cbranchsi4_reg-This-patch-optimizes-the-generati.patch
new file mode 100644
index 00000000..298765dc
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0016-Add-cbranchsi4_reg-This-patch-optimizes-the-generati.patch
@@ -0,0 +1,146 @@
1From e94d406c9fa0d7b99532bd8cf4b2a4580cdb02b7 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Tue, 17 Jan 2017 17:04:37 +0530
4Subject: [PATCH 16/54] Add cbranchsi4_reg This patch optimizes the generation
5 of pcmpne/pcmpeq instruction if the compare instruction has no immediate
6 values.For the immediate values the xor instruction is generated
7
8Signed-off-by: Nagaraju Mekala <nmekala@xilix.com>
9Signed-off-by: Ajit Agarwal <ajitkum@xilinx.com>
10
11ChangeLog:
122015-01-13 Nagaraju Mekala <nmekala@xilix.com>
13 Ajit Agarwal <ajitkum@xilinx.com>
14
15 *microblaze.md (cbranchsi4_reg): New
16 *microblaze.c (microblaze_expand_conditional_branch_reg): New
17
18Conflicts:
19
20 gcc/config/microblaze/microblaze-protos.h
21---
22 gcc/config/microblaze/microblaze-protos.h | 2 +-
23 gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c | 2 +-
24 gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c | 2 +-
25 gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c | 2 +-
26 gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c | 2 +-
27 gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c | 14 +++++++-------
28 gcc/testsuite/gcc.target/microblaze/isa/vanilla.c | 12 ++++++------
29 7 files changed, 18 insertions(+), 18 deletions(-)
30
31diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h
32index 31a6515176b..41557af0f3c 100644
33--- a/gcc/config/microblaze/microblaze-protos.h
34+++ b/gcc/config/microblaze/microblaze-protos.h
35@@ -33,7 +33,7 @@ extern int microblaze_expand_shift (rtx *);
36 extern bool microblaze_expand_move (machine_mode, rtx *);
37 extern bool microblaze_expand_block_move (rtx, rtx, rtx, rtx);
38 extern void microblaze_expand_divide (rtx *);
39-extern void microblaze_expand_conditional_branch (machine_mode, rtx *);
40+extern void microblaze_expand_conditional_branch (enum machine_mode, rtx *);
41 extern void microblaze_expand_conditional_branch_reg (machine_mode, rtx *);
42 extern void microblaze_expand_conditional_branch_sf (rtx *);
43 extern int microblaze_can_use_return_insn (void);
44diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c b/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c
45index 4041a241391..ccc6a461cd9 100644
46--- a/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c
47+++ b/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c
48@@ -6,5 +6,5 @@ void float_func ()
49 {
50 /* { dg-final { scan-assembler "fcmp\.(le|gt)\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
51 if (f2 <= f3)
52- print ("le");
53+ f2 = f3;
54 }
55diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c b/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c
56index 3902b839db9..1dd5fe6c539 100644
57--- a/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c
58+++ b/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c
59@@ -6,5 +6,5 @@ void float_func ()
60 {
61 /* { dg-final { scan-assembler "fcmp\.(lt|ge)\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
62 if (f2 < f3)
63- print ("lt");
64+ f2 = f3;
65 }
66diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c b/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c
67index 8555974dda5..d6f80fb0ec3 100644
68--- a/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c
69+++ b/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c
70@@ -6,5 +6,5 @@ void float_func ()
71 {
72 /* { dg-final { scan-assembler "fcmp\.(eq|ne)\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
73 if (f2 == f3)
74- print ("eq");
75+ f1 = f2 + f3;
76 }
77diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c b/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c
78index 79cc5f9dd8e..d1177249552 100644
79--- a/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c
80+++ b/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c
81@@ -5,5 +5,5 @@ void float_func(float f1, float f2, float f3)
82 /* { dg-final { scan-assembler "fcmp\.eq\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
83 /* { dg-final { scan-assembler "fcmp\.le\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
84 if(f1==f2 && f1<=f3)
85- print ("f1 eq f2 && f1 le f3");
86+ f2 = f3;
87 }
88diff --git a/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c b/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c
89index ebfb170ecee..75822977ef8 100644
90--- a/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c
91+++ b/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c
92@@ -5,17 +5,17 @@ volatile float f1, f2, f3;
93 void float_func ()
94 {
95 /* { dg-final { scan-assembler-not "fcmp" } } */
96- if (f2 <= f3)
97- print ("le");
98+ if (f2 <= f3)
99+ f1 = f3;
100 else if (f2 == f3)
101- print ("eq");
102+ f1 = f3;
103 else if (f2 < f3)
104- print ("lt");
105+ f1 = f3;
106 else if (f2 > f3)
107- print ("gt");
108+ f1 = f3;
109 else if (f2 >= f3)
110- print ("ge");
111+ f1 = f3;
112 else if (f2 != f3)
113- print ("ne");
114+ f1 = f3;
115
116 }
117diff --git a/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c b/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c
118index 1d6ba807b12..532c035adfd 100644
119--- a/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c
120+++ b/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c
121@@ -74,16 +74,16 @@ void float_cmp_func ()
122 {
123 /* { dg-final { scan-assembler-not "fcmp" } } */
124 if (f2 <= f3)
125- print ("le");
126+ f1 = f3;
127 else if (f2 == f3)
128- print ("eq");
129+ f1 = f3;
130 else if (f2 < f3)
131- print ("lt");
132+ f1 = f3;
133 else if (f2 > f3)
134- print ("gt");
135+ f1 = f3;
136 else if (f2 >= f3)
137- print ("ge");
138+ f1 = f3;
139 else if (f2 != f3)
140- print ("ne");
141+ f1 = f3;
142
143 }
144--
1452.34.1
146
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0017-Inline-Expansion-of-fsqrt-builtin.-The-changes-are-m.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0017-Inline-Expansion-of-fsqrt-builtin.-The-changes-are-m.patch
new file mode 100644
index 00000000..91ca87fc
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0017-Inline-Expansion-of-fsqrt-builtin.-The-changes-are-m.patch
@@ -0,0 +1,58 @@
1From 0760cd661f6c09cda8327288f79314319a0b9b14 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Tue, 17 Jan 2017 17:11:04 +0530
4Subject: [PATCH 17/54] Inline Expansion of fsqrt builtin. The changes are made
5 in the patch for the inline expansion of the fsqrt builtin with fqrt
6 instruction. The sqrt math function takes double as argument and return
7 double as argument. The pattern is selected while expanding the unary op
8 through expand_unop which passes DFmode and the DFmode pattern was not there
9 returning zero. Thus the sqrt math function is not inlined and expanded. The
10 pattern with DFmode argument is added. Also the source and destination
11 argument is not same the DF through two different consecutive registers with
12 lower 32 bit is the argument passed to sqrt and the higher 32 bit is zero. If
13 the source and destinations are different the DFmode 64 bits registers is not
14 set properly giving the problem in runtime. Such changes are taken care in
15 the implementation of the pattern for DFmode for inline expansion of the
16 sqrt.
17
18ChangeLog:
192015-06-16 Ajit Agarwal <ajitkum@xilinx.com>
20 Nagaraju Mekala <nmekala@xilinx.com>
21
22 * config/microblaze/microblaze.md (sqrtdf2): New
23 pattern.
24
25Signed-off-by:Ajit Agarwal ajitkum@xilinx.com
26 Nagaraju Mekala nmekala@xilinx.com
27---
28 gcc/config/microblaze/microblaze.md | 14 ++++++++++++++
29 1 file changed, 14 insertions(+)
30
31diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
32index 5d65ad84449..0597ed8d75a 100644
33--- a/gcc/config/microblaze/microblaze.md
34+++ b/gcc/config/microblaze/microblaze.md
35@@ -451,6 +451,20 @@
36 (set_attr "mode" "SF")
37 (set_attr "length" "4")])
38
39+(define_insn "sqrtdf2"
40+ [(set (match_operand:DF 0 "register_operand" "=d")
41+ (sqrt:DF (match_operand:DF 1 "register_operand" "dG")))]
42+ "TARGET_HARD_FLOAT && TARGET_FLOAT_SQRT"
43+ {
44+ if (REGNO (operands[0]) == REGNO (operands[1]))
45+ return "fsqrt\t%0,%1";
46+ else
47+ return "fsqrt\t%0,%1\n\taddk\t%D0,%D1,r0";
48+ }
49+ [(set_attr "type" "fsqrt")
50+ (set_attr "mode" "SF")
51+ (set_attr "length" "4")])
52+
53 (define_insn "fix_truncsfsi2"
54 [(set (match_operand:SI 0 "register_operand" "=d")
55 (fix:SI (match_operand:SF 1 "register_operand" "d")))]
56--
572.34.1
58
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0018-microblaze.md-Improve-adddi3-and-subdi3-insn-definit.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0018-microblaze.md-Improve-adddi3-and-subdi3-insn-definit.patch
new file mode 100644
index 00000000..f388e9b5
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0018-microblaze.md-Improve-adddi3-and-subdi3-insn-definit.patch
@@ -0,0 +1,63 @@
1From 0a7299e82a8f463e9e7cd6297c5bdc0aac3a0ec4 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Tue, 17 Jan 2017 18:07:24 +0530
4Subject: [PATCH 18/54] microblaze.md: Improve 'adddi3' and 'subdi3' insn
5 definitions Change adddi3 to handle DI immediates as the second operand, this
6 requires modification to the output template however reduces the need to
7 specify seperate templates for 16-bit positive/negative immediate operands.
8 The use of 32-bit immediates for the addi and addic instructions is handled
9 by the assembler, which will emit the imm instructions when required. This
10 conveniently handles the optimizable cases where the immediate constant value
11 does not need the higher half words of the operands upper/lower words.
12
13Change the constraints of the subdi3 instruction definition such that it
14does not match the second operand as an immediate value. This is because
15there is no definition to handle this case nor is it possible to
16implement purely with instructions as microblaze does not provide an
17instruction to perform a forward arithmetic subtraction (it only
18provides reverse 'rD = IMM - rA').
19
20Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
21---
22 gcc/config/microblaze/microblaze.md | 13 ++++++-------
23 1 file changed, 6 insertions(+), 7 deletions(-)
24
25diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
26index 0597ed8d75a..498926a4a75 100644
27--- a/gcc/config/microblaze/microblaze.md
28+++ b/gcc/config/microblaze/microblaze.md
29@@ -502,17 +502,16 @@
30 ;; Adding 2 DI operands in register or reg/imm
31
32 (define_insn "adddi3"
33- [(set (match_operand:DI 0 "register_operand" "=d,d,d")
34- (plus:DI (match_operand:DI 1 "register_operand" "%d,d,d")
35- (match_operand:DI 2 "arith_operand32" "d,P,N")))]
36+ [(set (match_operand:DI 0 "register_operand" "=d,d")
37+ (plus:DI (match_operand:DI 1 "register_operand" "%d,d")
38+ (match_operand:DI 2 "arith_operand" "d,i")))]
39 ""
40 "@
41 add\t%L0,%L1,%L2\;addc\t%M0,%M1,%M2
42- addi\t%L0,%L1,%2\;addc\t%M0,%M1,r0
43- addi\t%L0,%L1,%2\;addc\t%M0,%M1,r0\;addi\t%M0,%M0,-1"
44+ addi\t%L0,%L1,%j2\;addic\t%M0,%M1,%h2"
45 [(set_attr "type" "darith")
46 (set_attr "mode" "DI")
47- (set_attr "length" "8,8,12")])
48+ (set_attr "length" "8,8")])
49
50 ;;----------------------------------------------------------------
51 ;; Subtraction
52@@ -549,7 +548,7 @@
53 (define_insn "subdi3"
54 [(set (match_operand:DI 0 "register_operand" "=&d")
55 (minus:DI (match_operand:DI 1 "register_operand" "d")
56- (match_operand:DI 2 "arith_operand32" "d")))]
57+ (match_operand:DI 2 "register_operand" "d")))]
58 ""
59 "rsub\t%L0,%L2,%L1\;rsubc\t%M0,%M2,%M1"
60 [(set_attr "type" "darith")
61--
622.34.1
63
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0019-Update-ashlsi3-movsf-patterns-This-patch-removes-the.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0019-Update-ashlsi3-movsf-patterns-This-patch-removes-the.patch
new file mode 100644
index 00000000..0f388f70
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0019-Update-ashlsi3-movsf-patterns-This-patch-removes-the.patch
@@ -0,0 +1,75 @@
1From a969ab3f04de077eca6d928dd651e3c6b042367d Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Tue, 17 Jan 2017 18:18:41 +0530
4Subject: [PATCH 19/54] Update ashlsi3 & movsf patterns This patch removes the
5 use of HOST_WIDE_INT_PRINT_HEX macro in print_operand of
6 ashlsi3_with_mul_nodelay,ashlsi3_with_mul_delay and movsf_internal patterns
7 beacuse HOST_WIDE_INT_PRINT_HEX is generating 64-bit value which our
8 instruction doesn't support so using gen_int_mode function
9
10Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
11 :Ajit Agarwal <ajitkum@xilinx.com>
12
13ChangeLog:
142016-01-07 Nagaraju Mekala <nmekala@xilix.com>
15 Ajit Agarwal <ajitkum@xilinx.com>
16
17 *microblaze.md (ashlsi3_with_mul_nodelay,
18 ashlsi3_with_mul_delay,
19 movsf_internal):
20 Updated the patterns to use gen_int_mode function
21 *microblaze.cc (print_operand):
22 updated the 'F' case to use "unsinged int" instead
23 of HOST_WIDE_INT_PRINT_HEX
24
25Conflicts:
26 gcc/config/microblaze/microblaze.c
27---
28 gcc/config/microblaze/microblaze.cc | 2 +-
29 gcc/config/microblaze/microblaze.md | 10 ++++++++--
30 2 files changed, 9 insertions(+), 3 deletions(-)
31
32diff --git a/gcc/config/microblaze/microblaze.cc b/gcc/config/microblaze/microblaze.cc
33index 3fb402b87d4..ff64e0ca342 100644
34--- a/gcc/config/microblaze/microblaze.cc
35+++ b/gcc/config/microblaze/microblaze.cc
36@@ -2474,7 +2474,7 @@ print_operand (FILE * file, rtx op, int letter)
37 unsigned long value_long;
38 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op),
39 value_long);
40- fprintf (file, "0x%lx", value_long);
41+ fprintf (file, "0x%08x", (unsigned int) value_long);
42 }
43 else
44 {
45diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
46index 498926a4a75..0448101de8a 100644
47--- a/gcc/config/microblaze/microblaze.md
48+++ b/gcc/config/microblaze/microblaze.md
49@@ -1368,7 +1368,10 @@
50 (match_operand:SI 2 "immediate_operand" "I")))]
51 "!TARGET_SOFT_MUL
52 && ((1 << INTVAL (operands[2])) <= 32767 && (1 << INTVAL (operands[2])) >= -32768)"
53- "muli\t%0,%1,%m2"
54+ {
55+ operands[2] = gen_int_mode (1 << INTVAL (operands[2]), SImode);
56+ return "muli\t%0,%1,%2";
57+ }
58 ;; This MUL will not generate an imm. Can go into a delay slot.
59 [(set_attr "type" "arith")
60 (set_attr "mode" "SI")
61@@ -1380,7 +1383,10 @@
62 (ashift:SI (match_operand:SI 1 "register_operand" "d")
63 (match_operand:SI 2 "immediate_operand" "I")))]
64 "!TARGET_SOFT_MUL"
65- "muli\t%0,%1,%m2"
66+ {
67+ operands[2] = gen_int_mode (1 << INTVAL (operands[2]), SImode);
68+ return "muli\t%0,%1,%2";
69+ }
70 ;; This MUL will generate an IMM. Cannot go into a delay slot
71 [(set_attr "type" "no_delay_arith")
72 (set_attr "mode" "SI")
73--
742.34.1
75
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0020-8-stage-pipeline-for-microblaze-This-patch-adds-the-.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0020-8-stage-pipeline-for-microblaze-This-patch-adds-the-.patch
new file mode 100644
index 00000000..002e60be
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0020-8-stage-pipeline-for-microblaze-This-patch-adds-the-.patch
@@ -0,0 +1,177 @@
1From 21daca8e01515b2e73463adbf9488b63bb0ccf54 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Mon, 12 Sep 2022 21:05:51 +0530
4Subject: [PATCH 20/54] 8-stage pipeline for microblaze This patch adds the
5 support for the 8-stage pipeline. The new 8-stage pipeline reduces the
6 latencies of float & integer division drastically
7
8Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
9---
10 gcc/config/microblaze/microblaze.cc | 11 ++++
11 gcc/config/microblaze/microblaze.h | 3 +-
12 gcc/config/microblaze/microblaze.md | 79 +++++++++++++++++++++++++++-
13 gcc/config/microblaze/microblaze.opt | 4 ++
14 4 files changed, 94 insertions(+), 3 deletions(-)
15
16diff --git a/gcc/config/microblaze/microblaze.cc b/gcc/config/microblaze/microblaze.cc
17index ff64e0ca342..a58a5b2a1b0 100644
18--- a/gcc/config/microblaze/microblaze.cc
19+++ b/gcc/config/microblaze/microblaze.cc
20@@ -1846,6 +1846,17 @@ microblaze_option_override (void)
21 "%<-mcpu=v8.30.a%>");
22 TARGET_REORDER = 0;
23 }
24+ ver = microblaze_version_to_int("v10.0");
25+ if (ver < 0)
26+ {
27+ if (TARGET_AREA_OPTIMIZED_2)
28+ warning (0, "-mxl-frequency can be used only with -mcpu=v10.0 or greater");
29+ }
30+ else
31+ {
32+ if (TARGET_AREA_OPTIMIZED_2)
33+ microblaze_pipe = MICROBLAZE_PIPE_8;
34+ }
35
36 if (TARGET_MULTIPLY_HIGH && TARGET_SOFT_MUL)
37 error ("%<-mxl-multiply-high%> requires %<-mno-xl-soft-mul%>");
38diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
39index 49e7fbedd5a..e4faa9c681f 100644
40--- a/gcc/config/microblaze/microblaze.h
41+++ b/gcc/config/microblaze/microblaze.h
42@@ -27,7 +27,8 @@
43 enum pipeline_type
44 {
45 MICROBLAZE_PIPE_3 = 0,
46- MICROBLAZE_PIPE_5 = 1
47+ MICROBLAZE_PIPE_5 = 1,
48+ MICROBLAZE_PIPE_8 = 2
49 };
50
51 #define MICROBLAZE_MASK_NO_UNSAFE_DELAY 0x00000001
52diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
53index 0448101de8a..7a01b28d8f0 100644
54--- a/gcc/config/microblaze/microblaze.md
55+++ b/gcc/config/microblaze/microblaze.md
56@@ -35,6 +35,7 @@
57 (R_GOT 20) ;; GOT ptr reg
58 (MB_PIPE_3 0) ;; Microblaze 3-stage pipeline
59 (MB_PIPE_5 1) ;; Microblaze 5-stage pipeline
60+ (MB_PIPE_8 2) ;; Microblaze 8-stage pipeline
61 (UNSPEC_SET_GOT 101) ;;
62 (UNSPEC_GOTOFF 102) ;; GOT offset
63 (UNSPEC_PLT 103) ;; jump table
64@@ -82,7 +83,7 @@
65 ;; bshift Shift operations
66
67 (define_attr "type"
68- "unknown,branch,jump,call,load,store,move,arith,darith,imul,idiv,icmp,multi,nop,no_delay_arith,no_delay_load,no_delay_store,no_delay_imul,no_delay_move,bshift,fadd,frsub,fmul,fdiv,fcmp,fsl,fsqrt,fcvt,trap"
69+ "unknown,branch,jump,call,load,store,move,arith,darith,imul,idiv,icmp,multi,nop,no_delay_arith,no_delay_load,no_delay_store,no_delay_imul,no_delay_move,bshift,fadd,frsub,fmul,fdiv,fcmp,fsl,fsqrt,fcvt,fint,trap"
70 (const_string "unknown"))
71
72 ;; Main data type used by the insn
73@@ -224,6 +225,80 @@
74 ;;-----------------------------------------------------------------
75
76
77+
78+;;----------------------------------------------------------------
79+;; Microblaze 8-stage pipeline description (v10.0 and later)
80+;;----------------------------------------------------------------
81+
82+(define_automaton "mbpipe_8")
83+(define_cpu_unit "mb8_issue,mb8_iu,mb8_wb,mb8_fpu,mb8_fpu_2,mb8_mul,mb8_mul_2,mb8_div,mb8_div_2,mb8_bs,mb8_bs_2" "mbpipe_8")
84+
85+(define_insn_reservation "mb8-integer" 1
86+ (and (eq_attr "type" "branch,jump,call,arith,darith,icmp,nop,no_delay_arith")
87+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
88+ "mb8_issue,mb8_iu,mb8_wb")
89+
90+(define_insn_reservation "mb8-special-move" 2
91+ (and (eq_attr "type" "move")
92+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
93+ "mb8_issue,mb8_iu*2,mb8_wb")
94+
95+(define_insn_reservation "mb8-mem-load" 3
96+ (and (eq_attr "type" "load,no_delay_load")
97+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
98+ "mb8_issue,mb8_iu,mb8_wb")
99+
100+(define_insn_reservation "mb8-mem-store" 1
101+ (and (eq_attr "type" "store,no_delay_store")
102+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
103+ "mb8_issue,mb8_iu,mb8_wb")
104+
105+(define_insn_reservation "mb8-mul" 3
106+ (and (eq_attr "type" "imul,no_delay_imul")
107+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
108+ "mb8_issue,mb8_mul,mb8_mul_2*2,mb8_wb")
109+
110+(define_insn_reservation "mb8-div" 30
111+ (and (eq_attr "type" "idiv")
112+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
113+ "mb8_issue,mb8_div,mb8_div_2*29,mb8_wb")
114+
115+(define_insn_reservation "mb8-bs" 2
116+ (and (eq_attr "type" "bshift")
117+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
118+ "mb8_issue,mb8_bs,mb8_bs_2,mb8_wb")
119+
120+(define_insn_reservation "mb8-fpu-add-sub-mul" 1
121+ (and (eq_attr "type" "fadd,frsub,fmul")
122+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
123+ "mb8_issue,mb8_fpu,mb8_wb")
124+
125+(define_insn_reservation "mb8-fpu-fcmp" 3
126+ (and (eq_attr "type" "fcmp")
127+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
128+ "mb8_issue,mb8_fpu,mb8_fpu*2,mb8_wb")
129+
130+(define_insn_reservation "mb8-fpu-div" 24
131+ (and (eq_attr "type" "fdiv")
132+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
133+ "mb8_issue,mb8_fpu,mb8_fpu_2*23,mb8_wb")
134+
135+(define_insn_reservation "mb8-fpu-sqrt" 23
136+ (and (eq_attr "type" "fsqrt")
137+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
138+ "mb8_issue,mb8_fpu,mb8_fpu_2*22,mb8_wb")
139+
140+(define_insn_reservation "mb8-fpu-fcvt" 1
141+ (and (eq_attr "type" "fcvt")
142+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
143+ "mb8_issue,mb8_fpu,mb8_wb")
144+
145+(define_insn_reservation "mb8-fpu-fint" 2
146+ (and (eq_attr "type" "fint")
147+ (eq (symbol_ref "microblaze_pipe") (const_int MB_PIPE_8)))
148+ "mb8_issue,mb8_fpu,mb8_wb")
149+
150+
151 ;;----------------------------------------------------------------
152 ;; Microblaze 5-stage pipeline description (v5.00.a and later)
153 ;;----------------------------------------------------------------
154@@ -470,7 +545,7 @@
155 (fix:SI (match_operand:SF 1 "register_operand" "d")))]
156 "TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
157 "fint\t%0,%1"
158- [(set_attr "type" "fcvt")
159+ [(set_attr "type" "fint")
160 (set_attr "mode" "SF")
161 (set_attr "length" "4")])
162
163diff --git a/gcc/config/microblaze/microblaze.opt b/gcc/config/microblaze/microblaze.opt
164index dbf6390ef4b..37aaaf9ffda 100644
165--- a/gcc/config/microblaze/microblaze.opt
166+++ b/gcc/config/microblaze/microblaze.opt
167@@ -133,3 +133,7 @@ Data referenced by offset from start of text instead of GOT (with -fPIC/-fPIE).
168
169 mxl-mode-xilkernel
170 Target
171+
172+mxl-frequency
173+Target Mask(AREA_OPTIMIZED_2)
174+Use 8 stage pipeline (frequency optimization)
175--
1762.34.1
177
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0021-Correct-the-const-high-double-immediate-value-with-t.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0021-Correct-the-const-high-double-immediate-value-with-t.patch
new file mode 100644
index 00000000..2e8182d1
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0021-Correct-the-const-high-double-immediate-value-with-t.patch
@@ -0,0 +1,58 @@
1From 1cda2f5772650aa65853e6a3e9d8162498c2f469 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Tue, 13 Sep 2022 11:49:11 +0530
4Subject: [PATCH 21/54] Correct the const high double immediate value with this
5 patch the loading of the DI mode immediate values will be using
6 REAL_VALUE_FROM_CONST_DOUBLE and REAL_VALUE_TO_TARGET_DOUBLE functions, as
7 CONST_DOUBLE_HIGH was returning the sign extension value even of the unsigned
8 long long constants also
9
10Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
11 Ajit Agarwal <ajitkum@xilinx.com>
12---
13 gcc/config/microblaze/microblaze.cc | 6 ++++--
14 gcc/testsuite/gcc.target/microblaze/others/long.c | 9 +++++++++
15 2 files changed, 13 insertions(+), 2 deletions(-)
16 create mode 100644 gcc/testsuite/gcc.target/microblaze/others/long.c
17
18diff --git a/gcc/config/microblaze/microblaze.cc b/gcc/config/microblaze/microblaze.cc
19index a58a5b2a1b0..af5c2371740 100644
20--- a/gcc/config/microblaze/microblaze.cc
21+++ b/gcc/config/microblaze/microblaze.cc
22@@ -2458,14 +2458,16 @@ print_operand (FILE * file, rtx op, int letter)
23 else if (letter == 'h' || letter == 'j')
24 {
25 long val[2];
26+ long l[2];
27 if (code == CONST_DOUBLE)
28 {
29 if (GET_MODE (op) == DFmode)
30 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val);
31 else
32 {
33- val[0] = CONST_DOUBLE_HIGH (op);
34- val[1] = CONST_DOUBLE_LOW (op);
35+ REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), l);
36+ val[1] = l[WORDS_BIG_ENDIAN == 0];
37+ val[0] = l[WORDS_BIG_ENDIAN != 0];
38 }
39 }
40 else if (code == CONST_INT)
41diff --git a/gcc/testsuite/gcc.target/microblaze/others/long.c b/gcc/testsuite/gcc.target/microblaze/others/long.c
42new file mode 100644
43index 00000000000..b6b55d5ad65
44--- /dev/null
45+++ b/gcc/testsuite/gcc.target/microblaze/others/long.c
46@@ -0,0 +1,9 @@
47+#define BASEADDR 0xF0000000ULL
48+int main ()
49+{
50+ unsigned long long start;
51+ start = (unsigned long long) BASEADDR;
52+ return 0;
53+}
54+/* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0,0x00000000" } } */
55+/* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0,0xf0000000" } } */
56--
572.34.1
58
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0022-Fix-internal-compiler-error-with-msmall-divides-This.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0022-Fix-internal-compiler-error-with-msmall-divides-This.patch
new file mode 100644
index 00000000..599bd71e
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0022-Fix-internal-compiler-error-with-msmall-divides-This.patch
@@ -0,0 +1,31 @@
1From a88796930d8ef1b97056217ffdcc9f86326cdc98 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Tue, 13 Sep 2022 11:58:14 +0530
4Subject: [PATCH 22/54] Fix internal compiler error with msmall-divides This
5 patch will fix the internal error microblaze_expand_divide function which
6 come of rtx PLUS where the mem_rtx is of type SI and the operand is of type
7 QImode. This patch modifies the mem_rtx as QImode and Plus as QImode to fix
8 the error.
9
10 Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
11 Ajit Agarwal <ajitkum@xilinx.com>
12---
13 gcc/config/microblaze/microblaze.cc | 2 +-
14 1 file changed, 1 insertion(+), 1 deletion(-)
15
16diff --git a/gcc/config/microblaze/microblaze.cc b/gcc/config/microblaze/microblaze.cc
17index af5c2371740..4967d6a0133 100644
18--- a/gcc/config/microblaze/microblaze.cc
19+++ b/gcc/config/microblaze/microblaze.cc
20@@ -3777,7 +3777,7 @@ microblaze_expand_divide (rtx operands[])
21 emit_insn (gen_ashlsi3_bshift (regt1, operands[1], GEN_INT(4)));
22 emit_insn (gen_addsi3 (regt1, regt1, operands[2]));
23 mem_rtx = gen_rtx_MEM (QImode,
24- gen_rtx_PLUS (Pmode, regt1, div_table_rtx));
25+ gen_rtx_PLUS (QImode, regt1, div_table_rtx));
26
27 insn = emit_insn (gen_zero_extendqisi2(operands[0],mem_rtx));
28 jump = emit_jump_insn_after (gen_jump (div_end_label), insn);
29--
302.34.1
31
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0023-Fix-the-calculation-of-high-word-in-a-long-long-64-b.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0023-Fix-the-calculation-of-high-word-in-a-long-long-64-b.patch
new file mode 100644
index 00000000..65f283ad
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0023-Fix-the-calculation-of-high-word-in-a-long-long-64-b.patch
@@ -0,0 +1,36 @@
1From f9871617fe69a105ebc4aa4838c682bfe40e4f2c Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Tue, 13 Sep 2022 12:03:08 +0530
4Subject: [PATCH 23/54] Fix the calculation of high word in a long long 64-bit
5
6 This patch will change the calculation of high word in a long long 64-bit.
7 Earlier to this patch the high word of long long word (0xF0000000ULL) is
8 coming to be 0xFFFFFFFF and low word is 0xF0000000. Instead the high word
9 should be 0x00000000 and the low word should be 0xF0000000. This patch
10 removes the condition of checking high word = 0 & low word < 0.
11 This check is not required for the correctness of calculating 32-bit high
12 and low words in a 64-bit long long.
13
14 Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
15 Ajit Agarwal <ajitkum@xilinx.com>
16---
17 gcc/config/microblaze/microblaze.cc | 3 ---
18 1 file changed, 3 deletions(-)
19
20diff --git a/gcc/config/microblaze/microblaze.cc b/gcc/config/microblaze/microblaze.cc
21index 4967d6a0133..2d516724acc 100644
22--- a/gcc/config/microblaze/microblaze.cc
23+++ b/gcc/config/microblaze/microblaze.cc
24@@ -2474,9 +2474,6 @@ print_operand (FILE * file, rtx op, int letter)
25 {
26 val[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32;
27 val[1] = INTVAL (op) & 0x00000000ffffffffLL;
28- if (val[0] == 0 && val[1] < 0)
29- val[0] = -1;
30-
31 }
32 fprintf (file, "0x%8.8lx", (letter == 'h') ? val[0] : val[1]);
33 }
34--
352.34.1
36
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0024-this-patch-has-1.Fixed-the-bug-in-version-calculatio.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0024-this-patch-has-1.Fixed-the-bug-in-version-calculatio.patch
new file mode 100644
index 00000000..0356657b
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0024-this-patch-has-1.Fixed-the-bug-in-version-calculatio.patch
@@ -0,0 +1,373 @@
1From a8991be91d79cf0bd17b7d303a10ec5edd7408c6 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Tue, 13 Sep 2022 12:23:54 +0530
4Subject: [PATCH 24/54] this patch has 1.Fixed the bug in version calculation.
5 2.Add new bitfield instructions.
6
7Signed-off-by :Mahesh Bodapati <mbodapat@xilinx.com>
8---
9 gcc/config/microblaze/microblaze.cc | 154 ++++++++++++++--------------
10 gcc/config/microblaze/microblaze.h | 2 +
11 gcc/config/microblaze/microblaze.md | 69 +++++++++++++
12 3 files changed, 147 insertions(+), 78 deletions(-)
13
14diff --git a/gcc/config/microblaze/microblaze.cc b/gcc/config/microblaze/microblaze.cc
15index 2d516724acc..e28ab593c3e 100644
16--- a/gcc/config/microblaze/microblaze.cc
17+++ b/gcc/config/microblaze/microblaze.cc
18@@ -165,6 +165,9 @@ int microblaze_no_unsafe_delay;
19 /* Set to one if the targeted core has the CLZ insn. */
20 int microblaze_has_clz = 0;
21
22+/* Set to one if the targeted core has barrel-shift and cpu > 10.0 */
23+int microblaze_has_bitfield = 0;
24+
25 /* Which CPU pipeline do we use. We haven't really standardized on a CPU
26 version having only a particular type of pipeline. There can still be
27 options on the CPU to scale pipeline features up or down. :(
28@@ -240,6 +243,63 @@ section *sdata2_section;
29 #define TARGET_HAVE_TLS true
30 #endif
31
32+/* Convert a version number of the form "vX.YY.Z" to an integer encoding
33+ for easier range comparison. */
34+static int
35+microblaze_version_to_int (const char *version)
36+{
37+ const char *p, *v;
38+ const char *tmpl = "vXX.YY.Z";
39+ int iver1 =0, iver2 =0, iver3 =0;
40+
41+ p = version;
42+ v = tmpl;
43+
44+ while (*p)
45+ {
46+ if (*v == 'X')
47+ { /* Looking for major */
48+ if (*p == '.')
49+ {
50+ *v++;
51+ }
52+ else
53+ {
54+ if (!(*p >= '0' && *p <= '9'))
55+ return -1;
56+ iver1 += (int) (*p - '0');
57+ iver1 *= 1000;
58+ }
59+ }
60+ else if (*v == 'Y')
61+ { /* Looking for minor */
62+ if (!(*p >= '0' && *p <= '9'))
63+ return -1;
64+ iver2 += (int) (*p - '0');
65+ iver2 *= 10;
66+ }
67+ else if (*v == 'Z')
68+ { /* Looking for compat */
69+ if (!(*p >= 'a' && *p <= 'z'))
70+ return -1;
71+ iver3 = ((int) (*p)) - 96;
72+ }
73+ else
74+ {
75+ if (*p != *v)
76+ return -1;
77+ }
78+
79+ v++;
80+ p++;
81+ }
82+
83+ if (*p)
84+ return -1;
85+
86+ return iver1 + iver2 + iver3;
87+}
88+
89 /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant. */
90 static bool
91 microblaze_const_double_ok (rtx op, machine_mode mode)
92@@ -1344,8 +1404,7 @@ microblaze_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED,
93 {
94 if (TARGET_BARREL_SHIFT)
95 {
96- if (MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v5.00.a")
97- >= 0)
98+ if (microblaze_version_to_int(microblaze_select_cpu) >= microblaze_version_to_int("v5.00.a"))
99 *total = COSTS_N_INSNS (1);
100 else
101 *total = COSTS_N_INSNS (2);
102@@ -1406,8 +1465,7 @@ microblaze_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED,
103 }
104 else if (!TARGET_SOFT_MUL)
105 {
106- if (MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v5.00.a")
107- >= 0)
108+ if (microblaze_version_to_int(microblaze_select_cpu) >= microblaze_version_to_int("v5.00.a"))
109 *total = COSTS_N_INSNS (1);
110 else
111 *total = COSTS_N_INSNS (3);
112@@ -1680,72 +1738,13 @@ function_arg_partial_bytes (cumulative_args_t cum_v,
113 return 0;
114 }
115
116-/* Convert a version number of the form "vX.YY.Z" to an integer encoding
117- for easier range comparison. */
118-static int
119-microblaze_version_to_int (const char *version)
120-{
121- const char *p, *v;
122- const char *tmpl = "vXX.YY.Z";
123- int iver = 0;
124-
125- p = version;
126- v = tmpl;
127-
128- while (*p)
129- {
130- if (*v == 'X')
131- { /* Looking for major */
132- if (*p == '.')
133- {
134- v++;
135- }
136- else
137- {
138- if (!(*p >= '0' && *p <= '9'))
139- return -1;
140- iver += (int) (*p - '0');
141- iver *= 10;
142- }
143- }
144- else if (*v == 'Y')
145- { /* Looking for minor */
146- if (!(*p >= '0' && *p <= '9'))
147- return -1;
148- iver += (int) (*p - '0');
149- iver *= 10;
150- }
151- else if (*v == 'Z')
152- { /* Looking for compat */
153- if (!(*p >= 'a' && *p <= 'z'))
154- return -1;
155- iver *= 10;
156- iver += (int) (*p - 'a');
157- }
158- else
159- {
160- if (*p != *v)
161- return -1;
162- }
163-
164- v++;
165- p++;
166- }
167-
168- if (*p)
169- return -1;
170-
171- return iver;
172-}
173-
174-
175 static void
176 microblaze_option_override (void)
177 {
178 int i, start;
179 int regno;
180 machine_mode mode;
181- int ver;
182+ int ver,ver_int;
183
184 microblaze_section_threshold = (OPTION_SET_P (g_switch_value)
185 ? g_switch_value
186@@ -1766,13 +1765,13 @@ microblaze_option_override (void)
187 /* Check the MicroBlaze CPU version for any special action to be done. */
188 if (microblaze_select_cpu == NULL)
189 microblaze_select_cpu = MICROBLAZE_DEFAULT_CPU;
190- ver = microblaze_version_to_int (microblaze_select_cpu);
191- if (ver == -1)
192+ ver_int = microblaze_version_to_int (microblaze_select_cpu);
193+ if (ver_int == -1)
194 {
195 error ("%qs is an invalid argument to %<-mcpu=%>", microblaze_select_cpu);
196 }
197
198- ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v3.00.a");
199+ ver = ver_int - microblaze_version_to_int("v3.00.a");
200 if (ver < 0)
201 {
202 /* No hardware exceptions in earlier versions. So no worries. */
203@@ -1783,8 +1782,7 @@ microblaze_option_override (void)
204 microblaze_pipe = MICROBLAZE_PIPE_3;
205 }
206 else if (ver == 0
207- || (MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v4.00.b")
208- == 0))
209+ || (ver_int == microblaze_version_to_int("v4.00.b")))
210 {
211 #if 0
212 microblaze_select_flags |= (MICROBLAZE_MASK_NO_UNSAFE_DELAY);
213@@ -1801,11 +1799,9 @@ microblaze_option_override (void)
214 #endif
215 microblaze_no_unsafe_delay = 0;
216 microblaze_pipe = MICROBLAZE_PIPE_5;
217- if (MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v5.00.a") == 0
218- || MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu,
219- "v5.00.b") == 0
220- || MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu,
221- "v5.00.c") == 0)
222+ if ((ver_int == microblaze_version_to_int("v5.00.a"))
223+ || (ver_int == microblaze_version_to_int("v5.00.b"))
224+ || (ver_int == microblaze_version_to_int("v5.00.c")))
225 {
226 /* Pattern compares are to be turned on by default only when
227 compiling for MB v5.00.'z'. */
228@@ -1813,7 +1809,7 @@ microblaze_option_override (void)
229 }
230 }
231
232- ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v6.00.a");
233+ ver = ver_int - microblaze_version_to_int("v6.00.a");
234 if (ver < 0)
235 {
236 if (TARGET_MULTIPLY_HIGH)
237@@ -1822,7 +1818,7 @@ microblaze_option_override (void)
238 "%<-mcpu=v6.00.a%> or greater");
239 }
240
241- ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v8.10.a");
242+ ver = ver_int - microblaze_version_to_int("v8.10.a");
243 microblaze_has_clz = 1;
244 if (ver < 0)
245 {
246@@ -1831,7 +1827,7 @@ microblaze_option_override (void)
247 }
248
249 /* TARGET_REORDER defaults to 2 if -mxl-reorder not specified. */
250- ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v8.30.a");
251+ ver = ver_int - microblaze_version_to_int("v8.30.a");
252 if (ver < 0)
253 {
254 if (TARGET_REORDER == 1)
255@@ -1846,7 +1842,7 @@ microblaze_option_override (void)
256 "%<-mcpu=v8.30.a%>");
257 TARGET_REORDER = 0;
258 }
259- ver = microblaze_version_to_int("v10.0");
260+ ver = ver_int - microblaze_version_to_int("v10.0");
261 if (ver < 0)
262 {
263 if (TARGET_AREA_OPTIMIZED_2)
264@@ -1856,6 +1852,8 @@ microblaze_option_override (void)
265 {
266 if (TARGET_AREA_OPTIMIZED_2)
267 microblaze_pipe = MICROBLAZE_PIPE_8;
268+ if (TARGET_BARREL_SHIFT)
269+ microblaze_has_bitfield = 1;
270 }
271
272 if (TARGET_MULTIPLY_HIGH && TARGET_SOFT_MUL)
273diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
274index e4faa9c681f..94d96bf6b5d 100644
275--- a/gcc/config/microblaze/microblaze.h
276+++ b/gcc/config/microblaze/microblaze.h
277@@ -44,6 +44,7 @@ extern int microblaze_debugger_regno[];
278
279 extern int microblaze_no_unsafe_delay;
280 extern int microblaze_has_clz;
281+extern int microblaze_has_bitfield;
282 extern enum pipeline_type microblaze_pipe;
283
284 #define OBJECT_FORMAT_ELF
285@@ -63,6 +64,7 @@ extern enum pipeline_type microblaze_pipe;
286 /* Do we have CLZ? */
287 #define TARGET_HAS_CLZ (TARGET_PATTERN_COMPARE && microblaze_has_clz)
288
289+#define TARGET_HAS_BITFIELD (TARGET_BARREL_SHIFT && microblaze_has_bitfield)
290 /* The default is to support PIC. */
291 #define TARGET_SUPPORTS_PIC 1
292
293diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
294index 7a01b28d8f0..a76287ab4fd 100644
295--- a/gcc/config/microblaze/microblaze.md
296+++ b/gcc/config/microblaze/microblaze.md
297@@ -2491,4 +2491,73 @@
298 DONE;
299 }")
300
301+(define_expand "extvsi"
302+ [(set (match_operand:SI 0 "register_operand" "r")
303+ (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
304+ (match_operand:SI 2 "immediate_operand" "I")
305+ (match_operand:SI 3 "immediate_operand" "I")))]
306+"TARGET_HAS_BITFIELD"
307+"
308+{
309+ unsigned HOST_WIDE_INT len = UINTVAL (operands[2]);
310+ unsigned HOST_WIDE_INT pos = UINTVAL (operands[3]);
311+
312+ if ((len == 0) || (pos + len > 32) )
313+ FAIL;
314+
315+ ;;if (!register_operand (operands[1], VOIDmode))
316+ ;; FAIL;
317+ if (operands[0] == operands[1])
318+ FAIL;
319+ if (GET_CODE (operands[1]) == ASHIFT)
320+ FAIL;
321+;; operands[2] = GEN_INT(INTVAL(operands[2])+1 );
322+ emit_insn (gen_extv_32 (operands[0], operands[1],
323+ operands[2], operands[3]));
324+ DONE;
325+}")
326+
327+(define_insn "extv_32"
328+ [(set (match_operand:SI 0 "register_operand" "=r")
329+ (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
330+ (match_operand:SI 2 "immediate_operand" "I")
331+ (match_operand:SI 3 "immediate_operand" "I")))]
332+ "TARGET_HAS_BITFIELD && (UINTVAL (operands[2]) > 0)
333+ && ((UINTVAL (operands[2]) + UINTVAL (operands[3])) <= 32)"
334+ "bsefi %0,%1,%2,%3"
335+ [(set_attr "type" "bshift")
336+ (set_attr "length" "4")])
337+
338+(define_expand "insvsi"
339+ [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
340+ (match_operand:SI 1 "immediate_operand" "I")
341+ (match_operand:SI 2 "immediate_operand" "I"))
342+ (match_operand:SI 3 "register_operand" "r"))]
343+ "TARGET_HAS_BITFIELD"
344+ "
345+{
346+ unsigned HOST_WIDE_INT len = UINTVAL (operands[1]);
347+ unsigned HOST_WIDE_INT pos = UINTVAL (operands[2]);
348+
349+ if (len <= 0 || pos + len > 32)
350+ FAIL;
351+
352+ ;;if (!register_operand (operands[0], VOIDmode))
353+ ;; FAIL;
354+ emit_insn (gen_insv_32 (operands[0], operands[1],
355+ operands[2], operands[3]));
356+ DONE;
357+}")
358+
359+(define_insn "insv_32"
360+ [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
361+ (match_operand:SI 1 "immediate_operand" "I")
362+ (match_operand:SI 2 "immediate_operand" "I"))
363+ (match_operand:SI 3 "register_operand" "r"))]
364+ "TARGET_HAS_BITFIELD && UINTVAL (operands[1]) > 0
365+ && UINTVAL (operands[1]) + UINTVAL (operands[2]) <= 32"
366+ "bsifi %0, %3, %1, %2"
367+ [(set_attr "type" "bshift")
368+ (set_attr "length" "4")])
369+
370 (include "sync.md")
371--
3722.34.1
373
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0025-Fixing-the-issue-with-the-builtin_alloc.-register-r1.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0025-Fixing-the-issue-with-the-builtin_alloc.-register-r1.patch
new file mode 100644
index 00000000..cd286818
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0025-Fixing-the-issue-with-the-builtin_alloc.-register-r1.patch
@@ -0,0 +1,44 @@
1From 85273a514d0ab3b243b947633ab46705a0d946bc Mon Sep 17 00:00:00 2001
2From: Nagaraju Mekala <nmekala@xilix.com>
3Date: Thu, 23 Feb 2017 17:09:04 +0530
4Subject: [PATCH 25/54] Fixing the issue with the builtin_alloc. register r18
5 was not properly handling the stack pattern which was resolved by using free
6 available register
7
8signed-off-by:nagaraju mekala <nmekala@xilinx.com>
9---
10 gcc/config/microblaze/microblaze.md | 8 ++++----
11 1 file changed, 4 insertions(+), 4 deletions(-)
12
13diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
14index a76287ab4fd..12270f135cf 100644
15--- a/gcc/config/microblaze/microblaze.md
16+++ b/gcc/config/microblaze/microblaze.md
17@@ -2075,10 +2075,10 @@
18 ""
19 {
20 rtx retaddr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
21- rtx rtmp = gen_rtx_REG (SImode, R_TMP);
22+ rtx reg = gen_reg_rtx (Pmode);
23 rtx neg_op0;
24
25- emit_move_insn (rtmp, retaddr);
26+ emit_move_insn (reg, retaddr);
27 if (GET_CODE (operands[1]) != CONST_INT)
28 {
29 neg_op0 = gen_reg_rtx (Pmode);
30@@ -2087,9 +2087,9 @@
31 neg_op0 = GEN_INT (- INTVAL (operands[1]));
32
33 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
34- emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), rtmp);
35+ emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), reg);
36 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
37- emit_insn (gen_rtx_CLOBBER (SImode, rtmp));
38+ emit_insn (gen_rtx_CLOBBER (SImode, reg));
39 DONE;
40 }
41 )
42--
432.34.1
44
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0026-Removed-fsqrt-generation-for-double-values.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0026-Removed-fsqrt-generation-for-double-values.patch
new file mode 100644
index 00000000..02cc5a1e
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0026-Removed-fsqrt-generation-for-double-values.patch
@@ -0,0 +1,37 @@
1From aba85eba7bc5cc19edafe54379fb1f1794dc3844 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Mon, 4 Jun 2018 10:10:18 +0530
4Subject: [PATCH 26/54] Removed fsqrt generation for double values.
5
6---
7 gcc/config/microblaze/microblaze.md | 14 --------------
8 1 file changed, 14 deletions(-)
9
10diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
11index 12270f135cf..b05f7da30b4 100644
12--- a/gcc/config/microblaze/microblaze.md
13+++ b/gcc/config/microblaze/microblaze.md
14@@ -526,20 +526,6 @@
15 (set_attr "mode" "SF")
16 (set_attr "length" "4")])
17
18-(define_insn "sqrtdf2"
19- [(set (match_operand:DF 0 "register_operand" "=d")
20- (sqrt:DF (match_operand:DF 1 "register_operand" "dG")))]
21- "TARGET_HARD_FLOAT && TARGET_FLOAT_SQRT"
22- {
23- if (REGNO (operands[0]) == REGNO (operands[1]))
24- return "fsqrt\t%0,%1";
25- else
26- return "fsqrt\t%0,%1\n\taddk\t%D0,%D1,r0";
27- }
28- [(set_attr "type" "fsqrt")
29- (set_attr "mode" "SF")
30- (set_attr "length" "4")])
31-
32 (define_insn "fix_truncsfsi2"
33 [(set (match_operand:SI 0 "register_operand" "=d")
34 (fix:SI (match_operand:SF 1 "register_operand" "d")))]
35--
362.34.1
37
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0027-Intial-commit-of-64-bit-Microblaze.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0027-Intial-commit-of-64-bit-Microblaze.patch
new file mode 100644
index 00000000..c998d5eb
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0027-Intial-commit-of-64-bit-Microblaze.patch
@@ -0,0 +1,784 @@
1From dd3eee641d2bf28216bf02f324cf8b81d4a61e43 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Tue, 13 Sep 2022 13:56:52 +0530
4Subject: [PATCH 27/54] Intial commit of 64-bit Microblaze
5
6 Conflicts:
7 gcc/config/microblaze/microblaze.md
8---
9 gcc/config/microblaze/constraints.md | 6 +
10 gcc/config/microblaze/microblaze-protos.h | 1 +
11 gcc/config/microblaze/microblaze.cc | 109 +++++--
12 gcc/config/microblaze/microblaze.h | 4 +-
13 gcc/config/microblaze/microblaze.md | 352 +++++++++++++++++++++-
14 gcc/config/microblaze/microblaze.opt | 7 +-
15 gcc/config/microblaze/t-microblaze | 7 +-
16 7 files changed, 456 insertions(+), 30 deletions(-)
17
18diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md
19index aae4be73ae3..26742d34980 100644
20--- a/gcc/config/microblaze/constraints.md
21+++ b/gcc/config/microblaze/constraints.md
22@@ -52,6 +52,12 @@
23 (and (match_code "const_int")
24 (match_test "ival > 0 && ival < 0x10000")))
25
26+(define_constraint "K"
27+ "A constant in the range 0xffffff8000000000L to 0x0000007fffffffffL (inclusive)."
28+ (and (match_code "const_int")
29+ (match_test "ival > (long)0xffffff8000000000L && ival < (long)0x0000007fffffffffL")))
30+
31+
32 ;; Define floating point constraints
33
34 (define_constraint "G"
35diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h
36index 41557af0f3c..0e9f783c4a4 100644
37--- a/gcc/config/microblaze/microblaze-protos.h
38+++ b/gcc/config/microblaze/microblaze-protos.h
39@@ -36,6 +36,7 @@ extern void microblaze_expand_divide (rtx *);
40 extern void microblaze_expand_conditional_branch (enum machine_mode, rtx *);
41 extern void microblaze_expand_conditional_branch_reg (machine_mode, rtx *);
42 extern void microblaze_expand_conditional_branch_sf (rtx *);
43+extern void microblaze_expand_conditional_branch_df (rtx *);
44 extern int microblaze_can_use_return_insn (void);
45 extern void print_operand (FILE *, rtx, int);
46 extern void print_operand_address (FILE *, rtx);
47diff --git a/gcc/config/microblaze/microblaze.cc b/gcc/config/microblaze/microblaze.cc
48index e28ab593c3e..7975bc182f2 100644
49--- a/gcc/config/microblaze/microblaze.cc
50+++ b/gcc/config/microblaze/microblaze.cc
51@@ -3438,11 +3438,11 @@ microblaze_expand_move (machine_mode mode, rtx operands[])
52 op0 = operands[0];
53 op1 = operands[1];
54
55- if (!register_operand (op0, SImode)
56- && !register_operand (op1, SImode)
57+ if (!register_operand (op0, mode)
58+ && !register_operand (op1, mode)
59 && (GET_CODE (op1) != CONST_INT || INTVAL (op1) != 0))
60 {
61- rtx temp = force_reg (SImode, op1);
62+ rtx temp = force_reg (mode, op1);
63 emit_move_insn (op0, temp);
64 return true;
65 }
66@@ -3511,12 +3511,12 @@ microblaze_expand_move (machine_mode mode, rtx operands[])
67 && (flag_pic == 2 || microblaze_tls_symbol_p (p0)
68 || !SMALL_INT (p1)))))
69 {
70- rtx temp = force_reg (SImode, p0);
71+ rtx temp = force_reg (mode, p0);
72 rtx temp2 = p1;
73
74 if (flag_pic && reload_in_progress)
75 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
76- emit_move_insn (op0, gen_rtx_PLUS (SImode, temp, temp2));
77+ emit_move_insn (op0, gen_rtx_PLUS (mode, temp, temp2));
78 return true;
79 }
80 }
81@@ -3647,7 +3647,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
82 rtx cmp_op0 = operands[1];
83 rtx cmp_op1 = operands[2];
84 rtx label1 = operands[3];
85- rtx comp_reg = gen_reg_rtx (SImode);
86+ rtx comp_reg = gen_reg_rtx (mode);
87 rtx condition;
88
89 gcc_assert ((GET_CODE (cmp_op0) == REG) || (GET_CODE (cmp_op0) == SUBREG));
90@@ -3656,23 +3656,36 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
91 if (cmp_op1 == const0_rtx)
92 {
93 comp_reg = cmp_op0;
94- condition = gen_rtx_fmt_ee (signed_condition (code), SImode, comp_reg, const0_rtx);
95- emit_jump_insn (gen_condjump (condition, label1));
96+ condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx);
97+ if (mode == SImode)
98+ emit_jump_insn (gen_condjump (condition, label1));
99+ else
100+ emit_jump_insn (gen_long_condjump (condition, label1));
101+
102 }
103
104 else if (code == EQ || code == NE)
105 {
106 /* Use xor for equal/not-equal comparison. */
107- emit_insn (gen_xorsi3 (comp_reg, cmp_op0, cmp_op1));
108- condition = gen_rtx_fmt_ee (signed_condition (code), SImode, comp_reg, const0_rtx);
109- emit_jump_insn (gen_condjump (condition, label1));
110+ if (mode == SImode)
111+ emit_insn (gen_xorsi3 (comp_reg, cmp_op0, cmp_op1));
112+ else
113+ emit_insn (gen_xordi3 (comp_reg, cmp_op0, cmp_op1));
114+ condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx);
115+ if (mode == SImode)
116+ emit_jump_insn (gen_condjump (condition, label1));
117+ else
118+ emit_jump_insn (gen_long_condjump (condition, label1));
119 }
120 else
121 {
122 /* Generate compare and branch in single instruction. */
123 cmp_op1 = force_reg (mode, cmp_op1);
124 condition = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1);
125- emit_jump_insn (gen_branch_compare(condition, cmp_op0, cmp_op1, label1));
126+ if (mode == SImode)
127+ emit_jump_insn (gen_branch_compare(condition, cmp_op0, cmp_op1, label1));
128+ else
129+ emit_jump_insn (gen_long_branch_compare(condition, cmp_op0, cmp_op1, label1));
130 }
131 }
132
133@@ -3683,7 +3696,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
134 rtx cmp_op0 = operands[1];
135 rtx cmp_op1 = operands[2];
136 rtx label1 = operands[3];
137- rtx comp_reg = gen_reg_rtx (SImode);
138+ rtx comp_reg = gen_reg_rtx (mode);
139 rtx condition;
140
141 gcc_assert ((GET_CODE (cmp_op0) == REG)
142@@ -3694,30 +3707,63 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
143 {
144 comp_reg = cmp_op0;
145 condition = gen_rtx_fmt_ee (signed_condition (code),
146- SImode, comp_reg, const0_rtx);
147- emit_jump_insn (gen_condjump (condition, label1));
148+ mode, comp_reg, const0_rtx);
149+ if (mode == SImode)
150+ emit_jump_insn (gen_condjump (condition, label1));
151+ else
152+ emit_jump_insn (gen_long_condjump (condition, label1));
153 }
154 else if (code == EQ)
155 {
156- emit_insn (gen_seq_internal_pat (comp_reg,
157- cmp_op0, cmp_op1));
158- condition = gen_rtx_EQ (SImode, comp_reg, const0_rtx);
159- emit_jump_insn (gen_condjump (condition, label1));
160+ if (mode == SImode)
161+ {
162+ emit_insn (gen_seq_internal_pat (comp_reg, cmp_op0,
163+ cmp_op1));
164+ }
165+ else
166+ {
167+ emit_insn (gen_seq_internal_pat (comp_reg, cmp_op0,
168+ cmp_op1));
169+ }
170+ condition = gen_rtx_EQ (mode, comp_reg, const0_rtx);
171+ if (mode == SImode)
172+ emit_jump_insn (gen_condjump (condition, label1));
173+ else
174+ emit_jump_insn (gen_long_condjump (condition, label1));
175+
176 }
177 else if (code == NE)
178 {
179- emit_insn (gen_sne_internal_pat (comp_reg, cmp_op0,
180- cmp_op1));
181- condition = gen_rtx_NE (SImode, comp_reg, const0_rtx);
182- emit_jump_insn (gen_condjump (condition, label1));
183+ if (mode == SImode)
184+ {
185+ emit_insn (gen_sne_internal_pat (comp_reg, cmp_op0,
186+ cmp_op1));
187+ }
188+ else
189+ {
190+ emit_insn (gen_sne_internal_pat (comp_reg, cmp_op0,
191+ cmp_op1));
192+ }
193+ condition = gen_rtx_NE (mode, comp_reg, const0_rtx);
194+ if (mode == SImode)
195+ emit_jump_insn (gen_condjump (condition, label1));
196+ else
197+ emit_jump_insn (gen_long_condjump (condition, label1));
198 }
199 else
200 {
201 /* Generate compare and branch in single instruction. */
202 cmp_op1 = force_reg (mode, cmp_op1);
203 condition = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1);
204- emit_jump_insn (gen_branch_compare (condition, cmp_op0,
205- cmp_op1, label1));
206+ if (mode == SImode)
207+ emit_jump_insn (gen_branch_compare (condition, cmp_op0,
208+ cmp_op1, label1));
209+ else
210+ {
211+ emit_jump_insn (gen_long_branch_compare (condition, cmp_op0,
212+ cmp_op1, label1));
213+ }
214+
215 }
216 }
217
218@@ -3734,6 +3780,19 @@ microblaze_expand_conditional_branch_sf (rtx operands[])
219 emit_jump_insn (gen_condjump (condition, operands[3]));
220 }
221
222+void
223+microblaze_expand_conditional_branch_df (rtx operands[])
224+{
225+ rtx condition;
226+ rtx cmp_op0 = XEXP (operands[0], 0);
227+ rtx cmp_op1 = XEXP (operands[0], 1);
228+ rtx comp_reg = gen_reg_rtx (DImode);
229+
230+ emit_insn (gen_cstoredf4 (comp_reg, operands[0], cmp_op0, cmp_op1));
231+ condition = gen_rtx_NE (DImode, comp_reg, const0_rtx);
232+ emit_jump_insn (gen_long_condjump (condition, operands[3]));
233+}
234+
235 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
236
237 static bool
238diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
239index 94d96bf6b5d..f35f7075ce3 100644
240--- a/gcc/config/microblaze/microblaze.h
241+++ b/gcc/config/microblaze/microblaze.h
242@@ -102,6 +102,7 @@ extern enum pipeline_type microblaze_pipe;
243 #define ASM_SPEC "\
244 %(target_asm_spec) \
245 %{mbig-endian:-EB} \
246+%{m64:-m64} \
247 %{mlittle-endian:-EL}"
248
249 /* Extra switches sometimes passed to the linker. */
250@@ -110,6 +111,7 @@ extern enum pipeline_type microblaze_pipe;
251 #define LINK_SPEC "%{shared:-shared} -N -relax \
252 %{mbig-endian:-EB --oformat=elf32-microblaze} \
253 %{mlittle-endian:-EL --oformat=elf32-microblazeel} \
254+ %{m64:-EL --oformat=elf64-microblazeel} \
255 %{Zxl-mode-xmdstub:-defsym _TEXT_START_ADDR=0x800} \
256 %{mxl-mode-xmdstub:-defsym _TEXT_START_ADDR=0x800} \
257 %{mxl-gp-opt:%{G*}} %{!mxl-gp-opt: -G 0} \
258@@ -217,7 +219,7 @@ extern enum pipeline_type microblaze_pipe;
259 #define MIN_UNITS_PER_WORD 4
260 #define INT_TYPE_SIZE 32
261 #define SHORT_TYPE_SIZE 16
262-#define LONG_TYPE_SIZE 32
263+#define LONG_TYPE_SIZE 64
264 #define LONG_LONG_TYPE_SIZE 64
265 #define FLOAT_TYPE_SIZE 32
266 #define DOUBLE_TYPE_SIZE 64
267diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
268index b05f7da30b4..3f572fe2351 100644
269--- a/gcc/config/microblaze/microblaze.md
270+++ b/gcc/config/microblaze/microblaze.md
271@@ -497,7 +497,6 @@
272 (set_attr "mode" "SF")
273 (set_attr "length" "4")])
274
275-
276 (define_insn "divsf3"
277 [(set (match_operand:SF 0 "register_operand" "=d")
278 (div:SF (match_operand:SF 1 "register_operand" "d")
279@@ -508,6 +507,7 @@
280 (set_attr "mode" "SF")
281 (set_attr "length" "4")])
282
283+
284 (define_insn "sqrtsf2"
285 [(set (match_operand:SF 0 "register_operand" "=d")
286 (sqrt:SF (match_operand:SF 1 "register_operand" "d")))]
287@@ -562,6 +562,18 @@
288
289 ;; Adding 2 DI operands in register or reg/imm
290
291+(define_insn "adddi3_long"
292+ [(set (match_operand:DI 0 "register_operand" "=d,d")
293+ (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%dJ,dJ")
294+ (match_operand:DI 2 "arith_plus_operand" "d,K")))]
295+ "TARGET_MB_64"
296+ "@
297+ addlk\t%0,%z1,%2
298+ addlik\t%0,%z1,%2"
299+ [(set_attr "type" "arith,arith")
300+ (set_attr "mode" "DI,DI")
301+ (set_attr "length" "4,4")])
302+
303 (define_insn "adddi3"
304 [(set (match_operand:DI 0 "register_operand" "=d,d")
305 (plus:DI (match_operand:DI 1 "register_operand" "%d,d")
306@@ -606,6 +618,18 @@
307 ;; Double Precision Subtraction
308 ;;----------------------------------------------------------------
309
310+(define_insn "subdi3_long"
311+ [(set (match_operand:DI 0 "register_operand" "=d,d")
312+ (minus:DI (match_operand:DI 1 "register_operand" "d,d")
313+ (match_operand:DI 2 "register_operand" "d,n")))]
314+ "TARGET_MB_64"
315+ "@
316+ rsubl\t%0,%2,%1
317+ addlik\t%0,%z1,-%2"
318+ [(set_attr "type" "darith")
319+ (set_attr "mode" "DI,DI")
320+ (set_attr "length" "4,4")])
321+
322 (define_insn "subdi3"
323 [(set (match_operand:DI 0 "register_operand" "=&d")
324 (minus:DI (match_operand:DI 1 "register_operand" "d")
325@@ -795,6 +819,15 @@
326 (set_attr "mode" "SI")
327 (set_attr "length" "4")])
328
329+(define_insn "negdi2_long"
330+ [(set (match_operand:DI 0 "register_operand" "=d")
331+ (neg:DI (match_operand:DI 1 "register_operand" "d")))]
332+ "TARGET_MB_64"
333+ "rsubl\t%0,%1,r0"
334+ [(set_attr "type" "darith")
335+ (set_attr "mode" "DI")
336+ (set_attr "length" "4")])
337+
338 (define_insn "negdi2"
339 [(set (match_operand:DI 0 "register_operand" "=d")
340 (neg:DI (match_operand:DI 1 "register_operand" "d")))]
341@@ -814,6 +847,15 @@
342 (set_attr "mode" "SI")
343 (set_attr "length" "4")])
344
345+(define_insn "one_cmpldi2_long"
346+ [(set (match_operand:DI 0 "register_operand" "=d")
347+ (not:DI (match_operand:DI 1 "register_operand" "d")))]
348+ "TARGET_MB_64"
349+ "xorli\t%0,%1,-1"
350+ [(set_attr "type" "arith")
351+ (set_attr "mode" "DI")
352+ (set_attr "length" "4")])
353+
354 (define_insn "*one_cmpldi2"
355 [(set (match_operand:DI 0 "register_operand" "=d")
356 (not:DI (match_operand:DI 1 "register_operand" "d")))]
357@@ -840,6 +882,20 @@
358 ;; Logical
359 ;;----------------------------------------------------------------
360
361+(define_insn "anddi3"
362+ [(set (match_operand:DI 0 "register_operand" "=d,d")
363+ (and:DI (match_operand:DI 1 "arith_operand" "d,d")
364+ (match_operand:DI 2 "arith_operand" "d,K")))]
365+ "TARGET_MB_64"
366+ "@
367+ andl\t%0,%1,%2
368+ andli\t%0,%1,%2 #andl1"
369+ ;; andli\t%0,%1,%2 #andl3
370+ ;; andli\t%0,%1,%2 #andl2
371+ [(set_attr "type" "arith,arith")
372+ (set_attr "mode" "DI,DI")
373+ (set_attr "length" "4,4")])
374+
375 (define_insn "andsi3"
376 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
377 (and:SI (match_operand:SI 1 "arith_operand" "%d,d,d,d")
378@@ -855,6 +911,18 @@
379 (set_attr "length" "4,8,8,8")])
380
381
382+(define_insn "iordi3"
383+ [(set (match_operand:DI 0 "register_operand" "=d,d")
384+ (ior:DI (match_operand:DI 1 "arith_operand" "d,d")
385+ (match_operand:DI 2 "arith_operand" "d,K")))]
386+ "TARGET_MB_64"
387+ "@
388+ orl\t%0,%1,%2
389+ orli\t%0,%1,%2 #andl1"
390+ [(set_attr "type" "arith,arith")
391+ (set_attr "mode" "DI,DI")
392+ (set_attr "length" "4,4")])
393+
394 (define_insn "iorsi3"
395 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
396 (ior:SI (match_operand:SI 1 "arith_operand" "%d,d,d,d")
397@@ -869,6 +937,19 @@
398 (set_attr "mode" "SI,SI,SI,SI")
399 (set_attr "length" "4,8,8,8")])
400
401+(define_insn "xordi3"
402+ [(set (match_operand:DI 0 "register_operand" "=d,d")
403+ (xor:DI (match_operand:DI 1 "arith_operand" "%d,d")
404+ (match_operand:DI 2 "arith_operand" "d,K")))]
405+ "TARGET_MB_64"
406+ "@
407+ xorl\t%0,%1,%2
408+ xorli\t%0,%1,%2 #andl1"
409+ [(set_attr "type" "arith,arith")
410+ (set_attr "mode" "DI,DI")
411+ (set_attr "length" "4,4")])
412+
413+
414 (define_insn "xorsi3"
415 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
416 (xor:SI (match_operand:SI 1 "arith_operand" "%d,d,d")
417@@ -937,6 +1018,26 @@
418 (set_attr "mode" "SI")
419 (set_attr "length" "4")])
420
421+;;(define_expand "extendqidi2"
422+;; [(set (match_operand:DI 0 "register_operand" "=d")
423+;; (sign_extend:DI (match_operand:QI 1 "general_operand" "d")))]
424+;; "TARGET_MB_64"
425+;; {
426+;; if (GET_CODE (operands[1]) != REG)
427+;; FAIL;
428+;; }
429+;;)
430+
431+
432+;;(define_insn "extendqidi2"
433+;; [(set (match_operand:DI 0 "register_operand" "=d")
434+;; (sign_extend:DI (match_operand:QI 1 "register_operand" "d")))]
435+;; "TARGET_MB_64"
436+;; "sextl8\t%0,%1"
437+;; [(set_attr "type" "arith")
438+;; (set_attr "mode" "DI")
439+;; (set_attr "length" "4")])
440+
441 (define_insn "extendhisi2"
442 [(set (match_operand:SI 0 "register_operand" "=d")
443 (sign_extend:SI (match_operand:HI 1 "register_operand" "d")))]
444@@ -946,6 +1047,16 @@
445 (set_attr "mode" "SI")
446 (set_attr "length" "4")])
447
448+(define_insn "extendhidi2"
449+ [(set (match_operand:DI 0 "register_operand" "=d")
450+ (sign_extend:DI (match_operand:HI 1 "register_operand" "d")))]
451+ "TARGET_MB_64"
452+ "sextl16\t%0,%1"
453+ [(set_attr "type" "arith")
454+ (set_attr "mode" "DI")
455+ (set_attr "length" "4")])
456+
457+
458 ;; Those for integer source operand are ordered
459 ;; widest source type first.
460
461@@ -1009,6 +1120,32 @@
462 )
463
464
465+(define_insn "*movdi_internal_64"
466+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o")
467+ (match_operand:DI 1 "general_operand" " d,K,J,R,o,d,d"))]
468+ "TARGET_MB_64 && (INTVAL(operands[1]) < 0x7fffffffff) && (INTVAL(operands[1]) > 0xffffff8000000000)"
469+ {
470+ switch (which_alternative)
471+ {
472+ case 0:
473+ return "addlk\t%0,%1";
474+ case 1:
475+ return "addlik\t%0,r0,%1";
476+ case 2:
477+ return "addlk\t%0,r0,r0";
478+ case 3:
479+ case 4:
480+ return "lli\t%0,%1";
481+ case 5:
482+ case 6:
483+ return "sli\t%1,%0";
484+ }
485+ return "unreachable";
486+ }
487+ [(set_attr "type" "no_delay_move,no_delay_arith,no_delay_arith,no_delay_load,no_delay_load,no_delay_store,no_delay_store")
488+ (set_attr "mode" "DI")
489+ (set_attr "length" "8,8,8,8,12,8,12")])
490+
491
492 (define_insn "*movdi_internal"
493 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o")
494@@ -1421,6 +1558,36 @@
495 (set_attr "length" "4,4")]
496 )
497
498+;; Barrel shift left
499+(define_expand "ashldi3"
500+ [(set (match_operand:DI 0 "register_operand" "=&d")
501+ (ashift:DI (match_operand:DI 1 "register_operand" "d")
502+ (match_operand:DI 2 "arith_operand" "")))]
503+"TARGET_MB_64"
504+{
505+;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
506+if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
507+ {
508+ emit_insn(gen_ashldi3_long (operands[0], operands[1],operands[2]));
509+ DONE;
510+ }
511+else
512+ FAIL;
513+}
514+)
515+
516+(define_insn "ashldi3_long"
517+ [(set (match_operand:DI 0 "register_operand" "=d,d")
518+ (ashift:DI (match_operand:DI 1 "register_operand" "d,d")
519+ (match_operand:DI 2 "arith_operand" "I,d")))]
520+ "TARGET_MB_64"
521+ "@
522+ bsllli\t%0,%1,%2
523+ bslll\t%0,%1,%2"
524+ [(set_attr "type" "bshift,bshift")
525+ (set_attr "mode" "DI,DI")
526+ (set_attr "length" "4,4")]
527+)
528 ;; The following patterns apply when there is no barrel shifter present
529
530 (define_insn "*ashlsi3_with_mul_delay"
531@@ -1546,6 +1713,36 @@
532 ;;----------------------------------------------------------------
533 ;; 32-bit right shifts
534 ;;----------------------------------------------------------------
535+;; Barrel shift left
536+(define_expand "ashrdi3"
537+ [(set (match_operand:DI 0 "register_operand" "=&d")
538+ (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
539+ (match_operand:DI 2 "arith_operand" "")))]
540+"TARGET_MB_64"
541+{
542+;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
543+if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
544+ {
545+ emit_insn(gen_ashrdi3_long (operands[0], operands[1],operands[2]));
546+ DONE;
547+ }
548+else
549+ FAIL;
550+}
551+)
552+
553+(define_insn "ashrdi3_long"
554+ [(set (match_operand:DI 0 "register_operand" "=d,d")
555+ (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
556+ (match_operand:DI 2 "arith_operand" "I,d")))]
557+ "TARGET_MB_64"
558+ "@
559+ bslrai\t%0,%1,%2
560+ bslra\t%0,%1,%2"
561+ [(set_attr "type" "bshift,bshift")
562+ (set_attr "mode" "DI,DI")
563+ (set_attr "length" "4,4")]
564+ )
565 (define_expand "ashrsi3"
566 [(set (match_operand:SI 0 "register_operand" "=&d")
567 (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
568@@ -1655,6 +1852,36 @@
569 ;;----------------------------------------------------------------
570 ;; 32-bit right shifts (logical)
571 ;;----------------------------------------------------------------
572+;; Barrel shift left
573+(define_expand "lshrdi3"
574+ [(set (match_operand:DI 0 "register_operand" "=&d")
575+ (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
576+ (match_operand:DI 2 "arith_operand" "")))]
577+"TARGET_MB_64"
578+{
579+;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
580+if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
581+ {
582+ emit_insn(gen_lshrdi3_long (operands[0], operands[1],operands[2]));
583+ DONE;
584+ }
585+else
586+ FAIL;
587+}
588+)
589+
590+(define_insn "lshrdi3_long"
591+ [(set (match_operand:DI 0 "register_operand" "=d,d")
592+ (lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
593+ (match_operand:DI 2 "arith_operand" "I,d")))]
594+ "TARGET_MB_64"
595+ "@
596+ bslrli\t%0,%1,%2
597+ bslrl\t%0,%1,%2"
598+ [(set_attr "type" "bshift,bshift")
599+ (set_attr "mode" "DI,DI")
600+ (set_attr "length" "4,4")]
601+ )
602
603 (define_expand "lshrsi3"
604 [(set (match_operand:SI 0 "register_operand" "=&d")
605@@ -1800,6 +2027,8 @@
606 (set_attr "length" "4")]
607 )
608
609+
610+
611 ;;----------------------------------------------------------------
612 ;; Setting a register from an floating point comparison.
613 ;;----------------------------------------------------------------
614@@ -1815,6 +2044,18 @@
615 (set_attr "length" "4")]
616 )
617
618+(define_insn "cstoredf4"
619+ [(set (match_operand:DI 0 "register_operand" "=r")
620+ (match_operator:DI 1 "ordered_comparison_operator"
621+ [(match_operand:DF 2 "register_operand" "r")
622+ (match_operand:DF 3 "register_operand" "r")]))]
623+ "TARGET_MB_64"
624+ "dcmp.%C1\t%0,%3,%2"
625+ [(set_attr "type" "fcmp")
626+ (set_attr "mode" "DF")
627+ (set_attr "length" "4")]
628+)
629+
630 ;;----------------------------------------------------------------
631 ;; Conditional branches
632 ;;----------------------------------------------------------------
633@@ -1927,6 +2168,115 @@
634 (set_attr "length" "12")]
635 )
636
637+
638+(define_expand "cbranchdi4"
639+ [(set (pc)
640+ (if_then_else (match_operator 0 "ordered_comparison_operator"
641+ [(match_operand:DI 1 "register_operand")
642+ (match_operand:DI 2 "arith_operand" "I,i")])
643+ (label_ref (match_operand 3 ""))
644+ (pc)))]
645+ "TARGET_MB_64"
646+{
647+ microblaze_expand_conditional_branch (DImode, operands);
648+ DONE;
649+})
650+
651+(define_expand "cbranchdi4_reg"
652+ [(set (pc)
653+ (if_then_else (match_operator 0 "ordered_comparison_operator"
654+ [(match_operand:DI 1 "register_operand")
655+ (match_operand:DI 2 "register_operand")])
656+ (label_ref (match_operand 3 ""))
657+ (pc)))]
658+ "TARGET_MB_64"
659+{
660+ microblaze_expand_conditional_branch_reg (DImode, operands);
661+ DONE;
662+})
663+
664+(define_expand "cbranchdf4"
665+ [(set (pc)
666+ (if_then_else (match_operator 0 "ordered_comparison_operator"
667+ [(match_operand:DF 1 "register_operand")
668+ (match_operand:DF 2 "register_operand")])
669+ (label_ref (match_operand 3 ""))
670+ (pc)))]
671+ "TARGET_MB_64"
672+{
673+ microblaze_expand_conditional_branch_df (operands);
674+ DONE;
675+
676+})
677+
678+;; Used to implement comparison instructions
679+(define_expand "long_condjump"
680+ [(set (pc)
681+ (if_then_else (match_operand 0)
682+ (label_ref (match_operand 1))
683+ (pc)))])
684+
685+(define_insn "long_branch_zero"
686+ [(set (pc)
687+ (if_then_else (match_operator:DI 0 "ordered_comparison_operator"
688+ [(match_operand:DI 1 "register_operand" "d")
689+ (const_int 0)])
690+ (match_operand:DI 2 "pc_or_label_operand" "")
691+ (match_operand:DI 3 "pc_or_label_operand" "")))
692+ ]
693+ "TARGET_MB_64"
694+ {
695+ if (operands[3] == pc_rtx)
696+ return "beal%C0i%?\t%z1,%2";
697+ else
698+ return "beal%N0i%?\t%z1,%3";
699+ }
700+ [(set_attr "type" "branch")
701+ (set_attr "mode" "none")
702+ (set_attr "length" "4")]
703+)
704+
705+(define_insn "long_branch_compare"
706+ [(set (pc)
707+ (if_then_else (match_operator:DI 0 "cmp_op"
708+ [(match_operand:DI 1 "register_operand" "d")
709+ (match_operand:DI 2 "register_operand" "d")
710+ ])
711+ (label_ref (match_operand 3))
712+ (pc)))
713+ (clobber(reg:DI R_TMP))]
714+ "TARGET_MB_64"
715+ {
716+ operands[4] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
717+ enum rtx_code code = GET_CODE (operands[0]);
718+
719+ if (code == GT || code == LE)
720+ {
721+ output_asm_insn ("cmpl\tr18,%z1,%z2", operands);
722+ code = swap_condition (code);
723+ }
724+ else if (code == GTU || code == LEU)
725+ {
726+ output_asm_insn ("cmplu\tr18,%z1,%z2", operands);
727+ code = swap_condition (code);
728+ }
729+ else if (code == GE || code == LT)
730+ {
731+ output_asm_insn ("cmpl\tr18,%z2,%z1", operands);
732+ }
733+ else if (code == GEU || code == LTU)
734+ {
735+ output_asm_insn ("cmplu\tr18,%z2,%z1", operands);
736+ }
737+
738+ operands[0] = gen_rtx_fmt_ee (signed_condition (code), DImode, operands[4], const0_rtx);
739+ return "beal%C0i%?\tr18,%3";
740+ }
741+ [(set_attr "type" "branch")
742+ (set_attr "mode" "none")
743+ (set_attr "length" "12")]
744+)
745+
746 ;;----------------------------------------------------------------
747 ;; Unconditional branches
748 ;;----------------------------------------------------------------
749diff --git a/gcc/config/microblaze/microblaze.opt b/gcc/config/microblaze/microblaze.opt
750index 37aaaf9ffda..96615a6d2c4 100644
751--- a/gcc/config/microblaze/microblaze.opt
752+++ b/gcc/config/microblaze/microblaze.opt
753@@ -136,4 +136,9 @@ Target
754
755 mxl-frequency
756 Target Mask(AREA_OPTIMIZED_2)
757-Use 8 stage pipeline (frequency optimization)
758+Use 8 stage pipeline (frequency optimization).
759+
760+m64
761+Target Mask(MB_64)
762+MicroBlaze 64-bit mode.
763+
764diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze
765index 7e2fc5dcef8..4c25cfe15e7 100644
766--- a/gcc/config/microblaze/t-microblaze
767+++ b/gcc/config/microblaze/t-microblaze
768@@ -1,8 +1,11 @@
769-MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high mlittle-endian
770-MULTILIB_DIRNAMES = bs m mh le
771+MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high mlittle-endian m64
772+MULTILIB_DIRNAMES = bs m mh le m64
773 MULTILIB_EXCEPTIONS = *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high
774 MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian
775+MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/m64
776 MULTILIB_EXCEPTIONS += mxl-multiply-high/mlittle-endian
777+MULTILIB_EXCEPTIONS += mxl-multiply-high/m64
778+MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64
779
780 # Extra files
781 microblaze-c.o: $(srcdir)/config/microblaze/microblaze-c.cc \
782--
7832.34.1
784
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0028-Intial-commit-for-64bit-MB-sources.-Need-to-cleanup-.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0028-Intial-commit-for-64bit-MB-sources.-Need-to-cleanup-.patch
new file mode 100644
index 00000000..58bb6fd8
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0028-Intial-commit-for-64bit-MB-sources.-Need-to-cleanup-.patch
@@ -0,0 +1,2442 @@
1From fcec4be11de1c646bdcd6dcfc3844b7deb42898e Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Tue, 13 Sep 2022 14:38:48 +0530
4Subject: [PATCH 28/54] Intial commit for 64bit-MB sources. Need to cleanup the
5 code later.
6
7---
8 gcc/config/microblaze/constraints.md | 2 +-
9 gcc/config/microblaze/microblaze-c.cc | 6 +
10 gcc/config/microblaze/microblaze.cc | 216 ++++++---
11 gcc/config/microblaze/microblaze.h | 63 ++-
12 gcc/config/microblaze/microblaze.md | 605 ++++++++++++++++++------
13 gcc/config/microblaze/t-microblaze | 3 +-
14 libgcc/config/microblaze/crti.S | 4 +-
15 libgcc/config/microblaze/crtn.S | 4 +-
16 libgcc/config/microblaze/divdi3.S | 98 ++++
17 libgcc/config/microblaze/divdi3_table.c | 62 +++
18 libgcc/config/microblaze/moddi3.S | 97 ++++
19 libgcc/config/microblaze/muldi3.S | 73 +++
20 libgcc/config/microblaze/t-microblaze | 11 +-
21 libgcc/config/microblaze/udivdi3.S | 107 +++++
22 libgcc/config/microblaze/umoddi3.S | 110 +++++
23 15 files changed, 1229 insertions(+), 232 deletions(-)
24 create mode 100644 libgcc/config/microblaze/divdi3.S
25 create mode 100644 libgcc/config/microblaze/divdi3_table.c
26 create mode 100644 libgcc/config/microblaze/moddi3.S
27 create mode 100644 libgcc/config/microblaze/muldi3.S
28 create mode 100644 libgcc/config/microblaze/udivdi3.S
29 create mode 100644 libgcc/config/microblaze/umoddi3.S
30
31diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md
32index 26742d34980..7bb1e0b4c8d 100644
33--- a/gcc/config/microblaze/constraints.md
34+++ b/gcc/config/microblaze/constraints.md
35@@ -55,7 +55,7 @@
36 (define_constraint "K"
37 "A constant in the range 0xffffff8000000000L to 0x0000007fffffffffL (inclusive)."
38 (and (match_code "const_int")
39- (match_test "ival > (long)0xffffff8000000000L && ival < (long)0x0000007fffffffffL")))
40+ (match_test "ival > (long)-549755813888 && ival < (long)549755813887")))
41
42
43 ;; Define floating point constraints
44diff --git a/gcc/config/microblaze/microblaze-c.cc b/gcc/config/microblaze/microblaze-c.cc
45index 065351ad218..af73de0709c 100644
46--- a/gcc/config/microblaze/microblaze-c.cc
47+++ b/gcc/config/microblaze/microblaze-c.cc
48@@ -100,4 +100,10 @@ microblaze_cpp_define (cpp_reader *pfile)
49 builtin_define ("HAVE_HW_FPU_SQRT");
50 builtin_define ("__HAVE_HW_FPU_SQRT__");
51 }
52+ if (TARGET_MB_64)
53+ {
54+ builtin_define ("__arch64__");
55+ builtin_define ("__microblaze64__");
56+ builtin_define ("__MICROBLAZE64__");
57+ }
58 }
59diff --git a/gcc/config/microblaze/microblaze.cc b/gcc/config/microblaze/microblaze.cc
60index 7975bc182f2..46bbf8a21e7 100644
61--- a/gcc/config/microblaze/microblaze.cc
62+++ b/gcc/config/microblaze/microblaze.cc
63@@ -384,10 +384,10 @@ simple_memory_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
64 {
65 return 1;
66 }
67- else if (GET_CODE (plus0) == REG && GET_CODE (plus1) == REG)
68+ /*else if (GET_CODE (plus0) == REG && GET_CODE (plus1) == REG)
69 {
70 return 1;
71- }
72+ }*/
73 else
74 return 0;
75
76@@ -435,7 +435,7 @@ double_memory_operand (rtx op, machine_mode mode)
77 return 1;
78
79 return memory_address_p ((GET_MODE_CLASS (mode) == MODE_INT
80- ? E_SImode : E_SFmode),
81+ ? Pmode : E_SFmode),
82 plus_constant (Pmode, addr, 4));
83 }
84
85@@ -682,7 +682,7 @@ microblaze_legitimize_tls_address(rtx x, rtx reg)
86 /* Load the addend. */
87 addend = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, x, GEN_INT (TLS_DTPREL)),
88 UNSPEC_TLS);
89- addend = force_reg (SImode, gen_rtx_CONST (SImode, addend));
90+ addend = force_reg (Pmode, gen_rtx_CONST (Pmode, addend));
91 dest = gen_rtx_PLUS (Pmode, dest, addend);
92 break;
93
94@@ -700,7 +700,7 @@ microblaze_classify_unspec (struct microblaze_address_info *info, rtx x)
95
96 if (XINT (x, 1) == UNSPEC_GOTOFF)
97 {
98- info->regA = gen_rtx_REG (SImode, PIC_OFFSET_TABLE_REGNUM);
99+ info->regA = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM);
100 info->type = ADDRESS_GOTOFF;
101 }
102 else if (XINT (x, 1) == UNSPEC_PLT)
103@@ -1308,8 +1308,16 @@ microblaze_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length)
104 emit_move_insn (dest_reg, plus_constant (Pmode, dest_reg, MAX_MOVE_BYTES));
105
106 /* Emit the test & branch. */
107- emit_insn (gen_cbranchsi4 (gen_rtx_NE (SImode, src_reg, final_src),
108+
109+ if (TARGET_MB_64) {
110+ emit_insn (gen_cbranchdi4 (gen_rtx_NE (Pmode, src_reg, final_src),
111+ src_reg, final_src, label));
112+ }
113+ else {
114+ emit_insn (gen_cbranchsi4 (gen_rtx_NE (Pmode, src_reg, final_src),
115 src_reg, final_src, label));
116+
117+ }
118
119 /* Mop up any left-over bytes. */
120 if (leftover)
121@@ -1639,14 +1647,20 @@ microblaze_function_arg_advance (cumulative_args_t cum_v,
122 break;
123
124 case E_DFmode:
125- cum->arg_words += 2;
126+ if (TARGET_MB_64)
127+ cum->arg_words++;
128+ else
129+ cum->arg_words += 2;
130 if (!cum->gp_reg_found && cum->arg_number <= 2)
131 cum->fp_code += 2 << ((cum->arg_number - 1) * 2);
132 break;
133
134 case E_DImode:
135 cum->gp_reg_found = 1;
136- cum->arg_words += 2;
137+ if (TARGET_MB_64)
138+ cum->arg_words++;
139+ else
140+ cum->arg_words += 2;
141 break;
142
143 case E_QImode:
144@@ -2161,7 +2175,7 @@ compute_frame_size (HOST_WIDE_INT size)
145
146 if (regno != MB_ABI_SUB_RETURN_ADDR_REGNUM)
147 /* Don't account for link register. It is accounted specially below. */
148- gp_reg_size += GET_MODE_SIZE (SImode);
149+ gp_reg_size += GET_MODE_SIZE (Pmode);
150
151 mask |= (1L << (regno - GP_REG_FIRST));
152 }
153@@ -2430,7 +2444,7 @@ print_operand (FILE * file, rtx op, int letter)
154
155 if ((letter == 'M' && !WORDS_BIG_ENDIAN)
156 || (letter == 'L' && WORDS_BIG_ENDIAN) || letter == 'D')
157- regnum++;
158+ regnum++;
159
160 fprintf (file, "%s", reg_names[regnum]);
161 }
162@@ -2456,6 +2470,7 @@ print_operand (FILE * file, rtx op, int letter)
163 else if (letter == 'h' || letter == 'j')
164 {
165 long val[2];
166+ int val1[2];
167 long l[2];
168 if (code == CONST_DOUBLE)
169 {
170@@ -2468,12 +2483,12 @@ print_operand (FILE * file, rtx op, int letter)
171 val[0] = l[WORDS_BIG_ENDIAN != 0];
172 }
173 }
174- else if (code == CONST_INT)
175+ else if (code == CONST_INT || code == CONST)// || code == SYMBOL_REF ||code == LABEL_REF)
176 {
177- val[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32;
178- val[1] = INTVAL (op) & 0x00000000ffffffffLL;
179+ val1[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32;
180+ val1[1] = INTVAL (op) & 0x00000000ffffffffLL;
181 }
182- fprintf (file, "0x%8.8lx", (letter == 'h') ? val[0] : val[1]);
183+ fprintf (file, "0x%8.8lx", (letter == 'h') ? val1[0] : val1[1]);
184 }
185 else if (code == CONST_DOUBLE)
186 {
187@@ -2667,7 +2682,10 @@ microblaze_asm_constructor (rtx symbol ATTRIBUTE_UNUSED, int priority)
188
189 switch_to_section (get_section (section, 0, NULL));
190 assemble_align (POINTER_SIZE);
191- fputs ("\t.word\t", asm_out_file);
192+ if (TARGET_MB_64)
193+ fputs ("\t.dword\t", asm_out_file);
194+ else
195+ fputs ("\t.word\t", asm_out_file);
196 output_addr_const (asm_out_file, symbol);
197 fputs ("\n", asm_out_file);
198 }
199@@ -2690,7 +2708,10 @@ microblaze_asm_destructor (rtx symbol, int priority)
200
201 switch_to_section (get_section (section, 0, NULL));
202 assemble_align (POINTER_SIZE);
203- fputs ("\t.word\t", asm_out_file);
204+ if (TARGET_MB_64)
205+ fputs ("\t.dword\t", asm_out_file);
206+ else
207+ fputs ("\t.word\t", asm_out_file);
208 output_addr_const (asm_out_file, symbol);
209 fputs ("\n", asm_out_file);
210 }
211@@ -2756,7 +2777,7 @@ save_restore_insns (int prologue)
212 /* For interrupt_handlers, need to save/restore the MSR. */
213 if (microblaze_is_interrupt_variant ())
214 {
215- isr_mem_rtx = gen_rtx_MEM (SImode,
216+ isr_mem_rtx = gen_rtx_MEM (Pmode,
217 gen_rtx_PLUS (Pmode, base_reg_rtx,
218 GEN_INT (current_frame_info.
219 gp_offset -
220@@ -2764,8 +2785,8 @@ save_restore_insns (int prologue)
221
222 /* Do not optimize in flow analysis. */
223 MEM_VOLATILE_P (isr_mem_rtx) = 1;
224- isr_reg_rtx = gen_rtx_REG (SImode, MB_ABI_MSR_SAVE_REG);
225- isr_msr_rtx = gen_rtx_REG (SImode, ST_REG);
226+ isr_reg_rtx = gen_rtx_REG (Pmode, MB_ABI_MSR_SAVE_REG);
227+ isr_msr_rtx = gen_rtx_REG (Pmode, ST_REG);
228 }
229
230 if (microblaze_is_interrupt_variant () && !prologue)
231@@ -2773,8 +2794,8 @@ save_restore_insns (int prologue)
232 emit_move_insn (isr_reg_rtx, isr_mem_rtx);
233 emit_move_insn (isr_msr_rtx, isr_reg_rtx);
234 /* Do not optimize in flow analysis. */
235- emit_insn (gen_rtx_USE (SImode, isr_reg_rtx));
236- emit_insn (gen_rtx_USE (SImode, isr_msr_rtx));
237+ emit_insn (gen_rtx_USE (Pmode, isr_reg_rtx));
238+ emit_insn (gen_rtx_USE (Pmode, isr_msr_rtx));
239 }
240
241 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
242@@ -2785,9 +2806,9 @@ save_restore_insns (int prologue)
243 /* Don't handle here. Already handled as the first register. */
244 continue;
245
246- reg_rtx = gen_rtx_REG (SImode, regno);
247+ reg_rtx = gen_rtx_REG (Pmode, regno);
248 insn = gen_rtx_PLUS (Pmode, base_reg_rtx, GEN_INT (gp_offset));
249- mem_rtx = gen_rtx_MEM (SImode, insn);
250+ mem_rtx = gen_rtx_MEM (Pmode, insn);
251 if (microblaze_is_interrupt_variant () || save_volatiles)
252 /* Do not optimize in flow analysis. */
253 MEM_VOLATILE_P (mem_rtx) = 1;
254@@ -2802,7 +2823,7 @@ save_restore_insns (int prologue)
255 insn = emit_move_insn (reg_rtx, mem_rtx);
256 }
257
258- gp_offset += GET_MODE_SIZE (SImode);
259+ gp_offset += GET_MODE_SIZE (Pmode);
260 }
261 }
262
263@@ -2812,8 +2833,8 @@ save_restore_insns (int prologue)
264 emit_move_insn (isr_mem_rtx, isr_reg_rtx);
265
266 /* Do not optimize in flow analysis. */
267- emit_insn (gen_rtx_USE (SImode, isr_reg_rtx));
268- emit_insn (gen_rtx_USE (SImode, isr_msr_rtx));
269+ emit_insn (gen_rtx_USE (Pmode, isr_reg_rtx));
270+ emit_insn (gen_rtx_USE (Pmode, isr_msr_rtx));
271 }
272
273 /* Done saving and restoring */
274@@ -2903,7 +2924,10 @@ microblaze_elf_asm_cdtor (rtx symbol, int priority, bool is_ctor)
275
276 switch_to_section (s);
277 assemble_align (POINTER_SIZE);
278- fputs ("\t.word\t", asm_out_file);
279+ if (TARGET_MB_64)
280+ fputs ("\t.dword\t", asm_out_file);
281+ else
282+ fputs ("\t.word\t", asm_out_file);
283 output_addr_const (asm_out_file, symbol);
284 fputs ("\n", asm_out_file);
285 }
286@@ -3047,10 +3071,10 @@ microblaze_expand_prologue (void)
287 {
288 if (offset != 0)
289 ptr = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (offset));
290- emit_move_insn (gen_rtx_MEM (SImode, ptr),
291- gen_rtx_REG (SImode, regno));
292+ emit_move_insn (gen_rtx_MEM (Pmode, ptr),
293+ gen_rtx_REG (Pmode, regno));
294
295- offset += GET_MODE_SIZE (SImode);
296+ offset += GET_MODE_SIZE (Pmode);
297 }
298 }
299
300@@ -3059,15 +3083,23 @@ microblaze_expand_prologue (void)
301 rtx fsiz_rtx = GEN_INT (fsiz);
302
303 rtx_insn *insn = NULL;
304- insn = emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
305+ if (TARGET_MB_64)
306+ {
307+
308+ insn = emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx,
309 fsiz_rtx));
310+ }
311+ else {
312+ insn = emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
313+ fsiz_rtx));
314+ }
315 if (insn)
316 RTX_FRAME_RELATED_P (insn) = 1;
317
318 /* Handle SUB_RETURN_ADDR_REGNUM specially at first. */
319 if (!crtl->is_leaf || interrupt_handler)
320 {
321- mem_rtx = gen_rtx_MEM (SImode,
322+ mem_rtx = gen_rtx_MEM (Pmode,
323 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
324 const0_rtx));
325
326@@ -3075,7 +3107,7 @@ microblaze_expand_prologue (void)
327 /* Do not optimize in flow analysis. */
328 MEM_VOLATILE_P (mem_rtx) = 1;
329
330- reg_rtx = gen_rtx_REG (SImode, MB_ABI_SUB_RETURN_ADDR_REGNUM);
331+ reg_rtx = gen_rtx_REG (Pmode, MB_ABI_SUB_RETURN_ADDR_REGNUM);
332 insn = emit_move_insn (mem_rtx, reg_rtx);
333 RTX_FRAME_RELATED_P (insn) = 1;
334 }
335@@ -3185,12 +3217,12 @@ microblaze_expand_epilogue (void)
336 if (!crtl->is_leaf || interrupt_handler)
337 {
338 mem_rtx =
339- gen_rtx_MEM (SImode,
340+ gen_rtx_MEM (Pmode,
341 gen_rtx_PLUS (Pmode, stack_pointer_rtx, const0_rtx));
342 if (interrupt_handler)
343 /* Do not optimize in flow analysis. */
344 MEM_VOLATILE_P (mem_rtx) = 1;
345- reg_rtx = gen_rtx_REG (SImode, MB_ABI_SUB_RETURN_ADDR_REGNUM);
346+ reg_rtx = gen_rtx_REG (Pmode, MB_ABI_SUB_RETURN_ADDR_REGNUM);
347 emit_move_insn (reg_rtx, mem_rtx);
348 }
349
350@@ -3206,15 +3238,25 @@ microblaze_expand_epilogue (void)
351 /* _restore_ registers for epilogue. */
352 save_restore_insns (0);
353 emit_insn (gen_blockage ());
354- emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, fsiz_rtx));
355+ if (TARGET_MB_64)
356+ emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx, fsiz_rtx));
357+ else
358+ emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, fsiz_rtx));
359 }
360
361 if (crtl->calls_eh_return)
362- emit_insn (gen_addsi3 (stack_pointer_rtx,
363+ if (TARGET_MB_64) {
364+ emit_insn (gen_adddi3 (stack_pointer_rtx,
365 stack_pointer_rtx,
366- gen_raw_REG (SImode,
367+ gen_raw_REG (Pmode,
368 MB_EH_STACKADJ_REGNUM)));
369-
370+ }
371+ else {
372+ emit_insn (gen_addsi3 (stack_pointer_rtx,
373+ stack_pointer_rtx,
374+ gen_raw_REG (Pmode,
375+ MB_EH_STACKADJ_REGNUM)));
376+ }
377 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode, GP_REG_FIRST +
378 MB_ABI_SUB_RETURN_ADDR_REGNUM)));
379 }
380@@ -3381,9 +3423,14 @@ microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
381 else
382 this_rtx = gen_rtx_REG (Pmode, MB_ABI_FIRST_ARG_REGNUM);
383
384- /* Apply the constant offset, if required. */
385+ /* Apply the constant offset, if required. */
386 if (delta)
387- emit_insn (gen_addsi3 (this_rtx, this_rtx, GEN_INT (delta)));
388+ {
389+ if (TARGET_MB_64)
390+ emit_insn (gen_adddi3 (this_rtx, this_rtx, GEN_INT (delta)));
391+ else
392+ emit_insn (gen_addsi3 (this_rtx, this_rtx, GEN_INT (delta)));
393+ }
394
395 /* Apply the offset from the vtable, if required. */
396 if (vcall_offset)
397@@ -3396,7 +3443,10 @@ microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
398 rtx loc = gen_rtx_PLUS (Pmode, temp1, vcall_offset_rtx);
399 emit_move_insn (temp1, gen_rtx_MEM (Pmode, loc));
400
401- emit_insn (gen_addsi3 (this_rtx, this_rtx, temp1));
402+ if (TARGET_MB_64)
403+ emit_insn (gen_adddi3 (this_rtx, this_rtx, temp1));
404+ else
405+ emit_insn (gen_addsi3 (this_rtx, this_rtx, temp1));
406 }
407
408 /* Generate a tail call to the target function. */
409@@ -3631,9 +3681,9 @@ microblaze_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
410 emit_block_move (m_tramp, assemble_trampoline_template (),
411 GEN_INT (6*UNITS_PER_WORD), BLOCK_OP_NORMAL);
412
413- mem = adjust_address (m_tramp, SImode, 16);
414+ mem = adjust_address (m_tramp, Pmode, 16);
415 emit_move_insn (mem, chain_value);
416- mem = adjust_address (m_tramp, SImode, 20);
417+ mem = adjust_address (m_tramp, Pmode, 20);
418 emit_move_insn (mem, fnaddr);
419 }
420
421@@ -3657,7 +3707,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
422 {
423 comp_reg = cmp_op0;
424 condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx);
425- if (mode == SImode)
426+ if (mode == Pmode)
427 emit_jump_insn (gen_condjump (condition, label1));
428 else
429 emit_jump_insn (gen_long_condjump (condition, label1));
430@@ -3776,7 +3826,7 @@ microblaze_expand_conditional_branch_sf (rtx operands[])
431 rtx comp_reg = gen_reg_rtx (SImode);
432
433 emit_insn (gen_cstoresf4 (comp_reg, operands[0], cmp_op0, cmp_op1));
434- condition = gen_rtx_NE (SImode, comp_reg, const0_rtx);
435+ condition = gen_rtx_NE (Pmode, comp_reg, const0_rtx);
436 emit_jump_insn (gen_condjump (condition, operands[3]));
437 }
438
439@@ -3786,10 +3836,10 @@ microblaze_expand_conditional_branch_df (rtx operands[])
440 rtx condition;
441 rtx cmp_op0 = XEXP (operands[0], 0);
442 rtx cmp_op1 = XEXP (operands[0], 1);
443- rtx comp_reg = gen_reg_rtx (DImode);
444+ rtx comp_reg = gen_reg_rtx (Pmode);
445
446 emit_insn (gen_cstoredf4 (comp_reg, operands[0], cmp_op0, cmp_op1));
447- condition = gen_rtx_NE (DImode, comp_reg, const0_rtx);
448+ condition = gen_rtx_NE (Pmode, comp_reg, const0_rtx);
449 emit_jump_insn (gen_long_condjump (condition, operands[3]));
450 }
451
452@@ -3810,8 +3860,8 @@ microblaze_expand_divide (rtx operands[])
453 {
454 /* Table lookup software divides. Works for all (nr/dr) where (0 <= nr,dr <= 15). */
455
456- rtx regt1 = gen_reg_rtx (SImode);
457- rtx reg18 = gen_rtx_REG (SImode, R_TMP);
458+ rtx regt1 = gen_reg_rtx (Pmode);
459+ rtx reg18 = gen_rtx_REG (Pmode, R_TMP);
460 rtx regqi = gen_reg_rtx (QImode);
461 rtx_code_label *div_label = gen_label_rtx ();
462 rtx_code_label *div_end_label = gen_label_rtx ();
463@@ -3819,17 +3869,31 @@ microblaze_expand_divide (rtx operands[])
464 rtx mem_rtx;
465 rtx ret;
466 rtx_insn *jump, *cjump, *insn;
467-
468- insn = emit_insn (gen_iorsi3 (regt1, operands[1], operands[2]));
469- cjump = emit_jump_insn_after (gen_cbranchsi4 (
470- gen_rtx_GTU (SImode, regt1, GEN_INT (15)),
471+
472+ if (TARGET_MB_64) {
473+ insn = emit_insn (gen_iordi3 (regt1, operands[1], operands[2]));
474+ cjump = emit_jump_insn_after (gen_cbranchdi4 (
475+ gen_rtx_GTU (Pmode, regt1, GEN_INT (15)),
476+ regt1, GEN_INT (15), div_label), insn);
477+ }
478+ else {
479+ insn = emit_insn (gen_iorsi3 (regt1, operands[1], operands[2]));
480+ cjump = emit_jump_insn_after (gen_cbranchsi4 (
481+ gen_rtx_GTU (Pmode, regt1, GEN_INT (15)),
482 regt1, GEN_INT (15), div_label), insn);
483+ }
484 LABEL_NUSES (div_label) = 1;
485 JUMP_LABEL (cjump) = div_label;
486- emit_insn (gen_rtx_CLOBBER (SImode, reg18));
487+ emit_insn (gen_rtx_CLOBBER (Pmode, reg18));
488
489- emit_insn (gen_ashlsi3_bshift (regt1, operands[1], GEN_INT(4)));
490- emit_insn (gen_addsi3 (regt1, regt1, operands[2]));
491+ if (TARGET_MB_64) {
492+ emit_insn (gen_ashldi3_long (regt1, operands[1], GEN_INT(4)));
493+ emit_insn (gen_adddi3 (regt1, regt1, operands[2]));
494+ }
495+ else {
496+ emit_insn (gen_ashlsi3_bshift (regt1, operands[1], GEN_INT(4)));
497+ emit_insn (gen_addsi3 (regt1, regt1, operands[2]));
498+ }
499 mem_rtx = gen_rtx_MEM (QImode,
500 gen_rtx_PLUS (QImode, regt1, div_table_rtx));
501
502@@ -3976,7 +4040,7 @@ insert_wic_for_ilb_runout (rtx_insn *first)
503 {
504 insn =
505 emit_insn_before (gen_iprefetch
506- (gen_int_mode (addr_offset, SImode)),
507+ (gen_int_mode (addr_offset, Pmode)),
508 before_4);
509 recog_memoized (insn);
510 INSN_LOCATION (insn) = INSN_LOCATION (before_4);
511@@ -3986,7 +4050,27 @@ insert_wic_for_ilb_runout (rtx_insn *first)
512 }
513 }
514 }
515-
516+
517+/* Set the names for various arithmetic operations according to the
518+ * MICROBLAZE ABI. */
519+static void
520+microblaze_init_libfuncs (void)
521+{
522+ set_optab_libfunc (smod_optab, SImode, "__modsi3");
523+ set_optab_libfunc (sdiv_optab, SImode, "__divsi3");
524+ set_optab_libfunc (smul_optab, SImode, "__mulsi3");
525+ set_optab_libfunc (umod_optab, SImode, "__umodsi3");
526+ set_optab_libfunc (udiv_optab, SImode, "__udivsi3");
527+
528+ if (TARGET_MB_64)
529+ {
530+ set_optab_libfunc (smod_optab, DImode, "__moddi3");
531+ set_optab_libfunc (sdiv_optab, DImode, "__divdi3");
532+ set_optab_libfunc (smul_optab, DImode, "__muldi3");
533+ set_optab_libfunc (umod_optab, DImode, "__umoddi3");
534+ set_optab_libfunc (udiv_optab, DImode, "__udivdi3");
535+ }
536+}
537 /* Insert instruction prefetch instruction at the fall
538 through path of the function call. */
539
540@@ -4139,6 +4223,17 @@ microblaze_starting_frame_offset (void)
541 #undef TARGET_LRA_P
542 #define TARGET_LRA_P hook_bool_void_false
543
544+#ifdef TARGET_MB_64
545+#undef TARGET_ASM_ALIGNED_DI_OP
546+#define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
547+
548+#undef TARGET_ASM_ALIGNED_HI_OP
549+#define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
550+
551+#undef TARGET_ASM_ALIGNED_SI_OP
552+#define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
553+#endif
554+
555 #undef TARGET_FRAME_POINTER_REQUIRED
556 #define TARGET_FRAME_POINTER_REQUIRED microblaze_frame_pointer_required
557
558@@ -4148,6 +4243,9 @@ microblaze_starting_frame_offset (void)
559 #undef TARGET_TRAMPOLINE_INIT
560 #define TARGET_TRAMPOLINE_INIT microblaze_trampoline_init
561
562+#undef TARGET_INIT_LIBFUNCS
563+#define TARGET_INIT_LIBFUNCS microblaze_init_libfuncs
564+
565 #undef TARGET_PROMOTE_FUNCTION_MODE
566 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
567
568diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
569index f35f7075ce3..3aee003de0d 100644
570--- a/gcc/config/microblaze/microblaze.h
571+++ b/gcc/config/microblaze/microblaze.h
572@@ -173,7 +173,6 @@ extern enum pipeline_type microblaze_pipe;
573
574 /* Generate DWARF exception handling info. */
575 #define DWARF2_UNWIND_INFO 1
576-
577 /* Don't generate .loc operations. */
578 #define DWARF2_ASM_LINE_DEBUG_INFO 0
579
580@@ -206,38 +205,51 @@ extern enum pipeline_type microblaze_pipe;
581 ((flag_pic || GLOBAL) ? DW_EH_PE_aligned : DW_EH_PE_absptr)
582
583 /* Use DWARF 2 debugging information by default. */
584-#define DWARF2_DEBUGGING_INFO
585+#define DWARF2_DEBUGGING_INFO 1
586 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
587+#define DWARF2_ADDR_SIZE 4
588
589 /* Target machine storage layout */
590
591 #define BITS_BIG_ENDIAN 0
592 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
593 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN)
594-#define BITS_PER_WORD 32
595-#define UNITS_PER_WORD 4
596+//#define BITS_PER_WORD 64
597+//Revisit
598+#define MAX_BITS_PER_WORD 64
599+#define UNITS_PER_WORD (TARGET_MB_64 ? 8 : 4)
600+//#define MIN_UNITS_PER_WORD (TARGET_MB_64 ? 8 : 4)
601+//#define UNITS_PER_WORD 4
602 #define MIN_UNITS_PER_WORD 4
603 #define INT_TYPE_SIZE 32
604 #define SHORT_TYPE_SIZE 16
605-#define LONG_TYPE_SIZE 64
606+#define LONG_TYPE_SIZE (TARGET_MB_64 ? 64 : 32)
607 #define LONG_LONG_TYPE_SIZE 64
608 #define FLOAT_TYPE_SIZE 32
609 #define DOUBLE_TYPE_SIZE 64
610 #define LONG_DOUBLE_TYPE_SIZE 64
611-#define POINTER_SIZE 32
612-#define PARM_BOUNDARY 32
613-#define FUNCTION_BOUNDARY 32
614-#define EMPTY_FIELD_BOUNDARY 32
615+#define POINTER_SIZE (TARGET_MB_64 ? 64 : 32)
616+//#define WIDEST_HARDWARE_FP_SIZE 64
617+//#define POINTERS_EXTEND_UNSIGNED 1
618+#define PARM_BOUNDARY (TARGET_MB_64 ? 64 : 32)
619+#define FUNCTION_BOUNDARY (TARGET_MB_64 ? 64 : 32)
620+#define EMPTY_FIELD_BOUNDARY (TARGET_MB_64 ? 64 : 32)
621 #define STRUCTURE_SIZE_BOUNDARY 8
622-#define BIGGEST_ALIGNMENT 32
623+#define BIGGEST_ALIGNMENT (TARGET_MB_64 ? 64 : 32)
624 #define STRICT_ALIGNMENT 1
625 #define PCC_BITFIELD_TYPE_MATTERS 1
626
627+//#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_MB_64 ? TImode : DImode)
628 #undef SIZE_TYPE
629-#define SIZE_TYPE "unsigned int"
630+#define SIZE_TYPE (TARGET_MB_64 ? "long unsigned int" : "unsigned int")
631
632 #undef PTRDIFF_TYPE
633-#define PTRDIFF_TYPE "int"
634+#define PTRDIFF_TYPE (TARGET_MB_64 ? "long int" : "int")
635+
636+/*#undef INTPTR_TYPE
637+#define INTPTR_TYPE (TARGET_MB_64 ? "long int" : "int")*/
638+#undef UINTPTR_TYPE
639+#define UINTPTR_TYPE (TARGET_MB_64 ? "long unsigned int" : "unsigned int")
640
641 #define DATA_ALIGNMENT(TYPE, ALIGN) \
642 ((((ALIGN) < BITS_PER_WORD) \
643@@ -253,12 +265,12 @@ extern enum pipeline_type microblaze_pipe;
644 #define WORD_REGISTER_OPERATIONS 1
645
646 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
647-
648+/*
649 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
650 if (GET_MODE_CLASS (MODE) == MODE_INT \
651- && GET_MODE_SIZE (MODE) < 4) \
652- (MODE) = SImode;
653-
654+ && GET_MODE_SIZE (MODE) < (TARGET_MB_64 ? 8 : 4)) \
655+ (MODE) = TARGET_MB_64 ? DImode : SImode;
656+*/
657 /* Standard register usage. */
658
659 /* On the MicroBlaze, we have 32 integer registers */
660@@ -438,13 +450,16 @@ extern struct microblaze_frame_info current_frame_info;
661 #define FIRST_PARM_OFFSET(FNDECL) (UNITS_PER_WORD)
662
663 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
664+#define DWARF_CIE_DATA_ALIGNMENT -1
665
666 #define REG_PARM_STACK_SPACE(FNDECL) (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD)
667
668 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
669
670-#define STACK_BOUNDARY 32
671+#define STACK_BOUNDARY (TARGET_MB_64 ? 64 : 32)
672
673+#define PREFERRED_STACK_BOUNDARY (TARGET_MB_64 ? 64 : 32)
674+
675 #define NUM_OF_ARGS 6
676
677 #define GP_RETURN (GP_REG_FIRST + MB_ABI_INT_RETURN_VAL_REGNUM)
678@@ -455,12 +470,15 @@ extern struct microblaze_frame_info current_frame_info;
679 #define MAX_ARGS_IN_REGISTERS MB_ABI_MAX_ARG_REGS
680
681 #define LIBCALL_VALUE(MODE) \
682+ gen_rtx_REG (MODE,GP_RETURN)
683+
684+/*#define LIBCALL_VALUE(MODE) \
685 gen_rtx_REG ( \
686 ((GET_MODE_CLASS (MODE) != MODE_INT \
687 || GET_MODE_SIZE (MODE) >= 4) \
688 ? (MODE) \
689 : SImode), GP_RETURN)
690-
691+*/
692 /* 1 if N is a possible register number for a function value.
693 On the MicroBlaze, R2 R3 are the only register thus used.
694 Currently, R2 are only implemented here (C has no complex type) */
695@@ -500,7 +518,7 @@ typedef struct microblaze_args
696 /* 4 insns + 2 words of data. */
697 #define TRAMPOLINE_SIZE (6 * 4)
698
699-#define TRAMPOLINE_ALIGNMENT 32
700+#define TRAMPOLINE_ALIGNMENT 64
701
702 #define REGNO_OK_FOR_BASE_P(regno) microblaze_regno_ok_for_base_p ((regno), 1)
703
704@@ -529,13 +547,13 @@ typedef struct microblaze_args
705 addresses which require two reload registers. */
706 #define LEGITIMATE_PIC_OPERAND_P(X) microblaze_legitimate_pic_operand (X)
707
708-#define CASE_VECTOR_MODE (SImode)
709+#define CASE_VECTOR_MODE (TARGET_MB_64? DImode:SImode)
710
711 #ifndef DEFAULT_SIGNED_CHAR
712 #define DEFAULT_SIGNED_CHAR 1
713 #endif
714
715-#define MOVE_MAX 4
716+#define MOVE_MAX (TARGET_MB_64 ? 8 : 4)
717 #define MAX_MOVE_MAX 8
718
719 #define SLOW_BYTE_ACCESS 1
720@@ -545,7 +563,7 @@ typedef struct microblaze_args
721
722 #define SHIFT_COUNT_TRUNCATED 1
723
724-#define Pmode SImode
725+#define Pmode (TARGET_MB_64? DImode:SImode)
726
727 #define FUNCTION_MODE SImode
728
729@@ -707,6 +725,7 @@ do { \
730
731 #undef TARGET_ASM_OUTPUT_IDENT
732 #define TARGET_ASM_OUTPUT_IDENT microblaze_asm_output_ident
733+//#define TARGET_ASM_OUTPUT_IDENT default_asm_output_ident_directive
734
735 /* Default to -G 8 */
736 #ifndef MICROBLAZE_DEFAULT_GVALUE
737diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
738index 3f572fe2351..97da9aad6fd 100644
739--- a/gcc/config/microblaze/microblaze.md
740+++ b/gcc/config/microblaze/microblaze.md
741@@ -26,6 +26,7 @@
742 ;; Constants
743 ;;----------------------------------------------------
744 (define_constants [
745+ (R_Z 0) ;; For reg r0
746 (R_SP 1) ;; Stack pointer reg
747 (R_SR 15) ;; Sub-routine return addr reg
748 (R_IR 14) ;; Interrupt return addr reg
749@@ -541,6 +542,7 @@
750
751 ;; Add 2 SImode integers [ src1 = reg ; src2 = arith ; dest = reg ]
752 ;; Leave carry as is
753+
754 (define_insn "addsi3"
755 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
756 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%dJ,dJ,dJ")
757@@ -562,23 +564,38 @@
758
759 ;; Adding 2 DI operands in register or reg/imm
760
761-(define_insn "adddi3_long"
762+(define_expand "adddi3"
763+ [(set (match_operand:DI 0 "register_operand" "")
764+ (plus:DI (match_operand:DI 1 "register_operand" "")
765+ (match_operand:DI 2 "arith_plus_operand" "")))]
766+""
767+{
768+ if (TARGET_MB_64)
769+ {
770+ if (GET_CODE (operands[2]) == CONST_INT &&
771+ INTVAL(operands[2]) < (long)-549755813888 &&
772+ INTVAL(operands[2]) > (long)549755813887)
773+ FAIL;
774+ }
775+})
776+
777+(define_insn "*adddi3_long"
778 [(set (match_operand:DI 0 "register_operand" "=d,d")
779- (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%dJ,dJ")
780+ (plus:DI (match_operand:DI 1 "register_operand" "%d,d")
781 (match_operand:DI 2 "arith_plus_operand" "d,K")))]
782 "TARGET_MB_64"
783 "@
784- addlk\t%0,%z1,%2
785- addlik\t%0,%z1,%2"
786- [(set_attr "type" "arith,arith")
787- (set_attr "mode" "DI,DI")
788+ addlk\t%0,%1,%2
789+ addlik\t%0,%1,%2 #N10"
790+ [(set_attr "type" "darith,no_delay_arith")
791+ (set_attr "mode" "DI")
792 (set_attr "length" "4,4")])
793
794-(define_insn "adddi3"
795+(define_insn "*adddi3_all"
796 [(set (match_operand:DI 0 "register_operand" "=d,d")
797 (plus:DI (match_operand:DI 1 "register_operand" "%d,d")
798 (match_operand:DI 2 "arith_operand" "d,i")))]
799- ""
800+ "!TARGET_MB_64"
801 "@
802 add\t%L0,%L1,%L2\;addc\t%M0,%M1,%M2
803 addi\t%L0,%L1,%j2\;addic\t%M0,%M1,%h2"
804@@ -605,7 +622,7 @@
805 (define_insn "iprefetch"
806 [(unspec [(match_operand:SI 0 "const_int_operand" "n")] UNSPEC_IPREFETCH)
807 (clobber (mem:BLK (scratch)))]
808- "TARGET_PREFETCH"
809+ "TARGET_PREFETCH && !TARGET_MB_64"
810 {
811 operands[2] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
812 return "mfs\t%2,rpc\n\twic\t%2,r0";
813@@ -618,23 +635,33 @@
814 ;; Double Precision Subtraction
815 ;;----------------------------------------------------------------
816
817-(define_insn "subdi3_long"
818- [(set (match_operand:DI 0 "register_operand" "=d,d")
819- (minus:DI (match_operand:DI 1 "register_operand" "d,d")
820- (match_operand:DI 2 "register_operand" "d,n")))]
821+(define_expand "subdi3"
822+ [(set (match_operand:DI 0 "register_operand" "")
823+ (minus:DI (match_operand:DI 1 "register_operand" "")
824+ (match_operand:DI 2 "arith_operand" "")))]
825+""
826+"
827+{
828+}")
829+
830+(define_insn "subsidi3"
831+ [(set (match_operand:DI 0 "register_operand" "=d,d,d")
832+ (minus:DI (match_operand:DI 1 "register_operand" "d,d,d")
833+ (match_operand:DI 2 "arith_operand" "d,K,n")))]
834 "TARGET_MB_64"
835 "@
836 rsubl\t%0,%2,%1
837- addlik\t%0,%z1,-%2"
838- [(set_attr "type" "darith")
839- (set_attr "mode" "DI,DI")
840- (set_attr "length" "4,4")])
841+ addik\t%0,%z1,-%2
842+ addik\t%0,%z1,-%2"
843+ [(set_attr "type" "arith,no_delay_arith,no_delay_arith")
844+ (set_attr "mode" "DI")
845+ (set_attr "length" "4,4,4")])
846
847-(define_insn "subdi3"
848+(define_insn "subdi3_small"
849 [(set (match_operand:DI 0 "register_operand" "=&d")
850 (minus:DI (match_operand:DI 1 "register_operand" "d")
851 (match_operand:DI 2 "register_operand" "d")))]
852- ""
853+ "!TARGET_MB_64"
854 "rsub\t%L0,%L2,%L1\;rsubc\t%M0,%M2,%M1"
855 [(set_attr "type" "darith")
856 (set_attr "mode" "DI")
857@@ -663,7 +690,7 @@
858 (mult:DI
859 (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
860 (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
861- "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH"
862+ "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH && !TARGET_MB_64"
863 "mul\t%L0,%1,%2\;mulh\t%M0,%1,%2"
864 [(set_attr "type" "no_delay_arith")
865 (set_attr "mode" "DI")
866@@ -674,7 +701,7 @@
867 (mult:DI
868 (zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
869 (zero_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
870- "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH"
871+ "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH && !TARGET_MB_64"
872 "mul\t%L0,%1,%2\;mulhu\t%M0,%1,%2"
873 [(set_attr "type" "no_delay_arith")
874 (set_attr "mode" "DI")
875@@ -685,7 +712,7 @@
876 (mult:DI
877 (zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
878 (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
879- "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH"
880+ "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH && !TARGET_MB_64"
881 "mul\t%L0,%1,%2\;mulhsu\t%M0,%2,%1"
882 [(set_attr "type" "no_delay_arith")
883 (set_attr "mode" "DI")
884@@ -789,7 +816,7 @@
885 (match_operand:SI 4 "arith_operand")])
886 (label_ref (match_operand 5))
887 (pc)))]
888- "TARGET_HARD_FLOAT"
889+ "TARGET_HARD_FLOAT && !TARGET_MB_64"
890 [(set (match_dup 1) (match_dup 3))]
891
892 {
893@@ -819,6 +846,15 @@
894 (set_attr "mode" "SI")
895 (set_attr "length" "4")])
896
897+(define_insn "negsi_long"
898+ [(set (match_operand:SI 0 "register_operand" "=d")
899+ (neg:SI (match_operand:DI 1 "register_operand" "d")))]
900+ ""
901+ "rsubk\t%0,%1,r0"
902+ [(set_attr "type" "arith")
903+ (set_attr "mode" "SI")
904+ (set_attr "length" "4")])
905+
906 (define_insn "negdi2_long"
907 [(set (match_operand:DI 0 "register_operand" "=d")
908 (neg:DI (match_operand:DI 1 "register_operand" "d")))]
909@@ -847,16 +883,24 @@
910 (set_attr "mode" "SI")
911 (set_attr "length" "4")])
912
913-(define_insn "one_cmpldi2_long"
914+(define_expand "one_cmpldi2"
915+ [(set (match_operand:DI 0 "register_operand" "")
916+ (not:DI (match_operand:DI 1 "register_operand" "")))]
917+ ""
918+ "
919+{
920+}")
921+
922+(define_insn ""
923 [(set (match_operand:DI 0 "register_operand" "=d")
924- (not:DI (match_operand:DI 1 "register_operand" "d")))]
925+ (not:DI (match_operand:DI 1 "arith_operand" "d")))]
926 "TARGET_MB_64"
927 "xorli\t%0,%1,-1"
928- [(set_attr "type" "arith")
929+ [(set_attr "type" "no_delay_arith")
930 (set_attr "mode" "DI")
931 (set_attr "length" "4")])
932
933-(define_insn "*one_cmpldi2"
934+(define_insn ""
935 [(set (match_operand:DI 0 "register_operand" "=d")
936 (not:DI (match_operand:DI 1 "register_operand" "d")))]
937 ""
938@@ -871,7 +915,8 @@
939 (not:DI (match_operand:DI 1 "register_operand" "")))]
940 "reload_completed
941 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
942- && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))"
943+ && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
944+ && !TARGET_MB_64"
945
946 [(set (subreg:SI (match_dup 0) 0) (not:SI (subreg:SI (match_dup 1) 0)))
947 (set (subreg:SI (match_dup 0) 4) (not:SI (subreg:SI (match_dup 1) 4)))]
948@@ -883,18 +928,17 @@
949 ;;----------------------------------------------------------------
950
951 (define_insn "anddi3"
952- [(set (match_operand:DI 0 "register_operand" "=d,d")
953- (and:DI (match_operand:DI 1 "arith_operand" "d,d")
954- (match_operand:DI 2 "arith_operand" "d,K")))]
955+ [(set (match_operand:DI 0 "register_operand" "=d,d,d")
956+ (and:DI (match_operand:DI 1 "arith_operand" "d,d,d")
957+ (match_operand:DI 2 "arith_operand" "d,K,I")))]
958 "TARGET_MB_64"
959 "@
960 andl\t%0,%1,%2
961- andli\t%0,%1,%2 #andl1"
962- ;; andli\t%0,%1,%2 #andl3
963- ;; andli\t%0,%1,%2 #andl2
964- [(set_attr "type" "arith,arith")
965- (set_attr "mode" "DI,DI")
966- (set_attr "length" "4,4")])
967+ andli\t%0,%1,%2 #andl2
968+ andli\t%0,%1,%2 #andl3"
969+ [(set_attr "type" "arith,no_delay_arith,no_delay_arith")
970+ (set_attr "mode" "DI,DI,DI")
971+ (set_attr "length" "4,4,4")])
972
973 (define_insn "andsi3"
974 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
975@@ -919,7 +963,7 @@
976 "@
977 orl\t%0,%1,%2
978 orli\t%0,%1,%2 #andl1"
979- [(set_attr "type" "arith,arith")
980+ [(set_attr "type" "arith,no_delay_arith")
981 (set_attr "mode" "DI,DI")
982 (set_attr "length" "4,4")])
983
984@@ -945,7 +989,7 @@
985 "@
986 xorl\t%0,%1,%2
987 xorli\t%0,%1,%2 #andl1"
988- [(set_attr "type" "arith,arith")
989+ [(set_attr "type" "arith,no_delay_arith")
990 (set_attr "mode" "DI,DI")
991 (set_attr "length" "4,4")])
992
993@@ -1018,26 +1062,6 @@
994 (set_attr "mode" "SI")
995 (set_attr "length" "4")])
996
997-;;(define_expand "extendqidi2"
998-;; [(set (match_operand:DI 0 "register_operand" "=d")
999-;; (sign_extend:DI (match_operand:QI 1 "general_operand" "d")))]
1000-;; "TARGET_MB_64"
1001-;; {
1002-;; if (GET_CODE (operands[1]) != REG)
1003-;; FAIL;
1004-;; }
1005-;;)
1006-
1007-
1008-;;(define_insn "extendqidi2"
1009-;; [(set (match_operand:DI 0 "register_operand" "=d")
1010-;; (sign_extend:DI (match_operand:QI 1 "register_operand" "d")))]
1011-;; "TARGET_MB_64"
1012-;; "sextl8\t%0,%1"
1013-;; [(set_attr "type" "arith")
1014-;; (set_attr "mode" "DI")
1015-;; (set_attr "length" "4")])
1016-
1017 (define_insn "extendhisi2"
1018 [(set (match_operand:SI 0 "register_operand" "=d")
1019 (sign_extend:SI (match_operand:HI 1 "register_operand" "d")))]
1020@@ -1060,6 +1084,27 @@
1021 ;; Those for integer source operand are ordered
1022 ;; widest source type first.
1023
1024+(define_insn "extendsidi2_long"
1025+ [(set (match_operand:DI 0 "register_operand" "=d,d,d")
1026+ (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))]
1027+ "TARGET_MB_64"
1028+ {
1029+ switch (which_alternative)
1030+ {
1031+ case 0:
1032+ return "sextl32\t%0,%1";
1033+ case 1:
1034+ case 2:
1035+ {
1036+ output_asm_insn ("ll%i1\t%0,%1", operands);
1037+ return "sextl32\t%0,%0";
1038+ }
1039+ }
1040+ }
1041+ [(set_attr "type" "multi,multi,multi")
1042+ (set_attr "mode" "DI")
1043+ (set_attr "length" "4,8,8")])
1044+
1045 (define_insn "extendsidi2"
1046 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
1047 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))]
1048@@ -1088,69 +1133,118 @@
1049 ;; Unlike most other insns, the move insns can't be split with
1050 ;; different predicates, because register spilling and other parts of
1051 ;; the compiler, have memoized the insn number already.
1052+;; //}
1053
1054 (define_expand "movdi"
1055 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1056 (match_operand:DI 1 "general_operand" ""))]
1057 ""
1058 {
1059- /* If operands[1] is a constant address illegal for pic, then we need to
1060- handle it just like microblaze_legitimize_address does. */
1061- if (flag_pic && pic_address_needs_scratch (operands[1]))
1062+ if (TARGET_MB_64)
1063 {
1064+ if (microblaze_expand_move (DImode, operands)) DONE;
1065+ }
1066+ else
1067+ {
1068+ /* If operands[1] is a constant address illegal for pic, then we need to
1069+ handle it just like microblaze_legitimize_address does. */
1070+ if (flag_pic && pic_address_needs_scratch (operands[1]))
1071+ {
1072 rtx temp = force_reg (DImode, XEXP (XEXP (operands[1], 0), 0));
1073 rtx temp2 = XEXP (XEXP (operands[1], 0), 1);
1074 emit_move_insn (operands[0], gen_rtx_PLUS (DImode, temp, temp2));
1075 DONE;
1076- }
1077-
1078-
1079- if ((reload_in_progress | reload_completed) == 0
1080- && !register_operand (operands[0], DImode)
1081- && !register_operand (operands[1], DImode)
1082- && (((GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0)
1083- && operands[1] != CONST0_RTX (DImode))))
1084- {
1085+ }
1086
1087- rtx temp = force_reg (DImode, operands[1]);
1088- emit_move_insn (operands[0], temp);
1089- DONE;
1090+ if ((reload_in_progress | reload_completed) == 0
1091+ && !register_operand (operands[0], DImode)
1092+ && !register_operand (operands[1], DImode)
1093+ && (((GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0)
1094+ && operands[1] != CONST0_RTX (DImode))))
1095+ {
1096+ rtx temp = force_reg (DImode, operands[1]);
1097+ emit_move_insn (operands[0], temp);
1098+ DONE;
1099+ }
1100 }
1101 }
1102 )
1103
1104+;; Added for status registers
1105+(define_insn "movdi_status"
1106+ [(set (match_operand:DI 0 "register_operand" "=d,d,z")
1107+ (match_operand:DI 1 "register_operand" "z,d,d"))]
1108+ "microblaze_is_interrupt_variant () && TARGET_MB_64"
1109+ "@
1110+ mfs\t%0,%1 #mfs
1111+ addlk\t%0,%1,r0 #add movdi
1112+ mts\t%0,%1 #mts"
1113+ [(set_attr "type" "move")
1114+ (set_attr "mode" "DI")
1115+ (set_attr "length" "12")])
1116+
1117+;; This move will be not be moved to delay slot.
1118+(define_insn "*movdi_internal3"
1119+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d")
1120+ (match_operand:DI 1 "immediate_operand" "J,I,Mnis"))]
1121+ "TARGET_MB_64 && (register_operand (operands[0], DImode) &&
1122+ (GET_CODE (operands[1]) == CONST_INT &&
1123+ (INTVAL (operands[1]) <= (long)549755813887 && INTVAL (operands[1]) >= (long)-549755813888)))"
1124+ "@
1125+ addlk\t%0,r0,r0\t
1126+ addlik\t%0,r0,%1\t #N1 %X1
1127+ addlik\t%0,r0,%1\t #N2 %X1"
1128+ [(set_attr "type" "arith,no_delay_arith,no_delay_arith")
1129+ (set_attr "mode" "DI")
1130+ (set_attr "length" "4")])
1131
1132-(define_insn "*movdi_internal_64"
1133- [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o")
1134- (match_operand:DI 1 "general_operand" " d,K,J,R,o,d,d"))]
1135- "TARGET_MB_64 && (INTVAL(operands[1]) < 0x7fffffffff) && (INTVAL(operands[1]) > 0xffffff8000000000)"
1136+;; This move may be used for PLT label operand
1137+(define_insn "*movdi_internal5_pltop"
1138+ [(set (match_operand:DI 0 "register_operand" "=d,d")
1139+ (match_operand:DI 1 "call_insn_operand" ""))]
1140+ "TARGET_MB_64 && (register_operand (operands[0], Pmode) &&
1141+ PLT_ADDR_P (operands[1]))"
1142+ {
1143+ gcc_unreachable ();
1144+ }
1145+ [(set_attr "type" "load")
1146+ (set_attr "mode" "DI")
1147+ (set_attr "length" "4")])
1148+
1149+(define_insn "*movdi_internal2"
1150+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d, d,d,R,m")
1151+ (match_operand:DI 1 "move_src_operand" " d,I,Mnis,R,m,dJ,dJ"))]
1152+ "TARGET_MB_64"
1153 {
1154 switch (which_alternative)
1155 {
1156 case 0:
1157- return "addlk\t%0,%1";
1158- case 1:
1159- return "addlik\t%0,r0,%1";
1160- case 2:
1161- return "addlk\t%0,r0,r0";
1162- case 3:
1163- case 4:
1164- return "lli\t%0,%1";
1165- case 5:
1166- case 6:
1167- return "sli\t%1,%0";
1168- }
1169- return "unreachable";
1170- }
1171- [(set_attr "type" "no_delay_move,no_delay_arith,no_delay_arith,no_delay_load,no_delay_load,no_delay_store,no_delay_store")
1172+ return "addlk\t%0,%1,r0";
1173+ case 1:
1174+ case 2:
1175+ if (GET_CODE (operands[1]) == CONST_INT &&
1176+ (INTVAL (operands[1]) > (long)549755813887 || INTVAL (operands[1]) < (long)-549755813888))
1177+ return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
1178+ else
1179+ return "addlik\t%0,r0,%1";
1180+ case 3:
1181+ case 4:
1182+ return "ll%i1\t%0,%1";
1183+ case 5:
1184+ case 6:
1185+ return "sl%i0\t%z1,%0";
1186+ }
1187+ }
1188+ [(set_attr "type" "load,no_delay_load,no_delay_load,no_delay_load,no_delay_load,no_delay_store,no_delay_store")
1189 (set_attr "mode" "DI")
1190- (set_attr "length" "8,8,8,8,12,8,12")])
1191+ (set_attr "length" "4,4,12,4,8,4,8")])
1192+
1193
1194
1195 (define_insn "*movdi_internal"
1196 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o")
1197 (match_operand:DI 1 "general_operand" " d,i,J,R,o,d,d"))]
1198- ""
1199+ "!TARGET_MB_64"
1200 {
1201 switch (which_alternative)
1202 {
1203@@ -1182,7 +1276,8 @@
1204 "reload_completed
1205 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
1206 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
1207- && (REGNO(operands[0]) == (REGNO(operands[1]) + 1))"
1208+ && (REGNO(operands[0]) == (REGNO(operands[1]) + 1))
1209+ && !(TARGET_MB_64)"
1210
1211 [(set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))
1212 (set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))]
1213@@ -1194,12 +1289,22 @@
1214 "reload_completed
1215 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
1216 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
1217- && (REGNO (operands[0]) != (REGNO (operands[1]) + 1))"
1218+ && (REGNO (operands[0]) != (REGNO (operands[1]) + 1))
1219+ && !(TARGET_MB_64)"
1220
1221 [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))
1222 (set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))]
1223 "")
1224
1225+(define_insn "movdi_long_int"
1226+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
1227+ (match_operand:DI 1 "general_operand" "i"))]
1228+ ""
1229+ "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
1230+ [(set_attr "type" "no_delay_arith")
1231+ (set_attr "mode" "DI")
1232+ (set_attr "length" "12")])
1233+
1234 ;; Unlike most other insns, the move insns can't be split with
1235 ;; different predicates, because register spilling and other parts of
1236 ;; the compiler, have memoized the insn number already.
1237@@ -1271,6 +1376,8 @@
1238 (set_attr "length" "4,4,8,4,8,4,8")])
1239
1240
1241+
1242+
1243 ;; 16-bit Integer moves
1244
1245 ;; Unlike most other insns, the move insns can't be split with
1246@@ -1303,8 +1410,8 @@
1247 "@
1248 addik\t%0,r0,%1\t# %X1
1249 addk\t%0,%1,r0
1250- lhui\t%0,%1
1251- lhui\t%0,%1
1252+ lhu%i1\t%0,%1
1253+ lhu%i1\t%0,%1
1254 sh%i0\t%z1,%0
1255 sh%i0\t%z1,%0"
1256 [(set_attr "type" "arith,move,load,no_delay_load,store,no_delay_store")
1257@@ -1347,7 +1454,7 @@
1258 lbu%i1\t%0,%1
1259 lbu%i1\t%0,%1
1260 sb%i0\t%z1,%0
1261- sbi\t%z1,%0"
1262+ sb%i0\t%z1,%0"
1263 [(set_attr "type" "arith,arith,move,load,no_delay_load,store,no_delay_store")
1264 (set_attr "mode" "QI")
1265 (set_attr "length" "4,4,8,4,8,4,8")])
1266@@ -1420,7 +1527,7 @@
1267 addik\t%0,r0,%F1
1268 lw%i1\t%0,%1
1269 sw%i0\t%z1,%0
1270- swi\t%z1,%0"
1271+ sw%i0\t%z1,%0"
1272 [(set_attr "type" "move,no_delay_load,load,no_delay_load,no_delay_load,store,no_delay_store")
1273 (set_attr "mode" "SF")
1274 (set_attr "length" "4,4,4,4,4,4,4")])
1275@@ -1459,6 +1566,33 @@
1276 ;; movdf_internal
1277 ;; Applies to both TARGET_SOFT_FLOAT and TARGET_HARD_FLOAT
1278 ;;
1279+(define_insn "*movdf_internal_64"
1280+ [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,d,m")
1281+ (match_operand:DF 1 "general_operand" "d,dG,m,F,T,d"))]
1282+ "TARGET_MB_64"
1283+ {
1284+ switch (which_alternative)
1285+ {
1286+ case 0:
1287+ return "addlk\t%0,%1,r0";
1288+ case 1:
1289+ return "addlk\t%0,r0,r0";
1290+ case 2:
1291+ case 4:
1292+ return "ll%i1\t%0,%1";
1293+ case 3:
1294+ {
1295+ return "addlik\t%0,r0,%h1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #Xfer Lo";
1296+ }
1297+ case 5:
1298+ return "sl%i0\t%1,%0";
1299+ }
1300+ gcc_unreachable ();
1301+ }
1302+ [(set_attr "type" "no_delay_move,no_delay_move,no_delay_load,no_delay_load,no_delay_load,no_delay_store")
1303+ (set_attr "mode" "DF")
1304+ (set_attr "length" "4,4,4,16,4,4")])
1305+
1306 (define_insn "*movdf_internal"
1307 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,o")
1308 (match_operand:DF 1 "general_operand" "dG,o,F,T,d"))]
1309@@ -1493,7 +1627,8 @@
1310 "reload_completed
1311 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
1312 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
1313- && (REGNO (operands[0]) == (REGNO (operands[1]) + 1))"
1314+ && (REGNO (operands[0]) == (REGNO (operands[1]) + 1))
1315+ && !TARGET_MB_64"
1316 [(set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))
1317 (set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))]
1318 "")
1319@@ -1504,7 +1639,8 @@
1320 "reload_completed
1321 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
1322 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
1323- && (REGNO (operands[0]) != (REGNO (operands[1]) + 1))"
1324+ && (REGNO (operands[0]) != (REGNO (operands[1]) + 1))
1325+ && !TARGET_MB_64"
1326 [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))
1327 (set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))]
1328 "")
1329@@ -2003,6 +2139,31 @@ else
1330 "
1331 )
1332
1333+
1334+(define_insn "seq_internal_pat_long"
1335+ [(set (match_operand:DI 0 "register_operand" "=d")
1336+ (eq:DI
1337+ (match_operand:DI 1 "register_operand" "d")
1338+ (match_operand:DI 2 "register_operand" "d")))]
1339+ "TARGET_MB_64"
1340+ "pcmpleq\t%0,%1,%2"
1341+ [(set_attr "type" "arith")
1342+ (set_attr "mode" "DI")
1343+ (set_attr "length" "4")]
1344+)
1345+
1346+(define_insn "sne_internal_pat_long"
1347+ [(set (match_operand:DI 0 "register_operand" "=d")
1348+ (ne:DI
1349+ (match_operand:DI 1 "register_operand" "d")
1350+ (match_operand:DI 2 "register_operand" "d")))]
1351+ "TARGET_MB_64"
1352+ "pcmplne\t%0,%1,%2"
1353+ [(set_attr "type" "arith")
1354+ (set_attr "mode" "DI")
1355+ (set_attr "length" "4")]
1356+)
1357+
1358 (define_insn "seq_internal_pat"
1359 [(set (match_operand:SI 0 "register_operand" "=d")
1360 (eq:SI
1361@@ -2063,8 +2224,8 @@ else
1362 (define_expand "cbranchsi4"
1363 [(set (pc)
1364 (if_then_else (match_operator 0 "ordered_comparison_operator"
1365- [(match_operand:SI 1 "register_operand")
1366- (match_operand:SI 2 "arith_operand" "I,i")])
1367+ [(match_operand 1 "register_operand")
1368+ (match_operand 2 "arith_operand" "I,i")])
1369 (label_ref (match_operand 3 ""))
1370 (pc)))]
1371 ""
1372@@ -2076,13 +2237,13 @@ else
1373 (define_expand "cbranchsi4_reg"
1374 [(set (pc)
1375 (if_then_else (match_operator 0 "ordered_comparison_operator"
1376- [(match_operand:SI 1 "register_operand")
1377- (match_operand:SI 2 "register_operand")])
1378+ [(match_operand 1 "register_operand")
1379+ (match_operand 2 "register_operand")])
1380 (label_ref (match_operand 3 ""))
1381 (pc)))]
1382 ""
1383 {
1384- microblaze_expand_conditional_branch_reg (SImode, operands);
1385+ microblaze_expand_conditional_branch_reg (Pmode, operands);
1386 DONE;
1387 })
1388
1389@@ -2107,6 +2268,26 @@ else
1390 (label_ref (match_operand 1))
1391 (pc)))])
1392
1393+(define_insn "branch_zero64"
1394+ [(set (pc)
1395+ (if_then_else (match_operator 0 "ordered_comparison_operator"
1396+ [(match_operand 1 "register_operand" "d")
1397+ (const_int 0)])
1398+ (match_operand 2 "pc_or_label_operand" "")
1399+ (match_operand 3 "pc_or_label_operand" "")))
1400+ ]
1401+ "TARGET_MB_64"
1402+ {
1403+ if (operands[3] == pc_rtx)
1404+ return "bea%C0i%?\t%z1,%2";
1405+ else
1406+ return "bea%N0i%?\t%z1,%3";
1407+ }
1408+ [(set_attr "type" "branch")
1409+ (set_attr "mode" "none")
1410+ (set_attr "length" "4")]
1411+)
1412+
1413 (define_insn "branch_zero"
1414 [(set (pc)
1415 (if_then_else (match_operator:SI 0 "ordered_comparison_operator"
1416@@ -2127,6 +2308,47 @@ else
1417 (set_attr "length" "4")]
1418 )
1419
1420+(define_insn "branch_compare64"
1421+ [(set (pc)
1422+ (if_then_else (match_operator 0 "cmp_op"
1423+ [(match_operand 1 "register_operand" "d")
1424+ (match_operand 2 "register_operand" "d")
1425+ ])
1426+ (label_ref (match_operand 3))
1427+ (pc)))
1428+ (clobber(reg:SI R_TMP))]
1429+ "TARGET_MB_64"
1430+ {
1431+ operands[4] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
1432+ enum rtx_code code = GET_CODE (operands[0]);
1433+
1434+ if (code == GT || code == LE)
1435+ {
1436+ output_asm_insn ("cmp\tr18,%z1,%z2", operands);
1437+ code = swap_condition (code);
1438+ }
1439+ else if (code == GTU || code == LEU)
1440+ {
1441+ output_asm_insn ("cmpu\tr18,%z1,%z2", operands);
1442+ code = swap_condition (code);
1443+ }
1444+ else if (code == GE || code == LT)
1445+ {
1446+ output_asm_insn ("cmp\tr18,%z2,%z1", operands);
1447+ }
1448+ else if (code == GEU || code == LTU)
1449+ {
1450+ output_asm_insn ("cmpu\tr18,%z2,%z1", operands);
1451+ }
1452+
1453+ operands[0] = gen_rtx_fmt_ee (signed_condition (code), SImode, operands[4], const0_rtx);
1454+ return "bea%C0i%?\tr18,%3";
1455+ }
1456+ [(set_attr "type" "branch")
1457+ (set_attr "mode" "none")
1458+ (set_attr "length" "12")]
1459+)
1460+
1461 (define_insn "branch_compare"
1462 [(set (pc)
1463 (if_then_else (match_operator:SI 0 "cmp_op"
1464@@ -2310,7 +2532,7 @@ else
1465 ;; Indirect jumps. Jump to register values. Assuming absolute jumps
1466
1467 (define_insn "indirect_jump_internal1"
1468- [(set (pc) (match_operand:SI 0 "register_operand" "d"))]
1469+ [(set (pc) (match_operand 0 "register_operand" "d"))]
1470 ""
1471 "bra%?\t%0"
1472 [(set_attr "type" "jump")
1473@@ -2323,7 +2545,7 @@ else
1474 (use (label_ref (match_operand 1 "" "")))]
1475 ""
1476 {
1477- gcc_assert (GET_MODE (operands[0]) == Pmode);
1478+ //gcc_assert (GET_MODE (operands[0]) == Pmode);
1479
1480 if (!flag_pic || TARGET_PIC_DATA_TEXT_REL)
1481 emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1]));
1482@@ -2335,7 +2557,7 @@ else
1483
1484 (define_insn "tablejump_internal1"
1485 [(set (pc)
1486- (match_operand:SI 0 "register_operand" "d"))
1487+ (match_operand 0 "register_operand" "d"))
1488 (use (label_ref (match_operand 1 "" "")))]
1489 ""
1490 "bra%?\t%0 "
1491@@ -2345,9 +2567,9 @@ else
1492
1493 (define_expand "tablejump_internal3"
1494 [(parallel [(set (pc)
1495- (plus:SI (match_operand:SI 0 "register_operand" "d")
1496- (label_ref:SI (match_operand:SI 1 "" ""))))
1497- (use (label_ref:SI (match_dup 1)))])]
1498+ (plus (match_operand 0 "register_operand" "d")
1499+ (label_ref (match_operand:SI 1 "" ""))))
1500+ (use (label_ref (match_dup 1)))])]
1501 ""
1502 ""
1503 )
1504@@ -2408,7 +2630,7 @@ else
1505 (minus (reg 1) (match_operand 1 "register_operand" "")))
1506 (set (reg 1)
1507 (minus (reg 1) (match_dup 1)))]
1508- ""
1509+ "!TARGET_MB_64"
1510 {
1511 rtx retaddr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
1512 rtx reg = gen_reg_rtx (Pmode);
1513@@ -2433,7 +2655,7 @@ else
1514 (define_expand "save_stack_block"
1515 [(match_operand 0 "register_operand" "")
1516 (match_operand 1 "register_operand" "")]
1517- ""
1518+ "!TARGET_MB_64"
1519 {
1520 emit_move_insn (operands[0], operands[1]);
1521 DONE;
1522@@ -2443,7 +2665,7 @@ else
1523 (define_expand "restore_stack_block"
1524 [(match_operand 0 "register_operand" "")
1525 (match_operand 1 "register_operand" "")]
1526- ""
1527+ "!TARGET_MB_64"
1528 {
1529 rtx retaddr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
1530 rtx rtmp = gen_rtx_REG (SImode, R_TMP);
1531@@ -2490,7 +2712,7 @@ else
1532
1533 (define_insn "<optab>_internal"
1534 [(any_return)
1535- (use (match_operand:SI 0 "register_operand" ""))]
1536+ (use (match_operand 0 "register_operand" ""))]
1537 ""
1538 {
1539 if (microblaze_is_break_handler ())
1540@@ -2523,7 +2745,7 @@ else
1541 (define_expand "call"
1542 [(parallel [(call (match_operand 0 "memory_operand" "m")
1543 (match_operand 1 "" "i"))
1544- (clobber (reg:SI R_SR))
1545+ (clobber (reg R_SR))
1546 (use (match_operand 2 "" ""))
1547 (use (match_operand 3 "" ""))])]
1548 ""
1549@@ -2544,12 +2766,12 @@ else
1550
1551 if (GET_CODE (XEXP (operands[0], 0)) == UNSPEC)
1552 emit_call_insn (gen_call_internal_plt0 (operands[0], operands[1],
1553- gen_rtx_REG (SImode,
1554+ gen_rtx_REG (Pmode,
1555 GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM),
1556 pic_offset_table_rtx));
1557 else
1558 emit_call_insn (gen_call_internal0 (operands[0], operands[1],
1559- gen_rtx_REG (SImode,
1560+ gen_rtx_REG (Pmode,
1561 GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM)));
1562
1563 DONE;
1564@@ -2559,7 +2781,7 @@ else
1565 (define_expand "call_internal0"
1566 [(parallel [(call (match_operand 0 "" "")
1567 (match_operand 1 "" ""))
1568- (clobber (match_operand:SI 2 "" ""))])]
1569+ (clobber (match_operand 2 "" ""))])]
1570 ""
1571 {
1572 }
1573@@ -2568,18 +2790,34 @@ else
1574 (define_expand "call_internal_plt0"
1575 [(parallel [(call (match_operand 0 "" "")
1576 (match_operand 1 "" ""))
1577- (clobber (match_operand:SI 2 "" ""))
1578- (use (match_operand:SI 3 "" ""))])]
1579+ (clobber (match_operand 2 "" ""))
1580+ (use (match_operand 3 "" ""))])]
1581 ""
1582 {
1583 }
1584 )
1585
1586+(define_insn "call_internal_plt_64"
1587+ [(call (mem (match_operand 0 "call_insn_plt_operand" ""))
1588+ (match_operand 1 "" "i"))
1589+ (clobber (reg R_SR))
1590+ (use (reg R_GOT))]
1591+ "flag_pic && TARGET_MB_64"
1592+ {
1593+ register rtx target2 = gen_rtx_REG (Pmode,
1594+ GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM);
1595+ gen_rtx_CLOBBER (VOIDmode, target2);
1596+ return "brealid\tr15,%0\;%#";
1597+ }
1598+ [(set_attr "type" "call")
1599+ (set_attr "mode" "none")
1600+ (set_attr "length" "4")])
1601+
1602 (define_insn "call_internal_plt"
1603- [(call (mem (match_operand:SI 0 "call_insn_plt_operand" ""))
1604- (match_operand:SI 1 "" "i"))
1605- (clobber (reg:SI R_SR))
1606- (use (reg:SI R_GOT))]
1607+ [(call (mem (match_operand 0 "call_insn_plt_operand" ""))
1608+ (match_operand 1 "" "i"))
1609+ (clobber (reg R_SR))
1610+ (use (reg R_GOT))]
1611 "flag_pic"
1612 {
1613 rtx target2
1614@@ -2591,10 +2829,41 @@ else
1615 (set_attr "mode" "none")
1616 (set_attr "length" "4")])
1617
1618+(define_insn "call_internal1_64"
1619+ [(call (mem (match_operand:VOID 0 "call_insn_simple_operand" "ri"))
1620+ (match_operand 1 "" "i"))
1621+ (clobber (reg R_SR))]
1622+ "TARGET_MB_64"
1623+ {
1624+ register rtx target = operands[0];
1625+ register rtx target2 = gen_rtx_REG (Pmode,
1626+ GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM);
1627+ if (GET_CODE (target) == SYMBOL_REF) {
1628+ if (microblaze_break_function_p (SYMBOL_REF_DECL (target))) {
1629+ gen_rtx_CLOBBER (VOIDmode, target2);
1630+ return "breaki\tr16,%0\;%#";
1631+ }
1632+ else {
1633+ gen_rtx_CLOBBER (VOIDmode, target2);
1634+ return "brealid\tr15,%0\;%#";
1635+ }
1636+ } else if (GET_CODE (target) == CONST_INT)
1637+ return "la\t%@,r0,%0\;brald\tr15,%@\;%#";
1638+ else if (GET_CODE (target) == REG)
1639+ return "brald\tr15,%0\;%#";
1640+ else {
1641+ fprintf (stderr,"Unsupported call insn\n");
1642+ return NULL;
1643+ }
1644+ }
1645+ [(set_attr "type" "call")
1646+ (set_attr "mode" "none")
1647+ (set_attr "length" "4")])
1648+
1649 (define_insn "call_internal1"
1650 [(call (mem (match_operand:VOID 0 "call_insn_simple_operand" "ri"))
1651- (match_operand:SI 1 "" "i"))
1652- (clobber (reg:SI R_SR))]
1653+ (match_operand 1 "" "i"))
1654+ (clobber (reg R_SR))]
1655 ""
1656 {
1657 rtx target = operands[0];
1658@@ -2628,7 +2897,7 @@ else
1659 [(parallel [(set (match_operand 0 "register_operand" "=d")
1660 (call (match_operand 1 "memory_operand" "m")
1661 (match_operand 2 "" "i")))
1662- (clobber (reg:SI R_SR))
1663+ (clobber (reg R_SR))
1664 (use (match_operand 3 "" ""))])] ;; next_arg_reg
1665 ""
1666 {
1667@@ -2649,13 +2918,13 @@ else
1668 if (GET_CODE (XEXP (operands[1], 0)) == UNSPEC)
1669 emit_call_insn (gen_call_value_intern_plt0 (operands[0], operands[1],
1670 operands[2],
1671- gen_rtx_REG (SImode,
1672+ gen_rtx_REG (Pmode,
1673 GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM),
1674 pic_offset_table_rtx));
1675 else
1676 emit_call_insn (gen_call_value_internal (operands[0], operands[1],
1677 operands[2],
1678- gen_rtx_REG (SImode,
1679+ gen_rtx_REG (Pmode,
1680 GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM)));
1681
1682 DONE;
1683@@ -2667,7 +2936,7 @@ else
1684 [(parallel [(set (match_operand 0 "" "")
1685 (call (match_operand 1 "" "")
1686 (match_operand 2 "" "")))
1687- (clobber (match_operand:SI 3 "" ""))
1688+ (clobber (match_operand 3 "" ""))
1689 ])]
1690 ""
1691 {}
1692@@ -2677,18 +2946,35 @@ else
1693 [(parallel[(set (match_operand 0 "" "")
1694 (call (match_operand 1 "" "")
1695 (match_operand 2 "" "")))
1696- (clobber (match_operand:SI 3 "" ""))
1697- (use (match_operand:SI 4 "" ""))])]
1698+ (clobber (match_operand 3 "" ""))
1699+ (use (match_operand 4 "" ""))])]
1700 "flag_pic"
1701 {}
1702 )
1703
1704+(define_insn "call_value_intern_plt_64"
1705+ [(set (match_operand:VOID 0 "register_operand" "=d")
1706+ (call (mem (match_operand 1 "call_insn_plt_operand" ""))
1707+ (match_operand 2 "" "i")))
1708+ (clobber (match_operand 3 "register_operand" "=d"))
1709+ (use (match_operand 4 "register_operand"))]
1710+ "flag_pic && TARGET_MB_64"
1711+ {
1712+ register rtx target2=gen_rtx_REG (Pmode,GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM);
1713+
1714+ gen_rtx_CLOBBER (VOIDmode,target2);
1715+ return "brealid\tr15,%1\;%#";
1716+ }
1717+ [(set_attr "type" "call")
1718+ (set_attr "mode" "none")
1719+ (set_attr "length" "4")])
1720+
1721 (define_insn "call_value_intern_plt"
1722 [(set (match_operand:VOID 0 "register_operand" "=d")
1723- (call (mem (match_operand:SI 1 "call_insn_plt_operand" ""))
1724- (match_operand:SI 2 "" "i")))
1725- (clobber (match_operand:SI 3 "register_operand" "=d"))
1726- (use (match_operand:SI 4 "register_operand"))]
1727+ (call (mem (match_operand 1 "call_insn_plt_operand" ""))
1728+ (match_operand 2 "" "i")))
1729+ (clobber (match_operand 3 "register_operand" "=d"))
1730+ (use (match_operand 4 "register_operand"))]
1731 "flag_pic"
1732 {
1733 rtx target2
1734@@ -2701,11 +2987,46 @@ else
1735 (set_attr "mode" "none")
1736 (set_attr "length" "4")])
1737
1738+(define_insn "call_value_intern_64"
1739+ [(set (match_operand:VOID 0 "register_operand" "=d")
1740+ (call (mem (match_operand:VOID 1 "call_insn_operand" "ri"))
1741+ (match_operand 2 "" "i")))
1742+ (clobber (match_operand 3 "register_operand" "=d"))]
1743+ "TARGET_MB_64"
1744+ {
1745+ register rtx target = operands[1];
1746+ register rtx target2=gen_rtx_REG (Pmode,GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM);
1747+
1748+ if (GET_CODE (target) == SYMBOL_REF)
1749+ {
1750+ gen_rtx_CLOBBER (VOIDmode,target2);
1751+ if (microblaze_break_function_p (SYMBOL_REF_DECL (target)))
1752+ return "breaki\tr16,%1\;%#";
1753+ else if (SYMBOL_REF_FLAGS (target) & SYMBOL_FLAG_FUNCTION)
1754+ {
1755+ return "brealid\tr15,%1\;%#";
1756+ }
1757+ else
1758+ {
1759+ return "bralid\tr15,%1\;%#";
1760+ }
1761+ }
1762+ else if (GET_CODE (target) == CONST_INT)
1763+ return "la\t%@,r0,%1\;brald\tr15,%@\;%#";
1764+ else if (GET_CODE (target) == REG)
1765+ return "brald\tr15,%1\;%#";
1766+ else
1767+ return "Unsupported call insn\n";
1768+ }
1769+ [(set_attr "type" "call")
1770+ (set_attr "mode" "none")
1771+ (set_attr "length" "4")])
1772+
1773 (define_insn "call_value_intern"
1774 [(set (match_operand:VOID 0 "register_operand" "=d")
1775 (call (mem (match_operand:VOID 1 "call_insn_operand" "ri"))
1776- (match_operand:SI 2 "" "i")))
1777- (clobber (match_operand:SI 3 "register_operand" "=d"))]
1778+ (match_operand 2 "" "i")))
1779+ (clobber (match_operand 3 "register_operand" "=d"))]
1780 ""
1781 {
1782 rtx target = operands[1];
1783diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze
1784index 4c25cfe15e7..965132b3513 100644
1785--- a/gcc/config/microblaze/t-microblaze
1786+++ b/gcc/config/microblaze/t-microblaze
1787@@ -2,7 +2,8 @@ MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high mlittle-en
1788 MULTILIB_DIRNAMES = bs m mh le m64
1789 MULTILIB_EXCEPTIONS = *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high
1790 MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian
1791-MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/m64
1792+MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian/m64
1793+MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/m64 mxl-multiply-high
1794 MULTILIB_EXCEPTIONS += mxl-multiply-high/mlittle-endian
1795 MULTILIB_EXCEPTIONS += mxl-multiply-high/m64
1796 MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64
1797diff --git a/libgcc/config/microblaze/crti.S b/libgcc/config/microblaze/crti.S
1798index 0f24adb750d..1a89a0a2ffa 100644
1799--- a/libgcc/config/microblaze/crti.S
1800+++ b/libgcc/config/microblaze/crti.S
1801@@ -40,7 +40,7 @@
1802
1803 .align 2
1804 __init:
1805- addik r1, r1, -8
1806+ addik r1, r1, -16
1807 sw r15, r0, r1
1808 la r11, r0, _stack
1809 mts rshr, r11
1810@@ -51,5 +51,5 @@ __init:
1811 .global __fini
1812 .align 2
1813 __fini:
1814- addik r1, r1, -8
1815+ addik r1, r1, -16
1816 sw r15, r0, r1
1817diff --git a/libgcc/config/microblaze/crtn.S b/libgcc/config/microblaze/crtn.S
1818index d38d7ab9f98..29a004973ae 100644
1819--- a/libgcc/config/microblaze/crtn.S
1820+++ b/libgcc/config/microblaze/crtn.S
1821@@ -33,9 +33,9 @@
1822 .section .init, "ax"
1823 lw r15, r0, r1
1824 rtsd r15, 8
1825- addik r1, r1, 8
1826+ addik r1, r1, 16
1827
1828 .section .fini, "ax"
1829 lw r15, r0, r1
1830 rtsd r15, 8
1831- addik r1, r1, 8
1832+ addik r1, r1, 16
1833diff --git a/libgcc/config/microblaze/divdi3.S b/libgcc/config/microblaze/divdi3.S
1834new file mode 100644
1835index 00000000000..d37bf5165c6
1836--- /dev/null
1837+++ b/libgcc/config/microblaze/divdi3.S
1838@@ -0,0 +1,98 @@
1839+###################################-
1840+#
1841+# Copyright (C) 2009-2017 Free Software Foundation, Inc.
1842+#
1843+# Contributed by Michael Eager <eager@eagercon.com>.
1844+#
1845+# This file is free software; you can redistribute it and/or modify it
1846+# under the terms of the GNU General Public License as published by the
1847+# Free Software Foundation; either version 3, or (at your option) any
1848+# later version.
1849+#
1850+# GCC is distributed in the hope that it will be useful, but WITHOUT
1851+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
1852+# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
1853+# License for more details.
1854+#
1855+# Under Section 7 of GPL version 3, you are granted additional
1856+# permissions described in the GCC Runtime Library Exception, version
1857+# 3.1, as published by the Free Software Foundation.
1858+#
1859+# You should have received a copy of the GNU General Public License and
1860+# a copy of the GCC Runtime Library Exception along with this program;
1861+# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
1862+# <http://www.gnu.org/licenses/>.
1863+#
1864+# divdi3.S
1865+#
1866+# Divide operation for 32 bit integers.
1867+# Input : Dividend in Reg r5
1868+# Divisor in Reg r6
1869+# Output: Result in Reg r3
1870+#
1871+#######################################
1872+
1873+#ifdef __arch64__
1874+ .globl __divdi3
1875+ .ent __divdi3
1876+ .type __divdi3,@function
1877+__divdi3:
1878+ .frame r1,0,r15
1879+
1880+ ADDLIK r1,r1,-32
1881+ SLI r28,r1,0
1882+ SLI r29,r1,8
1883+ SLI r30,r1,16
1884+ SLI r31,r1,24
1885+
1886+ BEALEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error
1887+ BEALEQI r5,$LaResult_Is_Zero # Result is Zero
1888+ XORL r28,r5,r6 # Get the sign of the result
1889+ BEALGEI r5,$LaR5_Pos
1890+ RSUBLI r5,r5,0 # Make r5 positive
1891+$LaR5_Pos:
1892+ BEALGEI r6,$LaR6_Pos
1893+ RSUBLI r6,r6,0 # Make r6 positive
1894+$LaR6_Pos:
1895+ ADDLIK r30,r0,0 # Clear mod
1896+ ADDLIK r3,r0,0 # clear div
1897+ ADDLIK r29,r0,64 # Initialize the loop count
1898+
1899+ # First part try to find the first '1' in the r5
1900+$LaDIV0:
1901+ BEALLTI r5,$LaDIV2 # This traps r5 == 0x80000000
1902+$LaDIV1:
1903+ ADDL r5,r5,r5 # left shift logical r5
1904+ ADDLIK r29,r29,-1
1905+ BEALGTI r5,$LaDIV1
1906+$LaDIV2:
1907+ ADDL r5,r5,r5 # left shift logical r5 get the '1' into the Carry
1908+ ADDLC r30,r30,r30 # Move that bit into the Mod register
1909+ RSUBL r31,r6,r30 # Try to subtract (r30 a r6)
1910+ BEALLTI r31,$LaMOD_TOO_SMALL
1911+ ORL r30,r0,r31 # Move the r31 to mod since the result was positive
1912+ ADDLIK r3,r3,1
1913+$LaMOD_TOO_SMALL:
1914+ ADDLIK r29,r29,-1
1915+ BEALEQi r29,$LaLOOP_END
1916+ ADDL r3,r3,r3 # Shift in the '1' into div
1917+ BREAI $LaDIV2 # Div2
1918+$LaLOOP_END:
1919+ BEALGEI r28,$LaRETURN_HERE
1920+ RSUBLI r3,r3,0 # Negate the result
1921+ BREAI $LaRETURN_HERE
1922+$LaDiv_By_Zero:
1923+$LaResult_Is_Zero:
1924+ ORL r3,r0,r0 # set result to 0
1925+$LaRETURN_HERE:
1926+# Restore values of CSRs and that of r3 and the divisor and the dividend
1927+ LLI r28,r1,0
1928+ LLI r29,r1,8
1929+ LLI r30,r1,16
1930+ LLI r31,r1,24
1931+ ADDLIK r1,r1,32
1932+ RTSD r15,8
1933+ nop
1934+.end __divdi3
1935+ .size __divdi3, . - __divdi3
1936+#endif
1937diff --git a/libgcc/config/microblaze/divdi3_table.c b/libgcc/config/microblaze/divdi3_table.c
1938new file mode 100644
1939index 00000000000..80962597ea5
1940--- /dev/null
1941+++ b/libgcc/config/microblaze/divdi3_table.c
1942@@ -0,0 +1,62 @@
1943+/* Table for software lookup divide for Xilinx MicroBlaze.
1944+
1945+ Copyright (C) 2009-2017 Free Software Foundation, Inc.
1946+
1947+ Contributed by Michael Eager <eager@eagercon.com>.
1948+
1949+ This file is free software; you can redistribute it and/or modify it
1950+ under the terms of the GNU General Public License as published by the
1951+ Free Software Foundation; either version 3, or (at your option) any
1952+ later version.
1953+
1954+ GCC is distributed in the hope that it will be useful, but WITHOUT
1955+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
1956+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
1957+ License for more details.
1958+
1959+ Under Section 7 of GPL version 3, you are granted additional
1960+ permissions described in the GCC Runtime Library Exception, version
1961+ 3.1, as published by the Free Software Foundation.
1962+
1963+ You should have received a copy of the GNU General Public License and
1964+ a copy of the GCC Runtime Library Exception along with this program;
1965+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
1966+ <http://www.gnu.org/licenses/>. */
1967+
1968+
1969+unsigned char _divdi3_table[] =
1970+{
1971+ 0, 0/1, 0/2, 0/3, 0/4, 0/5, 0/6, 0/7,
1972+ 0/8, 0/9, 0/10, 0/11, 0/12, 0/13, 0/14, 0/15,
1973+ 0, 1/1, 1/2, 1/3, 1/4, 1/5, 1/6, 1/7,
1974+ 1/8, 1/9, 1/10, 1/11, 1/12, 1/13, 1/14, 1/15,
1975+ 0, 2/1, 2/2, 2/3, 2/4, 2/5, 2/6, 2/7,
1976+ 2/8, 2/9, 2/10, 2/11, 2/12, 2/13, 2/14, 2/15,
1977+ 0, 3/1, 3/2, 3/3, 3/4, 3/5, 3/6, 3/7,
1978+ 3/8, 3/9, 3/10, 3/11, 3/12, 3/13, 3/14, 3/15,
1979+ 0, 4/1, 4/2, 4/3, 4/4, 4/5, 4/6, 4/7,
1980+ 4/8, 4/9, 4/10, 4/11, 4/12, 4/13, 4/14, 4/15,
1981+ 0, 5/1, 5/2, 5/3, 5/4, 5/5, 5/6, 5/7,
1982+ 5/8, 5/9, 5/10, 5/11, 5/12, 5/13, 5/14, 5/15,
1983+ 0, 6/1, 6/2, 6/3, 6/4, 6/5, 6/6, 6/7,
1984+ 6/8, 6/9, 6/10, 6/11, 6/12, 6/13, 6/14, 6/15,
1985+ 0, 7/1, 7/2, 7/3, 7/4, 7/5, 7/6, 7/7,
1986+ 7/8, 7/9, 7/10, 7/11, 7/12, 7/13, 7/14, 7/15,
1987+ 0, 8/1, 8/2, 8/3, 8/4, 8/5, 8/6, 8/7,
1988+ 8/8, 8/9, 8/10, 8/11, 8/12, 8/13, 8/14, 8/15,
1989+ 0, 9/1, 9/2, 9/3, 9/4, 9/5, 9/6, 9/7,
1990+ 9/8, 9/9, 9/10, 9/11, 9/12, 9/13, 9/14, 9/15,
1991+ 0, 10/1, 10/2, 10/3, 10/4, 10/5, 10/6, 10/7,
1992+ 10/8, 10/9, 10/10, 10/11, 10/12, 10/13, 10/14, 10/15,
1993+ 0, 11/1, 11/2, 11/3, 11/4, 11/5, 11/6, 11/7,
1994+ 11/8, 11/9, 11/10, 11/11, 11/12, 11/13, 11/14, 11/15,
1995+ 0, 12/1, 12/2, 12/3, 12/4, 12/5, 12/6, 12/7,
1996+ 12/8, 12/9, 12/10, 12/11, 12/12, 12/13, 12/14, 12/15,
1997+ 0, 13/1, 13/2, 13/3, 13/4, 13/5, 13/6, 13/7,
1998+ 13/8, 13/9, 13/10, 13/11, 13/12, 13/13, 13/14, 13/15,
1999+ 0, 14/1, 14/2, 14/3, 14/4, 14/5, 14/6, 14/7,
2000+ 14/8, 14/9, 14/10, 14/11, 14/12, 14/13, 14/14, 14/15,
2001+ 0, 15/1, 15/2, 15/3, 15/4, 15/5, 15/6, 15/7,
2002+ 15/8, 15/9, 15/10, 15/11, 15/12, 15/13, 15/14, 15/15,
2003+};
2004+
2005diff --git a/libgcc/config/microblaze/moddi3.S b/libgcc/config/microblaze/moddi3.S
2006new file mode 100644
2007index 00000000000..5d3f7c03fc8
2008--- /dev/null
2009+++ b/libgcc/config/microblaze/moddi3.S
2010@@ -0,0 +1,97 @@
2011+###################################
2012+#
2013+# Copyright (C) 2009-2017 Free Software Foundation, Inc.
2014+#
2015+# Contributed by Michael Eager <eager@eagercon.com>.
2016+#
2017+# This file is free software; you can redistribute it and/or modify it
2018+# under the terms of the GNU General Public License as published by the
2019+# Free Software Foundation; either version 3, or (at your option) any
2020+# later version.
2021+#
2022+# GCC is distributed in the hope that it will be useful, but WITHOUT
2023+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
2024+# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
2025+# License for more details.
2026+#
2027+# Under Section 7 of GPL version 3, you are granted additional
2028+# permissions described in the GCC Runtime Library Exception, version
2029+# 3.1, as published by the Free Software Foundation.
2030+#
2031+# You should have received a copy of the GNU General Public License and
2032+# a copy of the GCC Runtime Library Exception along with this program;
2033+# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
2034+# <http://www.gnu.org/licenses/>.
2035+#
2036+# moddi3.S
2037+#
2038+# modulo operation for 32 bit integers.
2039+# Input : op1 in Reg r5
2040+# op2 in Reg r6
2041+# Output: op1 mod op2 in Reg r3
2042+#
2043+#######################################
2044+
2045+#ifdef __arch64__
2046+ .globl __moddi3
2047+ .ent __moddi3
2048+ .type __moddi3,@function
2049+__moddi3:
2050+ .frame r1,0,r15
2051+
2052+ addlik r1,r1,-32
2053+ sli r28,r1,0
2054+ sli r29,r1,8
2055+ sli r30,r1,16
2056+ sli r31,r1,32
2057+
2058+ BEALEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error
2059+ BEALEQI r5,$LaResult_Is_Zero # Result is Zero
2060+ ADDL r28,r5,r0 # Get the sign of the result [ Depends only on the first arg]
2061+ BEALGEI r5,$LaR5_Pos
2062+ RSUBLI r5,r5,0 # Make r5 positive
2063+$LaR5_Pos:
2064+ BEALGEI r6,$LaR6_Pos
2065+ RSUBLI r6,r6,0 # Make r6 positive
2066+$LaR6_Pos:
2067+ ADDLIK r3,r0,0 # Clear mod
2068+ ADDLIK r30,r0,0 # clear div
2069+ ADDLIK r29,r0,64 # Initialize the loop count
2070+ BEALLTI r5,$LaDIV2 # If r5 is still negative (0x80000000), skip
2071+ # the first bit search.
2072+ # First part try to find the first '1' in the r5
2073+$LaDIV1:
2074+ ADDL r5,r5,r5 # left shift logical r5
2075+ ADDLIK r29,r29,-1
2076+ BEALGEI r5,$LaDIV1 #
2077+$LaDIV2:
2078+ ADDL r5,r5,r5 # left shift logical r5 get the '1' into the Carry
2079+ ADDLC r3,r3,r3 # Move that bit into the Mod register
2080+ rSUBL r31,r6,r3 # Try to subtract (r30 a r6)
2081+ BEALLTi r31,$LaMOD_TOO_SMALL
2082+ ORL r3,r0,r31 # Move the r31 to mod since the result was positive
2083+ ADDLIK r30,r30,1
2084+$LaMOD_TOO_SMALL:
2085+ ADDLIK r29,r29,-1
2086+ BEALEQi r29,$LaLOOP_END
2087+ ADDL r30,r30,r30 # Shift in the '1' into div
2088+ BREAI $LaDIV2 # Div2
2089+$LaLOOP_END:
2090+ BEALGEI r28,$LaRETURN_HERE
2091+ rsubli r3,r3,0 # Negate the result
2092+ BREAI $LaRETURN_HERE
2093+$LaDiv_By_Zero:
2094+$LaResult_Is_Zero:
2095+ orl r3,r0,r0 # set result to 0 [Both mod as well as div are 0]
2096+$LaRETURN_HERE:
2097+# Restore values of CSRs and that of r3 and the divisor and the dividend
2098+ lli r28,r1,0
2099+ lli r29,r1,8
2100+ lli r30,r1,16
2101+ lli r31,r1,24
2102+ addlik r1,r1,32
2103+ rtsd r15,8
2104+ nop
2105+ .end __moddi3
2106+ .size __moddi3, . - __moddi3
2107+#endif
2108diff --git a/libgcc/config/microblaze/muldi3.S b/libgcc/config/microblaze/muldi3.S
2109new file mode 100644
2110index 00000000000..567784197d3
2111--- /dev/null
2112+++ b/libgcc/config/microblaze/muldi3.S
2113@@ -0,0 +1,73 @@
2114+/*###################################-*-asm*-
2115+#
2116+# Copyright (C) 2009-2017 Free Software Foundation, Inc.
2117+#
2118+# Contributed by Michael Eager <eager@eagercon.com>.
2119+#
2120+# This file is free software; you can redistribute it and/or modify it
2121+# under the terms of the GNU General Public License as published by the
2122+# Free Software Foundation; either version 3, or (at your option) any
2123+# later version.
2124+#
2125+# GCC is distributed in the hope that it will be useful, but WITHOUT
2126+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
2127+# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
2128+# License for more details.
2129+#
2130+# Under Section 7 of GPL version 3, you are granted additional
2131+# permissions described in the GCC Runtime Library Exception, version
2132+# 3.1, as published by the Free Software Foundation.
2133+#
2134+# You should have received a copy of the GNU General Public License and
2135+# a copy of the GCC Runtime Library Exception along with this program;
2136+# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
2137+# <http://www.gnu.org/licenses/>.
2138+#
2139+# muldi3.S
2140+#
2141+# Multiply operation for 32 bit integers.
2142+# Input : Operand1 in Reg r5
2143+# Operand2 in Reg r6
2144+# Output: Result [op1 * op2] in Reg r3
2145+#
2146+#######################################*/
2147+
2148+#ifdef __arch64__
2149+ .globl __muldi3
2150+ .ent __muldi3
2151+ .type __muldi3,@function
2152+__muldi3:
2153+ .frame r1,0,r15
2154+ addl r3,r0,r0
2155+ BEALEQI r5,$L_Result_Is_Zero # Multiply by Zero
2156+ BEALEQI r6,$L_Result_Is_Zero # Multiply by Zero
2157+ XORL r4,r5,r6 # Get the sign of the result
2158+ BEALGEI r5,$L_R5_Pos
2159+ RSUBLI r5,r5,0 # Make r5 positive
2160+$L_R5_Pos:
2161+ BEALGEI r6,$L_R6_Pos
2162+ RSUBLI r6,r6,0 # Make r6 positive
2163+$L_R6_Pos:
2164+ breai $L1
2165+$L2:
2166+ addl r5,r5,r5
2167+$L1:
2168+ srll r6,r6
2169+ addlc r7,r0,r0
2170+ bealeqi r7,$L2
2171+ addl r3,r3,r5
2172+ bealnei r6,$L2
2173+ beallti r4,$L_NegateResult
2174+ rtsd r15,8
2175+ nop
2176+$L_NegateResult:
2177+ rsubl r3,r3,r0
2178+ rtsd r15,8
2179+ nop
2180+$L_Result_Is_Zero:
2181+ addli r3,r0,0
2182+ rtsd r15,8
2183+ nop
2184+ .end __muldi3
2185+ .size __muldi3, . - __muldi3
2186+#endif
2187diff --git a/libgcc/config/microblaze/t-microblaze b/libgcc/config/microblaze/t-microblaze
2188index 8d954a49575..35021b24b7d 100644
2189--- a/libgcc/config/microblaze/t-microblaze
2190+++ b/libgcc/config/microblaze/t-microblaze
2191@@ -1,11 +1,16 @@
2192-LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3
2193+LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3 \
2194+ _divdi3 _moddi3 _muldi3 _udivdi3 _umoddi3
2195
2196 LIB2ADD += \
2197 $(srcdir)/config/microblaze/divsi3.S \
2198+ $(srcdir)/config/microblaze/divdi3.S \
2199 $(srcdir)/config/microblaze/modsi3.S \
2200- $(srcdir)/config/microblaze/muldi3_hard.S \
2201+ $(srcdir)/config/microblaze/moddi3.S \
2202 $(srcdir)/config/microblaze/mulsi3.S \
2203+ $(srcdir)/config/microblaze/muldi3.S \
2204 $(srcdir)/config/microblaze/stack_overflow_exit.S \
2205 $(srcdir)/config/microblaze/udivsi3.S \
2206+ $(srcdir)/config/microblaze/udivdi3.S \
2207 $(srcdir)/config/microblaze/umodsi3.S \
2208- $(srcdir)/config/microblaze/divsi3_table.c
2209+ $(srcdir)/config/microblaze/umoddi3.S \
2210+ $(srcdir)/config/microblaze/divsi3_table.c \
2211diff --git a/libgcc/config/microblaze/udivdi3.S b/libgcc/config/microblaze/udivdi3.S
2212new file mode 100644
2213index 00000000000..c210fbc7128
2214--- /dev/null
2215+++ b/libgcc/config/microblaze/udivdi3.S
2216@@ -0,0 +1,107 @@
2217+###################################-
2218+#
2219+# Copyright (C) 2009-2017 Free Software Foundation, Inc.
2220+#
2221+# Contributed by Michael Eager <eager@eagercon.com>.
2222+#
2223+# This file is free software; you can redistribute it and/or modify it
2224+# under the terms of the GNU General Public License as published by the
2225+# Free Software Foundation; either version 3, or (at your option) any
2226+# later version.
2227+#
2228+# GCC is distributed in the hope that it will be useful, but WITHOUT
2229+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
2230+# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
2231+# License for more details.
2232+#
2233+# Under Section 7 of GPL version 3, you are granted additional
2234+# permissions described in the GCC Runtime Library Exception, version
2235+# 3.1, as published by the Free Software Foundation.
2236+#
2237+# You should have received a copy of the GNU General Public License and
2238+# a copy of the GCC Runtime Library Exception along with this program;
2239+# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
2240+# <http://www.gnu.org/licenses/>.
2241+#
2242+# udivdi3.S
2243+#
2244+# Unsigned divide operation.
2245+# Input : Divisor in Reg r5
2246+# Dividend in Reg r6
2247+# Output: Result in Reg r3
2248+#
2249+#######################################
2250+
2251+#ifdef __arch64__
2252+ .globl __udivdi3
2253+ .ent __udivdi3
2254+ .type __udivdi3,@function
2255+__udivdi3:
2256+ .frame r1,0,r15
2257+
2258+ ADDlIK r1,r1,-24
2259+ SLI r29,r1,0
2260+ SLI r30,r1,8
2261+ SLI r31,r1,16
2262+
2263+ BEALEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error
2264+ ADDLIK r30,r0,0 # Clear mod
2265+ BEALEQI r5,$LaResult_Is_Zero # Result is Zero
2266+ ADDLIK r29,r0,64 # Initialize the loop count
2267+
2268+ # Check if r6 and r5 are equal # if yes, return 1
2269+ RSUBL r18,r5,r6
2270+ ADDLIK r3,r0,1
2271+ BEALEQI r18,$LaRETURN_HERE
2272+
2273+ # Check if (uns)r6 is greater than (uns)r5. In that case, just return 0
2274+ XORL r18,r5,r6
2275+ ADDL r3,r0,r0 # We would anyways clear r3
2276+ BEALGEI r18,$LRSUBL
2277+ BEALLTI r6,$LaRETURN_HERE # r6[bit 31 = 1] hence is greater
2278+ BREAI $LCheckr6
2279+$LRSUBL:
2280+ RSUBL r18,r6,r5 # MICROBLAZEcmp
2281+ BEALLTI r18,$LaRETURN_HERE
2282+
2283+ # If r6 [bit 31] is set, then return result as 1
2284+$LCheckr6:
2285+ BEALGTI r6,$LaDIV0
2286+ ADDLIK r3,r0,1
2287+ BREAI $LaRETURN_HERE
2288+
2289+ # First part try to find the first '1' in the r5
2290+$LaDIV0:
2291+ BEALLTI r5,$LaDIV2
2292+$LaDIV1:
2293+ ADDL r5,r5,r5 # left shift logical r5
2294+ ADDLIK r29,r29,-1
2295+ BEALGTI r5,$LaDIV1
2296+$LaDIV2:
2297+ ADDL r5,r5,r5 # left shift logical r5 get the '1' into the Carry
2298+ ADDLC r30,r30,r30 # Move that bit into the Mod register
2299+ RSUBL r31,r6,r30 # Try to subtract (r30 a r6)
2300+ BEALLTI r31,$LaMOD_TOO_SMALL
2301+ ORL r30,r0,r31 # Move the r31 to mod since the result was positive
2302+ ADDLIK r3,r3,1
2303+$LaMOD_TOO_SMALL:
2304+ ADDLIK r29,r29,-1
2305+ BEALEQi r29,$LaLOOP_END
2306+ ADDL r3,r3,r3 # Shift in the '1' into div
2307+ BREAI $LaDIV2 # Div2
2308+$LaLOOP_END:
2309+ BREAI $LaRETURN_HERE
2310+$LaDiv_By_Zero:
2311+$LaResult_Is_Zero:
2312+ ORL r3,r0,r0 # set result to 0
2313+$LaRETURN_HERE:
2314+ # Restore values of CSRs and that of r3 and the divisor and the dividend
2315+ LLI r29,r1,0
2316+ LLI r30,r1,8
2317+ LLI r31,r1,16
2318+ ADDLIK r1,r1,24
2319+ RTSD r15,8
2320+ NOP
2321+ .end __udivdi3
2322+ .size __udivdi3, . - __udivdi3
2323+#endif
2324diff --git a/libgcc/config/microblaze/umoddi3.S b/libgcc/config/microblaze/umoddi3.S
2325new file mode 100644
2326index 00000000000..7f5cd23f9a1
2327--- /dev/null
2328+++ b/libgcc/config/microblaze/umoddi3.S
2329@@ -0,0 +1,110 @@
2330+###################################
2331+#
2332+# Copyright (C) 2009-2017 Free Software Foundation, Inc.
2333+#
2334+# Contributed by Michael Eager <eager@eagercon.com>.
2335+#
2336+# This file is free software; you can redistribute it and/or modify it
2337+# under the terms of the GNU General Public License as published by the
2338+# Free Software Foundation; either version 3, or (at your option) any
2339+# later version.
2340+#
2341+# GCC is distributed in the hope that it will be useful, but WITHOUT
2342+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
2343+# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
2344+# License for more details.
2345+#
2346+# Under Section 7 of GPL version 3, you are granted additional
2347+# permissions described in the GCC Runtime Library Exception, version
2348+# 3.1, as published by the Free Software Foundation.
2349+#
2350+# You should have received a copy of the GNU General Public License and
2351+# a copy of the GCC Runtime Library Exception along with this program;
2352+# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
2353+# <http://www.gnu.org/licenses/>.
2354+#
2355+# umoddi3.S
2356+#
2357+# Unsigned modulo operation for 32 bit integers.
2358+# Input : op1 in Reg r5
2359+# op2 in Reg r6
2360+# Output: op1 mod op2 in Reg r3
2361+#
2362+#######################################
2363+
2364+#ifdef __arch64__
2365+ .globl __umoddi3
2366+ .ent __umoddi3
2367+ .type __umoddi3,@function
2368+__umoddi3:
2369+ .frame r1,0,r15
2370+
2371+ addlik r1,r1,-24
2372+ sli r29,r1,0
2373+ sli r30,r1,8
2374+ sli r31,r1,16
2375+
2376+ BEALEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error
2377+ ADDLIK r3,r0,0 # Clear div
2378+ BEALEQI r5,$LaResult_Is_Zero # Result is Zero
2379+ ADDLIK r30,r0,0 # clear mod
2380+ ADDLIK r29,r0,64 # Initialize the loop count
2381+
2382+# Check if r6 and r5 are equal # if yes, return 0
2383+ rsubl r18,r5,r6
2384+ bealeqi r18,$LaRETURN_HERE
2385+
2386+# Check if (uns)r6 is greater than (uns)r5. In that case, just return r5
2387+ xorl r18,r5,r6
2388+ addlik r3,r5,0
2389+ bealgei r18,$LRSUB
2390+ beallti r6,$LaRETURN_HERE
2391+ breai $LCheckr6
2392+$LRSUB:
2393+ rsubl r18,r5,r6 # MICROBLAZEcmp
2394+ bealgti r18,$LaRETURN_HERE
2395+
2396+# If r6 [bit 31] is set, then return result as r5-r6
2397+$LCheckr6:
2398+ addlik r3,r0,0
2399+ bealgti r6,$LaDIV0
2400+ addlik r18,r0,0x7fffffff
2401+ andl r5,r5,r18
2402+ andl r6,r6,r18
2403+ breaid $LaRETURN_HERE
2404+ rsubl r3,r6,r5
2405+# First part: try to find the first '1' in the r5
2406+$LaDIV0:
2407+ BEALLTI r5,$LaDIV2
2408+$LaDIV1:
2409+ ADDL r5,r5,r5 # left shift logical r5
2410+ ADDLIK r29,r29,-1
2411+ BEALGEI r5,$LaDIV1 #
2412+$LaDIV2:
2413+ ADDL r5,r5,r5 # left shift logical r5 get the '1' into the Carry
2414+ ADDLC r3,r3,r3 # Move that bit into the Mod register
2415+ rSUBL r31,r6,r3 # Try to subtract (r3 a r6)
2416+ BEALLTi r31,$LaMOD_TOO_SMALL
2417+ ORL r3,r0,r31 # Move the r31 to mod since the result was positive
2418+ ADDLIK r30,r30,1
2419+$LaMOD_TOO_SMALL:
2420+ ADDLIK r29,r29,-1
2421+ BEALEQi r29,$LaLOOP_END
2422+ ADDL r30,r30,r30 # Shift in the '1' into div
2423+ BREAI $LaDIV2 # Div2
2424+$LaLOOP_END:
2425+ BREAI $LaRETURN_HERE
2426+$LaDiv_By_Zero:
2427+$LaResult_Is_Zero:
2428+ orl r3,r0,r0 # set result to 0
2429+$LaRETURN_HERE:
2430+# Restore values of CSRs and that of r3 and the divisor and the dividend
2431+ lli r29,r1,0
2432+ lli r30,r1,8
2433+ lli r31,r1,16
2434+ addlik r1,r1,24
2435+ rtsd r15,8
2436+ nop
2437+.end __umoddi3
2438+ .size __umoddi3, . - __umoddi3
2439+#endif
2440--
24412.34.1
2442
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0029-re-arrangement-of-the-compare-branches.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0029-re-arrangement-of-the-compare-branches.patch
new file mode 100644
index 00000000..448e850f
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0029-re-arrangement-of-the-compare-branches.patch
@@ -0,0 +1,268 @@
1From 870bfd716fcddeb72660f3176fb2a68aaa5ecc0e Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Tue, 13 Sep 2022 14:45:15 +0530
4Subject: [PATCH 29/54] re-arrangement of the compare branches
5
6---
7 gcc/config/microblaze/microblaze.cc | 28 ++----
8 gcc/config/microblaze/microblaze.md | 141 +++++++++++++---------------
9 2 files changed, 73 insertions(+), 96 deletions(-)
10
11diff --git a/gcc/config/microblaze/microblaze.cc b/gcc/config/microblaze/microblaze.cc
12index 46bbf8a21e7..de3c95a005e 100644
13--- a/gcc/config/microblaze/microblaze.cc
14+++ b/gcc/config/microblaze/microblaze.cc
15@@ -3707,11 +3707,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
16 {
17 comp_reg = cmp_op0;
18 condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx);
19- if (mode == Pmode)
20- emit_jump_insn (gen_condjump (condition, label1));
21- else
22- emit_jump_insn (gen_long_condjump (condition, label1));
23-
24+ emit_jump_insn (gen_condjump (condition, label1));
25 }
26
27 else if (code == EQ || code == NE)
28@@ -3722,10 +3718,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
29 else
30 emit_insn (gen_xordi3 (comp_reg, cmp_op0, cmp_op1));
31 condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx);
32- if (mode == SImode)
33- emit_jump_insn (gen_condjump (condition, label1));
34- else
35- emit_jump_insn (gen_long_condjump (condition, label1));
36+ emit_jump_insn (gen_condjump (condition, label1));
37 }
38 else
39 {
40@@ -3758,10 +3751,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
41 comp_reg = cmp_op0;
42 condition = gen_rtx_fmt_ee (signed_condition (code),
43 mode, comp_reg, const0_rtx);
44- if (mode == SImode)
45- emit_jump_insn (gen_condjump (condition, label1));
46- else
47- emit_jump_insn (gen_long_condjump (condition, label1));
48+ emit_jump_insn (gen_condjump (condition, label1));
49 }
50 else if (code == EQ)
51 {
52@@ -3776,10 +3766,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
53 cmp_op1));
54 }
55 condition = gen_rtx_EQ (mode, comp_reg, const0_rtx);
56- if (mode == SImode)
57- emit_jump_insn (gen_condjump (condition, label1));
58- else
59- emit_jump_insn (gen_long_condjump (condition, label1));
60+ emit_jump_insn (gen_condjump (condition, label1));
61
62 }
63 else if (code == NE)
64@@ -3795,10 +3782,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
65 cmp_op1));
66 }
67 condition = gen_rtx_NE (mode, comp_reg, const0_rtx);
68- if (mode == SImode)
69- emit_jump_insn (gen_condjump (condition, label1));
70- else
71- emit_jump_insn (gen_long_condjump (condition, label1));
72+ emit_jump_insn (gen_condjump (condition, label1));
73 }
74 else
75 {
76@@ -3840,7 +3824,7 @@ microblaze_expand_conditional_branch_df (rtx operands[])
77
78 emit_insn (gen_cstoredf4 (comp_reg, operands[0], cmp_op0, cmp_op1));
79 condition = gen_rtx_NE (Pmode, comp_reg, const0_rtx);
80- emit_jump_insn (gen_long_condjump (condition, operands[3]));
81+ emit_jump_insn (gen_condjump (condition, operands[3]));
82 }
83
84 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
85diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
86index 97da9aad6fd..31bf04e4abd 100644
87--- a/gcc/config/microblaze/microblaze.md
88+++ b/gcc/config/microblaze/microblaze.md
89@@ -2268,7 +2268,27 @@ else
90 (label_ref (match_operand 1))
91 (pc)))])
92
93-(define_insn "branch_zero64"
94+(define_insn "branch_zero_64"
95+ [(set (pc)
96+ (if_then_else (match_operator:SI 0 "ordered_comparison_operator"
97+ [(match_operand:SI 1 "register_operand" "d")
98+ (const_int 0)])
99+ (match_operand:SI 2 "pc_or_label_operand" "")
100+ (match_operand:SI 3 "pc_or_label_operand" "")))
101+ ]
102+ "TARGET_MB_64"
103+ {
104+ if (operands[3] == pc_rtx)
105+ return "bea%C0i%?\t%z1,%2";
106+ else
107+ return "bea%N0i%?\t%z1,%3";
108+ }
109+ [(set_attr "type" "branch")
110+ (set_attr "mode" "none")
111+ (set_attr "length" "4")]
112+)
113+
114+(define_insn "long_branch_zero"
115 [(set (pc)
116 (if_then_else (match_operator 0 "ordered_comparison_operator"
117 [(match_operand 1 "register_operand" "d")
118@@ -2279,9 +2299,9 @@ else
119 "TARGET_MB_64"
120 {
121 if (operands[3] == pc_rtx)
122- return "bea%C0i%?\t%z1,%2";
123+ return "beal%C0i%?\t%z1,%2";
124 else
125- return "bea%N0i%?\t%z1,%3";
126+ return "beal%N0i%?\t%z1,%3";
127 }
128 [(set_attr "type" "branch")
129 (set_attr "mode" "none")
130@@ -2310,9 +2330,9 @@ else
131
132 (define_insn "branch_compare64"
133 [(set (pc)
134- (if_then_else (match_operator 0 "cmp_op"
135- [(match_operand 1 "register_operand" "d")
136- (match_operand 2 "register_operand" "d")
137+ (if_then_else (match_operator:SI 0 "cmp_op"
138+ [(match_operand:SI 1 "register_operand" "d")
139+ (match_operand:SI 2 "register_operand" "d")
140 ])
141 (label_ref (match_operand 3))
142 (pc)))
143@@ -2349,6 +2369,47 @@ else
144 (set_attr "length" "12")]
145 )
146
147+(define_insn "long_branch_compare"
148+ [(set (pc)
149+ (if_then_else (match_operator 0 "cmp_op"
150+ [(match_operand 1 "register_operand" "d")
151+ (match_operand 2 "register_operand" "d")
152+ ])
153+ (label_ref (match_operand 3))
154+ (pc)))
155+ (clobber(reg:DI R_TMP))]
156+ "TARGET_MB_64"
157+ {
158+ operands[4] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
159+ enum rtx_code code = GET_CODE (operands[0]);
160+
161+ if (code == GT || code == LE)
162+ {
163+ output_asm_insn ("cmpl\tr18,%z1,%z2", operands);
164+ code = swap_condition (code);
165+ }
166+ else if (code == GTU || code == LEU)
167+ {
168+ output_asm_insn ("cmplu\tr18,%z1,%z2", operands);
169+ code = swap_condition (code);
170+ }
171+ else if (code == GE || code == LT)
172+ {
173+ output_asm_insn ("cmpl\tr18,%z2,%z1", operands);
174+ }
175+ else if (code == GEU || code == LTU)
176+ {
177+ output_asm_insn ("cmplu\tr18,%z2,%z1", operands);
178+ }
179+
180+ operands[0] = gen_rtx_fmt_ee (signed_condition (code), DImode, operands[4], const0_rtx);
181+ return "beal%C0i%?\tr18,%3";
182+ }
183+ [(set_attr "type" "branch")
184+ (set_attr "mode" "none")
185+ (set_attr "length" "12")]
186+)
187+
188 (define_insn "branch_compare"
189 [(set (pc)
190 (if_then_else (match_operator:SI 0 "cmp_op"
191@@ -2431,74 +2492,6 @@ else
192
193 })
194
195-;; Used to implement comparison instructions
196-(define_expand "long_condjump"
197- [(set (pc)
198- (if_then_else (match_operand 0)
199- (label_ref (match_operand 1))
200- (pc)))])
201-
202-(define_insn "long_branch_zero"
203- [(set (pc)
204- (if_then_else (match_operator:DI 0 "ordered_comparison_operator"
205- [(match_operand:DI 1 "register_operand" "d")
206- (const_int 0)])
207- (match_operand:DI 2 "pc_or_label_operand" "")
208- (match_operand:DI 3 "pc_or_label_operand" "")))
209- ]
210- "TARGET_MB_64"
211- {
212- if (operands[3] == pc_rtx)
213- return "beal%C0i%?\t%z1,%2";
214- else
215- return "beal%N0i%?\t%z1,%3";
216- }
217- [(set_attr "type" "branch")
218- (set_attr "mode" "none")
219- (set_attr "length" "4")]
220-)
221-
222-(define_insn "long_branch_compare"
223- [(set (pc)
224- (if_then_else (match_operator:DI 0 "cmp_op"
225- [(match_operand:DI 1 "register_operand" "d")
226- (match_operand:DI 2 "register_operand" "d")
227- ])
228- (label_ref (match_operand 3))
229- (pc)))
230- (clobber(reg:DI R_TMP))]
231- "TARGET_MB_64"
232- {
233- operands[4] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
234- enum rtx_code code = GET_CODE (operands[0]);
235-
236- if (code == GT || code == LE)
237- {
238- output_asm_insn ("cmpl\tr18,%z1,%z2", operands);
239- code = swap_condition (code);
240- }
241- else if (code == GTU || code == LEU)
242- {
243- output_asm_insn ("cmplu\tr18,%z1,%z2", operands);
244- code = swap_condition (code);
245- }
246- else if (code == GE || code == LT)
247- {
248- output_asm_insn ("cmpl\tr18,%z2,%z1", operands);
249- }
250- else if (code == GEU || code == LTU)
251- {
252- output_asm_insn ("cmplu\tr18,%z2,%z1", operands);
253- }
254-
255- operands[0] = gen_rtx_fmt_ee (signed_condition (code), DImode, operands[4], const0_rtx);
256- return "beal%C0i%?\tr18,%3";
257- }
258- [(set_attr "type" "branch")
259- (set_attr "mode" "none")
260- (set_attr "length" "12")]
261-)
262-
263 ;;----------------------------------------------------------------
264 ;; Unconditional branches
265 ;;----------------------------------------------------------------
266--
2672.34.1
268
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0030-previous-commit-broke-the-handling-of-SI-Branch-comp.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0030-previous-commit-broke-the-handling-of-SI-Branch-comp.patch
new file mode 100644
index 00000000..92951b08
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0030-previous-commit-broke-the-handling-of-SI-Branch-comp.patch
@@ -0,0 +1,28 @@
1From e4713a382c1e6729cd3228284def9fa59da70028 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Wed, 8 Aug 2018 17:37:26 +0530
4Subject: [PATCH 30/54] previous commit broke the handling of SI Branch compare
5 for Microblaze 32-bit..
6
7---
8 gcc/config/microblaze/microblaze.md | 4 ++--
9 1 file changed, 2 insertions(+), 2 deletions(-)
10
11diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
12index 31bf04e4abd..e37a7704195 100644
13--- a/gcc/config/microblaze/microblaze.md
14+++ b/gcc/config/microblaze/microblaze.md
15@@ -2224,8 +2224,8 @@ else
16 (define_expand "cbranchsi4"
17 [(set (pc)
18 (if_then_else (match_operator 0 "ordered_comparison_operator"
19- [(match_operand 1 "register_operand")
20- (match_operand 2 "arith_operand" "I,i")])
21+ [(match_operand:SI 1 "register_operand")
22+ (match_operand:SI 2 "arith_operand" "I,i")])
23 (label_ref (match_operand 3 ""))
24 (pc)))]
25 ""
26--
272.34.1
28
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0031-Support-of-multilibs-with-m64.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0031-Support-of-multilibs-with-m64.patch
new file mode 100644
index 00000000..40009bf0
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0031-Support-of-multilibs-with-m64.patch
@@ -0,0 +1,77 @@
1From 0673e986a5c06cba6507e0361ebdb9cf309f6a4c Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Tue, 11 Sep 2018 13:43:48 +0530
4Subject: [PATCH 31/54] Support of multilibs with m64 ...
5
6Conflicts:
7 gcc/config/microblaze/microblaze-c.c
8
9signed-off-by : Mahesh Bodapati <mbodapat@xilinx.com>
10---
11 gcc/config/microblaze/microblaze-c.cc | 1 +
12 gcc/config/microblaze/t-microblaze | 15 ++++++---------
13 libgcc/config/microblaze/t-microblaze | 11 +++--------
14 3 files changed, 10 insertions(+), 17 deletions(-)
15
16diff --git a/gcc/config/microblaze/microblaze-c.cc b/gcc/config/microblaze/microblaze-c.cc
17index af73de0709c..c7cb139d25a 100644
18--- a/gcc/config/microblaze/microblaze-c.cc
19+++ b/gcc/config/microblaze/microblaze-c.cc
20@@ -102,6 +102,7 @@ microblaze_cpp_define (cpp_reader *pfile)
21 }
22 if (TARGET_MB_64)
23 {
24+ builtin_define ("__microblaze64");
25 builtin_define ("__arch64__");
26 builtin_define ("__microblaze64__");
27 builtin_define ("__MICROBLAZE64__");
28diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze
29index 965132b3513..47b869b9303 100644
30--- a/gcc/config/microblaze/t-microblaze
31+++ b/gcc/config/microblaze/t-microblaze
32@@ -1,12 +1,9 @@
33-MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high mlittle-endian m64
34-MULTILIB_DIRNAMES = bs m mh le m64
35-MULTILIB_EXCEPTIONS = *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high
36-MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian
37-MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian/m64
38-MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/m64 mxl-multiply-high
39-MULTILIB_EXCEPTIONS += mxl-multiply-high/mlittle-endian
40-MULTILIB_EXCEPTIONS += mxl-multiply-high/m64
41-MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64
42+MULTILIB_OPTIONS = m64 mxl-barrel-shift mlittle-endian mno-xl-soft-mul mxl-multiply-high
43+MULTILIB_DIRNAMES = m64 bs le m mh
44+MULTILIB_EXCEPTIONS = *m64/mxl-multiply-high mxl-multiply-high
45+MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high
46+MULTILIB_EXCEPTIONS += *mlittle-endian/mxl-multiply-high mxl-multiply-high
47+MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mlittle-endian/mxl-multiply-high
48
49 # Extra files
50 microblaze-c.o: $(srcdir)/config/microblaze/microblaze-c.cc \
51diff --git a/libgcc/config/microblaze/t-microblaze b/libgcc/config/microblaze/t-microblaze
52index 35021b24b7d..8d954a49575 100644
53--- a/libgcc/config/microblaze/t-microblaze
54+++ b/libgcc/config/microblaze/t-microblaze
55@@ -1,16 +1,11 @@
56-LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3 \
57- _divdi3 _moddi3 _muldi3 _udivdi3 _umoddi3
58+LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3
59
60 LIB2ADD += \
61 $(srcdir)/config/microblaze/divsi3.S \
62- $(srcdir)/config/microblaze/divdi3.S \
63 $(srcdir)/config/microblaze/modsi3.S \
64- $(srcdir)/config/microblaze/moddi3.S \
65+ $(srcdir)/config/microblaze/muldi3_hard.S \
66 $(srcdir)/config/microblaze/mulsi3.S \
67- $(srcdir)/config/microblaze/muldi3.S \
68 $(srcdir)/config/microblaze/stack_overflow_exit.S \
69 $(srcdir)/config/microblaze/udivsi3.S \
70- $(srcdir)/config/microblaze/udivdi3.S \
71 $(srcdir)/config/microblaze/umodsi3.S \
72- $(srcdir)/config/microblaze/umoddi3.S \
73- $(srcdir)/config/microblaze/divsi3_table.c \
74+ $(srcdir)/config/microblaze/divsi3_table.c
75--
762.34.1
77
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0032-Fixed-issues-like-1-Interrupt-alignment-issue-2-Sign.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0032-Fixed-issues-like-1-Interrupt-alignment-issue-2-Sign.patch
new file mode 100644
index 00000000..df7ef8da
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0032-Fixed-issues-like-1-Interrupt-alignment-issue-2-Sign.patch
@@ -0,0 +1,70 @@
1From 63e3adfb493e225c55536e72cfbf8be70977cdc8 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Tue, 13 Sep 2022 15:24:25 +0530
4Subject: [PATCH 32/54] Fixed issues like: 1 Interrupt alignment issue 2 Sign
5 extension issue
6
7---
8 gcc/config/microblaze/microblaze.cc | 16 ++++++++++------
9 gcc/config/microblaze/microblaze.md | 2 +-
10 2 files changed, 11 insertions(+), 7 deletions(-)
11
12diff --git a/gcc/config/microblaze/microblaze.cc b/gcc/config/microblaze/microblaze.cc
13index de3c95a005e..6fbecb43e4a 100644
14--- a/gcc/config/microblaze/microblaze.cc
15+++ b/gcc/config/microblaze/microblaze.cc
16@@ -2183,9 +2183,14 @@ compute_frame_size (HOST_WIDE_INT size)
17
18 total_size += gp_reg_size;
19
20- /* Add 4 bytes for MSR. */
21+ /* Add 4/8 bytes for MSR. */
22 if (microblaze_is_interrupt_variant ())
23- total_size += 4;
24+ {
25+ if (TARGET_MB_64)
26+ total_size += 8;
27+ else
28+ total_size += 4;
29+ }
30
31 /* No space to be allocated for link register in leaf functions with no other
32 stack requirements. */
33@@ -2470,7 +2475,6 @@ print_operand (FILE * file, rtx op, int letter)
34 else if (letter == 'h' || letter == 'j')
35 {
36 long val[2];
37- int val1[2];
38 long l[2];
39 if (code == CONST_DOUBLE)
40 {
41@@ -2485,10 +2489,10 @@ print_operand (FILE * file, rtx op, int letter)
42 }
43 else if (code == CONST_INT || code == CONST)// || code == SYMBOL_REF ||code == LABEL_REF)
44 {
45- val1[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32;
46- val1[1] = INTVAL (op) & 0x00000000ffffffffLL;
47+ val[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32;
48+ val[1] = INTVAL (op) & 0x00000000ffffffffLL;
49 }
50- fprintf (file, "0x%8.8lx", (letter == 'h') ? val1[0] : val1[1]);
51+ fprintf (file, "0x%8.8lx", (letter == 'h') ? val[0] : val[1]);
52 }
53 else if (code == CONST_DOUBLE)
54 {
55diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
56index e37a7704195..72c2a9a38cd 100644
57--- a/gcc/config/microblaze/microblaze.md
58+++ b/gcc/config/microblaze/microblaze.md
59@@ -1096,7 +1096,7 @@
60 case 1:
61 case 2:
62 {
63- output_asm_insn ("ll%i1\t%0,%1", operands);
64+ output_asm_insn ("lw%i1\t%0,%1", operands);
65 return "sextl32\t%0,%0";
66 }
67 }
68--
692.34.1
70
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0033-fixed-below-issues-Floating-point-print-issues-in-64.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0033-fixed-below-issues-Floating-point-print-issues-in-64.patch
new file mode 100644
index 00000000..cf1076ea
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0033-fixed-below-issues-Floating-point-print-issues-in-64.patch
@@ -0,0 +1,304 @@
1From 58d4d2ca4fdf90d9d21e7813a599b3491f52e34d Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Tue, 13 Sep 2022 15:28:58 +0530
4Subject: [PATCH 33/54] fixed below issues: - Floating point print issues in
5 64bit mode - Dejagnu Jump related issues - Added dbl instruction
6
7 Conflicts:
8 gcc/config/microblaze/microblaze.md
9---
10 gcc/config/microblaze/microblaze.cc | 12 +++-
11 gcc/config/microblaze/microblaze.h | 7 +++
12 gcc/config/microblaze/microblaze.md | 86 ++++++++++++++++++++++++-----
13 libgcc/config/microblaze/crti.S | 24 +++++++-
14 libgcc/config/microblaze/crtn.S | 13 +++++
15 5 files changed, 125 insertions(+), 17 deletions(-)
16
17diff --git a/gcc/config/microblaze/microblaze.cc b/gcc/config/microblaze/microblaze.cc
18index 6fbecb43e4a..965a041ea8c 100644
19--- a/gcc/config/microblaze/microblaze.cc
20+++ b/gcc/config/microblaze/microblaze.cc
21@@ -2479,7 +2479,12 @@ print_operand (FILE * file, rtx op, int letter)
22 if (code == CONST_DOUBLE)
23 {
24 if (GET_MODE (op) == DFmode)
25- REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val);
26+ {
27+ if (TARGET_MB_64)
28+ REAL_VALUE_TO_TARGET_LONG_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val);
29+ else
30+ REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val);
31+ }
32 else
33 {
34 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), l);
35@@ -3886,7 +3891,10 @@ microblaze_expand_divide (rtx operands[])
36 gen_rtx_PLUS (QImode, regt1, div_table_rtx));
37
38 insn = emit_insn (gen_zero_extendqisi2(operands[0],mem_rtx));
39- jump = emit_jump_insn_after (gen_jump (div_end_label), insn);
40+ if (TARGET_MB_64)
41+ jump = emit_jump_insn_after (gen_jump_64 (div_end_label), insn);
42+ else
43+ jump = emit_jump_insn_after (gen_jump (div_end_label), insn);
44 JUMP_LABEL (jump) = div_end_label;
45 LABEL_NUSES (div_end_label) = 1;
46 emit_barrier ();
47diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
48index 3aee003de0d..145368db8b8 100644
49--- a/gcc/config/microblaze/microblaze.h
50+++ b/gcc/config/microblaze/microblaze.h
51@@ -888,10 +888,17 @@ do { \
52 /* We do this to save a few 10s of code space that would be taken up
53 by the call_FUNC () wrappers, used by the generic CRT_CALL_STATIC_FUNCTION
54 definition in crtstuff.c. */
55+#ifdef __arch64__
56+#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
57+ asm ( SECTION_OP "\n" \
58+ "\tbrealid r15, " #FUNC "\n\t nop\n" \
59+ TEXT_SECTION_ASM_OP);
60+#else
61 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
62 asm ( SECTION_OP "\n" \
63 "\tbrlid r15, " #FUNC "\n\t nop\n" \
64 TEXT_SECTION_ASM_OP);
65+#endif
66
67 /* We need to group -lm as well, since some Newlib math functions
68 reference __errno! */
69diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
70index 72c2a9a38cd..b3d265d9941 100644
71--- a/gcc/config/microblaze/microblaze.md
72+++ b/gcc/config/microblaze/microblaze.md
73@@ -527,6 +527,15 @@
74 (set_attr "mode" "SF")
75 (set_attr "length" "4")])
76
77+(define_insn "floatdidf2"
78+ [(set (match_operand:DF 0 "register_operand" "=d")
79+ (float:DF (match_operand:DI 1 "register_operand" "d")))]
80+ "TARGET_MB_64"
81+ "dbl\t%0,%1"
82+ [(set_attr "type" "fcvt")
83+ (set_attr "mode" "DF")
84+ (set_attr "length" "4")])
85+
86 (define_insn "fix_truncsfsi2"
87 [(set (match_operand:SI 0 "register_operand" "=d")
88 (fix:SI (match_operand:SF 1 "register_operand" "d")))]
89@@ -1299,7 +1308,7 @@
90 (define_insn "movdi_long_int"
91 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
92 (match_operand:DI 1 "general_operand" "i"))]
93- ""
94+ "TARGET_MB_64"
95 "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
96 [(set_attr "type" "no_delay_arith")
97 (set_attr "mode" "DI")
98@@ -1582,7 +1591,7 @@
99 return "ll%i1\t%0,%1";
100 case 3:
101 {
102- return "addlik\t%0,r0,%h1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #Xfer Lo";
103+ return "addlik\t%0,r0,%j1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%h1 #Xfer Lo";
104 }
105 case 5:
106 return "sl%i0\t%1,%0";
107@@ -2371,9 +2380,9 @@ else
108
109 (define_insn "long_branch_compare"
110 [(set (pc)
111- (if_then_else (match_operator 0 "cmp_op"
112- [(match_operand 1 "register_operand" "d")
113- (match_operand 2 "register_operand" "d")
114+ (if_then_else (match_operator:DI 0 "cmp_op"
115+ [(match_operand:DI 1 "register_operand" "d")
116+ (match_operand:DI 2 "register_operand" "d")
117 ])
118 (label_ref (match_operand 3))
119 (pc)))
120@@ -2495,6 +2504,20 @@ else
121 ;;----------------------------------------------------------------
122 ;; Unconditional branches
123 ;;----------------------------------------------------------------
124+(define_insn "jump_64"
125+ [(set (pc)
126+ (label_ref (match_operand 0 "" "")))]
127+ "TARGET_MB_64"
128+ {
129+ if (GET_CODE (operands[0]) == REG)
130+ return "brea%?\t%0";
131+ else
132+ return "breai%?\t%l0";
133+ }
134+ [(set_attr "type" "jump")
135+ (set_attr "mode" "none")
136+ (set_attr "length" "4")])
137+
138 (define_insn "jump"
139 [(set (pc)
140 (label_ref (match_operand 0 "" "")))]
141@@ -2540,17 +2563,25 @@ else
142 {
143 //gcc_assert (GET_MODE (operands[0]) == Pmode);
144
145- if (!flag_pic || TARGET_PIC_DATA_TEXT_REL)
146- emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1]));
147- else
148- emit_jump_insn (gen_tablejump_internal3 (operands[0], operands[1]));
149+ if (!flag_pic || TARGET_PIC_DATA_TEXT_REL) {
150+ if (!TARGET_MB_64)
151+ emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1]));
152+ else
153+ emit_jump_insn (gen_tablejump_internal2 (operands[0], operands[1]));
154+ }
155+ else {
156+ if (!TARGET_MB_64)
157+ emit_jump_insn (gen_tablejump_internal3 (operands[0], operands[1]));
158+ else
159+ emit_jump_insn (gen_tablejump_internal4 (operands[0], operands[1]));
160+ }
161 DONE;
162 }
163 )
164
165 (define_insn "tablejump_internal1"
166 [(set (pc)
167- (match_operand 0 "register_operand" "d"))
168+ (match_operand:SI 0 "register_operand" "d"))
169 (use (label_ref (match_operand 1 "" "")))]
170 ""
171 "bra%?\t%0 "
172@@ -2558,11 +2589,21 @@ else
173 (set_attr "mode" "none")
174 (set_attr "length" "4")])
175
176+(define_insn "tablejump_internal2"
177+ [(set (pc)
178+ (match_operand:DI 0 "register_operand" "d"))
179+ (use (label_ref (match_operand 1 "" "")))]
180+ "TARGET_MB_64"
181+ "bra%?\t%0 "
182+ [(set_attr "type" "jump")
183+ (set_attr "mode" "none")
184+ (set_attr "length" "4")])
185+
186 (define_expand "tablejump_internal3"
187 [(parallel [(set (pc)
188- (plus (match_operand 0 "register_operand" "d")
189- (label_ref (match_operand:SI 1 "" ""))))
190- (use (label_ref (match_dup 1)))])]
191+ (plus:SI (match_operand:SI 0 "register_operand" "d")
192+ (label_ref:SI (match_operand:SI 1 "" ""))))
193+ (use (label_ref:SI (match_dup 1)))])]
194 ""
195 ""
196 )
197@@ -2593,6 +2634,23 @@ else
198 ""
199 )
200
201+(define_insn ""
202+ [(set (pc)
203+ (plus:DI (match_operand:DI 0 "register_operand" "d")
204+ (label_ref:DI (match_operand 1 "" ""))))
205+ (use (label_ref:DI (match_dup 1)))]
206+ "TARGET_MB_64 && NEXT_INSN (as_a <rtx_insn *> (operands[1])) != 0
207+ && GET_CODE (PATTERN (NEXT_INSN (as_a <rtx_insn *> (operands[1])))) == ADDR_DIFF_VEC
208+ && flag_pic"
209+ {
210+ output_asm_insn ("addlk\t%0,%0,r20",operands);
211+ return "bra%?\t%0";
212+}
213+ [(set_attr "type" "jump")
214+ (set_attr "mode" "none")
215+ (set_attr "length" "4")])
216+
217+
218 ;;----------------------------------------------------------------
219 ;; Function prologue/epilogue and stack allocation
220 ;;----------------------------------------------------------------
221@@ -3101,7 +3159,7 @@ else
222 ;; The insn to set GOT. The hardcoded number "8" accounts for $pc difference
223 ;; between "mfs" and "addik" instructions.
224 (define_insn "set_got"
225- [(set (match_operand:SI 0 "register_operand" "=r")
226+ [(set (match_operand 0 "register_operand" "=r")
227 (unspec:SI [(const_int 0)] UNSPEC_SET_GOT))]
228 ""
229 "mfs\t%0,rpc\n\taddik\t%0,%0,_GLOBAL_OFFSET_TABLE_+8"
230diff --git a/libgcc/config/microblaze/crti.S b/libgcc/config/microblaze/crti.S
231index 1a89a0a2ffa..7cf5664880b 100644
232--- a/libgcc/config/microblaze/crti.S
233+++ b/libgcc/config/microblaze/crti.S
234@@ -33,11 +33,32 @@
235 .section .init, "ax"
236 .global __init
237
238+#ifdef __arch64__
239 .weak _stack
240- .set _stack, 0xffffffff
241+ .set _stack, 0xffffffffffffffff
242 .weak _stack_end
243 .set _stack_end, 0
244
245+ .align 3
246+__init:
247+ addlik r1, r1, -32
248+ sl r15, r0, r1
249+ addlik r11, r0, _stack
250+ mts rshr, r11
251+ addlik r11, r0, _stack_end
252+ mts rslr, r11
253+
254+ .section .fini, "ax"
255+ .global __fini
256+ .align 3
257+__fini:
258+ addlik r1, r1, -32
259+ sl r15, r0, r1
260+#else
261+ .weak _stack
262+ .set _stack, 0xffffffff
263+ .weak _stack_end
264+ .set _stack_end, 0
265 .align 2
266 __init:
267 addik r1, r1, -16
268@@ -53,3 +74,4 @@ __init:
269 __fini:
270 addik r1, r1, -16
271 sw r15, r0, r1
272+#endif
273diff --git a/libgcc/config/microblaze/crtn.S b/libgcc/config/microblaze/crtn.S
274index 29a004973ae..9697b247b6c 100644
275--- a/libgcc/config/microblaze/crtn.S
276+++ b/libgcc/config/microblaze/crtn.S
277@@ -29,7 +29,19 @@
278 .section .note.GNU-stack,"",%progbits
279 .previous
280 #endif
281+#ifdef __arch64__
282+ .section .init, "ax"
283+ ll r15, r0, r1
284+ addlik r1, r1, 32
285+ rtsd r15, 8
286+ nop
287
288+ .section .fini, "ax"
289+ ll r15, r0, r1
290+ addlik r1, r1, 32
291+ rtsd r15, 8
292+ nop
293+#else
294 .section .init, "ax"
295 lw r15, r0, r1
296 rtsd r15, 8
297@@ -39,3 +51,4 @@
298 lw r15, r0, r1
299 rtsd r15, 8
300 addik r1, r1, 16
301+#endif
302--
3032.34.1
304
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0034-Added-double-arith-instructions-Fixed-prologue-stack.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0034-Added-double-arith-instructions-Fixed-prologue-stack.patch
new file mode 100644
index 00000000..ab50b599
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0034-Added-double-arith-instructions-Fixed-prologue-stack.patch
@@ -0,0 +1,135 @@
1From 924a756b5c9edc5d626f68323f67ced2800c75ff Mon Sep 17 00:00:00 2001
2From: Nagaraju Mekala <nmekala@xilix.com>
3Date: Tue, 9 Oct 2018 10:07:08 +0530
4Subject: [PATCH 34/54] -Added double arith instructions -Fixed prologue stack
5 pointer decrement issue
6
7---
8 gcc/config/microblaze/microblaze.md | 78 +++++++++++++++++++++++++----
9 gcc/config/microblaze/t-microblaze | 7 +++
10 2 files changed, 76 insertions(+), 9 deletions(-)
11
12diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
13index b3d265d9941..0f769f320b2 100644
14--- a/gcc/config/microblaze/microblaze.md
15+++ b/gcc/config/microblaze/microblaze.md
16@@ -527,6 +527,66 @@
17 (set_attr "mode" "SF")
18 (set_attr "length" "4")])
19
20+(define_insn "fix_truncsfsi2"
21+ [(set (match_operand:SI 0 "register_operand" "=d")
22+ (fix:SI (match_operand:SF 1 "register_operand" "d")))]
23+ "TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
24+ "fint\t%0,%1"
25+ [(set_attr "type" "fint")
26+ (set_attr "mode" "SF")
27+ (set_attr "length" "4")])
28+
29+
30+(define_insn "adddf3"
31+ [(set (match_operand:DF 0 "register_operand" "=d")
32+ (plus:DF (match_operand:DF 1 "register_operand" "d")
33+ (match_operand:DF 2 "register_operand" "d")))]
34+ "TARGET_MB_64"
35+ "dadd\t%0,%1,%2"
36+ [(set_attr "type" "fadd")
37+ (set_attr "mode" "DF")
38+ (set_attr "length" "4")])
39+
40+(define_insn "subdf3"
41+ [(set (match_operand:DF 0 "register_operand" "=d")
42+ (minus:DF (match_operand:DF 1 "register_operand" "d")
43+ (match_operand:DF 2 "register_operand" "d")))]
44+ "TARGET_MB_64"
45+ "drsub\t%0,%2,%1"
46+ [(set_attr "type" "frsub")
47+ (set_attr "mode" "DF")
48+ (set_attr "length" "4")])
49+
50+(define_insn "muldf3"
51+ [(set (match_operand:DF 0 "register_operand" "=d")
52+ (mult:DF (match_operand:DF 1 "register_operand" "d")
53+ (match_operand:DF 2 "register_operand" "d")))]
54+ "TARGET_MB_64"
55+ "dmul\t%0,%1,%2"
56+ [(set_attr "type" "fmul")
57+ (set_attr "mode" "DF")
58+ (set_attr "length" "4")])
59+
60+(define_insn "divdf3"
61+ [(set (match_operand:DF 0 "register_operand" "=d")
62+ (div:DF (match_operand:DF 1 "register_operand" "d")
63+ (match_operand:DF 2 "register_operand" "d")))]
64+ "TARGET_MB_64"
65+ "ddiv\t%0,%2,%1"
66+ [(set_attr "type" "fdiv")
67+ (set_attr "mode" "DF")
68+ (set_attr "length" "4")])
69+
70+
71+(define_insn "sqrtdf2"
72+ [(set (match_operand:DF 0 "register_operand" "=d")
73+ (sqrt:DF (match_operand:DF 1 "register_operand" "d")))]
74+ "TARGET_MB_64"
75+ "dsqrt\t%0,%1"
76+ [(set_attr "type" "fsqrt")
77+ (set_attr "mode" "DF")
78+ (set_attr "length" "4")])
79+
80 (define_insn "floatdidf2"
81 [(set (match_operand:DF 0 "register_operand" "=d")
82 (float:DF (match_operand:DI 1 "register_operand" "d")))]
83@@ -536,13 +596,13 @@
84 (set_attr "mode" "DF")
85 (set_attr "length" "4")])
86
87-(define_insn "fix_truncsfsi2"
88- [(set (match_operand:SI 0 "register_operand" "=d")
89- (fix:SI (match_operand:SF 1 "register_operand" "d")))]
90- "TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
91- "fint\t%0,%1"
92- [(set_attr "type" "fint")
93- (set_attr "mode" "SF")
94+(define_insn "floatdfdi2"
95+ [(set (match_operand:DI 0 "register_operand" "=d")
96+ (float:DI (match_operand:DF 1 "register_operand" "d")))]
97+ "TARGET_MB_64"
98+ "dlong\t%0,%1"
99+ [(set_attr "type" "fcvt")
100+ (set_attr "mode" "DI")
101 (set_attr "length" "4")])
102
103 ;;----------------------------------------------------------------
104@@ -660,8 +720,8 @@
105 "TARGET_MB_64"
106 "@
107 rsubl\t%0,%2,%1
108- addik\t%0,%z1,-%2
109- addik\t%0,%z1,-%2"
110+ addlik\t%0,%z1,-%2
111+ addlik\t%0,%z1,-%2"
112 [(set_attr "type" "arith,no_delay_arith,no_delay_arith")
113 (set_attr "mode" "DI")
114 (set_attr "length" "4,4,4")])
115diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze
116index 47b869b9303..3522afd4831 100644
117--- a/gcc/config/microblaze/t-microblaze
118+++ b/gcc/config/microblaze/t-microblaze
119@@ -1,6 +1,13 @@
120 MULTILIB_OPTIONS = m64 mxl-barrel-shift mlittle-endian mno-xl-soft-mul mxl-multiply-high
121 MULTILIB_DIRNAMES = m64 bs le m mh
122 MULTILIB_EXCEPTIONS = *m64/mxl-multiply-high mxl-multiply-high
123+MULTILIB_EXCEPTIONS += *m64
124+MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift
125+MULTILIB_EXCEPTIONS += *m64/mno-xl-soft-mul
126+MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mno-xl-soft-mul
127+MULTILIB_EXCEPTIONS += *m64/mno-xl-soft-mul
128+MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mno-xl-soft-mul/mxl-multiply-high
129+MULTILIB_EXCEPTIONS += *m64/mno-xl-soft-mul/mxl-multiply-high
130 MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high
131 MULTILIB_EXCEPTIONS += *mlittle-endian/mxl-multiply-high mxl-multiply-high
132 MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mlittle-endian/mxl-multiply-high
133--
1342.34.1
135
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0035-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0035-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch
new file mode 100644
index 00000000..589ca998
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0035-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch
@@ -0,0 +1,37 @@
1From 3ebc7f9a11d66843982544cd0f88f35cc4defb83 Mon Sep 17 00:00:00 2001
2From: Nagaraju Mekala <nmekala@xilix.com>
3Date: Fri, 12 Oct 2018 16:07:36 +0530
4Subject: [PATCH 35/54] Fixed the issue in the delay slot with swap
5 instructions
6
7---
8 gcc/config/microblaze/microblaze.md | 6 ++++++
9 1 file changed, 6 insertions(+)
10
11diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
12index 0f769f320b2..6ada55ac2bc 100644
13--- a/gcc/config/microblaze/microblaze.md
14+++ b/gcc/config/microblaze/microblaze.md
15@@ -443,6 +443,9 @@
16 (bswap:SI (match_operand:SI 1 "register_operand" "r")))]
17 "TARGET_REORDER"
18 "swapb %0, %1"
19+ [(set_attr "type" "no_delay_arith")
20+ (set_attr "mode" "SI")
21+ (set_attr "length" "4")]
22 )
23
24 (define_insn "bswaphi2"
25@@ -451,6 +454,9 @@
26 "TARGET_REORDER"
27 "swapb %0, %1
28 swaph %0, %0"
29+ [(set_attr "type" "no_delay_arith")
30+ (set_attr "mode" "SI")
31+ (set_attr "length" "8")]
32 )
33
34 ;;----------------------------------------------------------------
35--
362.34.1
37
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0036-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0036-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch
new file mode 100644
index 00000000..8431cb16
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0036-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch
@@ -0,0 +1,256 @@
1From 9ea2aee3599d2f1fc9d67c7a72cd7c826272a2fa Mon Sep 17 00:00:00 2001
2From: Nagaraju Mekala <nmekala@xilix.com>
3Date: Sat, 13 Oct 2018 21:12:43 +0530
4Subject: [PATCH 36/54] Fixed the load store issue with the 32bit arith
5 libraries
6
7---
8 libgcc/config/microblaze/divsi3.S | 25 ++++++++++++++++++++++++-
9 libgcc/config/microblaze/modsi3.S | 26 +++++++++++++++++++++++++-
10 libgcc/config/microblaze/mulsi3.S | 3 +++
11 libgcc/config/microblaze/udivsi3.S | 24 +++++++++++++++++++++++-
12 libgcc/config/microblaze/umodsi3.S | 24 +++++++++++++++++++++++-
13 5 files changed, 98 insertions(+), 4 deletions(-)
14
15diff --git a/libgcc/config/microblaze/divsi3.S b/libgcc/config/microblaze/divsi3.S
16index a449fedd53e..9f04f59104e 100644
17--- a/libgcc/config/microblaze/divsi3.S
18+++ b/libgcc/config/microblaze/divsi3.S
19@@ -41,6 +41,17 @@
20 .globl __divsi3
21 .ent __divsi3
22 .type __divsi3,@function
23+#ifdef __arch64__
24+ .align 3
25+__divsi3:
26+ .frame r1,0,r15
27+
28+ ADDIK r1,r1,-32
29+ SLI r28,r1,0
30+ SLI r29,r1,8
31+ SLI r30,r1,16
32+ SLI r31,r1,24
33+#else
34 __divsi3:
35 .frame r1,0,r15
36
37@@ -49,7 +60,7 @@ __divsi3:
38 SWI r29,r1,4
39 SWI r30,r1,8
40 SWI r31,r1,12
41-
42+#endif
43 BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error
44 BEQI r5,$LaResult_Is_Zero # Result is Zero
45 BGEID r5,$LaR5_Pos
46@@ -89,6 +100,17 @@ $LaLOOP_END:
47 $LaDiv_By_Zero:
48 $LaResult_Is_Zero:
49 OR r3,r0,r0 # set result to 0
50+#ifdef __arch64__
51+$LaRETURN_HERE:
52+# Restore values of CSRs and that of r3 and the divisor and the dividend
53+ LLI r28,r1,0
54+ LLI r29,r1,8
55+ LLI r30,r1,16
56+ LLI r31,r1,24
57+ ADDLIK r1,r1,32
58+ RTSD r15,8
59+ NOP
60+#else
61 $LaRETURN_HERE:
62 # Restore values of CSRs and that of r3 and the divisor and the dividend
63 LWI r28,r1,0
64@@ -97,6 +119,7 @@ $LaRETURN_HERE:
65 LWI r31,r1,12
66 RTSD r15,8
67 ADDIK r1,r1,16
68+#endif
69 .end __divsi3
70 .size __divsi3, . - __divsi3
71
72diff --git a/libgcc/config/microblaze/modsi3.S b/libgcc/config/microblaze/modsi3.S
73index 282fabfd966..d2f9dc770e4 100644
74--- a/libgcc/config/microblaze/modsi3.S
75+++ b/libgcc/config/microblaze/modsi3.S
76@@ -41,6 +41,17 @@
77 .globl __modsi3
78 .ent __modsi3
79 .type __modsi3,@function
80+#ifdef __arch64__
81+ .align 3
82+__modsi3:
83+ .frame r1,0,r15
84+
85+ addlik r1,r1,-32
86+ sli r28,r1,0
87+ sli r29,r1,8
88+ sli r30,r1,16
89+ sli r31,r1,24
90+#else
91 __modsi3:
92 .frame r1,0,r15
93
94@@ -49,6 +60,7 @@ __modsi3:
95 swi r29,r1,4
96 swi r30,r1,8
97 swi r31,r1,12
98+#endif
99
100 BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error
101 BEQI r5,$LaResult_Is_Zero # Result is Zero
102@@ -88,6 +100,18 @@ $LaLOOP_END:
103 $LaDiv_By_Zero:
104 $LaResult_Is_Zero:
105 or r3,r0,r0 # set result to 0 [Both mod as well as div are 0]
106+
107+#ifdef __arch64__
108+$LaRETURN_HERE:
109+# Restore values of CSRs and that of r3 and the divisor and the dividend
110+ lli r28,r1,0
111+ lli r29,r1,8
112+ lli r30,r1,16
113+ lli r31,r1,24
114+ addik r1,r1,32
115+ rtsd r15,8
116+ nop
117+#else
118 $LaRETURN_HERE:
119 # Restore values of CSRs and that of r3 and the divisor and the dividend
120 lwi r28,r1,0
121@@ -95,7 +119,7 @@ $LaRETURN_HERE:
122 lwi r30,r1,8
123 lwi r31,r1,12
124 rtsd r15,8
125- addik r1,r1,16
126+#endif
127 .end __modsi3
128 .size __modsi3, . - __modsi3
129
130diff --git a/libgcc/config/microblaze/mulsi3.S b/libgcc/config/microblaze/mulsi3.S
131index 3da55416964..437e2bc309e 100644
132--- a/libgcc/config/microblaze/mulsi3.S
133+++ b/libgcc/config/microblaze/mulsi3.S
134@@ -41,6 +41,9 @@
135 .globl __mulsi3
136 .ent __mulsi3
137 .type __mulsi3,@function
138+#ifdef __arch64__
139+ .align 3
140+#endif
141 __mulsi3:
142 .frame r1,0,r15
143 add r3,r0,r0
144diff --git a/libgcc/config/microblaze/udivsi3.S b/libgcc/config/microblaze/udivsi3.S
145index 7f3fe99eb12..496dd6794bf 100644
146--- a/libgcc/config/microblaze/udivsi3.S
147+++ b/libgcc/config/microblaze/udivsi3.S
148@@ -41,6 +41,16 @@
149 .globl __udivsi3
150 .ent __udivsi3
151 .type __udivsi3,@function
152+#ifdef __arch64__
153+ .align 3
154+__udivsi3:
155+ .frame r1,0,r15
156+
157+ ADDLIK r1,r1,-24
158+ SLI r29,r1,0
159+ SLI r30,r1,8
160+ SLI r31,r1,16
161+#else
162 __udivsi3:
163 .frame r1,0,r15
164
165@@ -48,7 +58,7 @@ __udivsi3:
166 SWI r29,r1,0
167 SWI r30,r1,4
168 SWI r31,r1,8
169-
170+#endif
171 BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error
172 BEQID r5,$LaResult_Is_Zero # Result is Zero
173 ADDIK r30,r0,0 # Clear mod
174@@ -98,6 +108,17 @@ $LaLOOP_END:
175 $LaDiv_By_Zero:
176 $LaResult_Is_Zero:
177 OR r3,r0,r0 # set result to 0
178+
179+#ifdef __arch64__
180+$LaRETURN_HERE:
181+ # Restore values of CSRs and that of r3 and the divisor and the dividend
182+ LLI r29,r1,0
183+ LLI r30,r1,8
184+ LLI r31,r1,16
185+ ADDIK r1,r1,24
186+ RTSD r15,8
187+ NOP
188+#else
189 $LaRETURN_HERE:
190 # Restore values of CSRs and that of r3 and the divisor and the dividend
191 LWI r29,r1,0
192@@ -105,5 +126,6 @@ $LaRETURN_HERE:
193 LWI r31,r1,8
194 RTSD r15,8
195 ADDIK r1,r1,12
196+#endif
197 .end __udivsi3
198 .size __udivsi3, . - __udivsi3
199diff --git a/libgcc/config/microblaze/umodsi3.S b/libgcc/config/microblaze/umodsi3.S
200index 6c7f2b3c917..fffc784b4cb 100644
201--- a/libgcc/config/microblaze/umodsi3.S
202+++ b/libgcc/config/microblaze/umodsi3.S
203@@ -41,6 +41,16 @@
204 .globl __umodsi3
205 .ent __umodsi3
206 .type __umodsi3,@function
207+#ifdef __arch64__
208+ .align 3
209+__umodsi3:
210+ .frame r1,0,r15
211+
212+ addik r1,r1,-24
213+ swi r29,r1,0
214+ swi r30,r1,8
215+ swi r31,r1,16
216+#else
217 __umodsi3:
218 .frame r1,0,r15
219
220@@ -48,7 +58,7 @@ __umodsi3:
221 swi r29,r1,0
222 swi r30,r1,4
223 swi r31,r1,8
224-
225+#endif
226 BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error
227 BEQId r5,$LaResult_Is_Zero # Result is Zero
228 ADDIK r3,r0,0 # Clear div
229@@ -101,6 +111,17 @@ $LaLOOP_END:
230 $LaDiv_By_Zero:
231 $LaResult_Is_Zero:
232 or r3,r0,r0 # set result to 0
233+
234+#ifdef __arch64__
235+$LaRETURN_HERE:
236+# Restore values of CSRs and that of r3 and the divisor and the dividend
237+ lli r29,r1,0
238+ lli r30,r1,8
239+ lli r31,r1,16
240+ addlik r1,r1,24
241+ rtsd r15,8
242+ nop
243+#else
244 $LaRETURN_HERE:
245 # Restore values of CSRs and that of r3 and the divisor and the dividend
246 lwi r29,r1,0
247@@ -108,5 +129,6 @@ $LaRETURN_HERE:
248 lwi r31,r1,8
249 rtsd r15,8
250 addik r1,r1,12
251+#endif
252 .end __umodsi3
253 .size __umodsi3, . - __umodsi3
254--
2552.34.1
256
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0037-extending-the-Dwarf-support-to-64bit-Microblaze.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0037-extending-the-Dwarf-support-to-64bit-Microblaze.patch
new file mode 100644
index 00000000..8b0fa208
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0037-extending-the-Dwarf-support-to-64bit-Microblaze.patch
@@ -0,0 +1,25 @@
1From d2c971646ce103fa17cc32474cb942268bc59258 Mon Sep 17 00:00:00 2001
2From: Nagaraju Mekala <nmekala@xilix.com>
3Date: Mon, 15 Oct 2018 12:00:10 +0530
4Subject: [PATCH 37/54] extending the Dwarf support to 64bit Microblaze
5
6---
7 gcc/config/microblaze/microblaze.h | 2 +-
8 1 file changed, 1 insertion(+), 1 deletion(-)
9
10diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
11index 145368db8b8..4258dcde0d1 100644
12--- a/gcc/config/microblaze/microblaze.h
13+++ b/gcc/config/microblaze/microblaze.h
14@@ -207,7 +207,7 @@ extern enum pipeline_type microblaze_pipe;
15 /* Use DWARF 2 debugging information by default. */
16 #define DWARF2_DEBUGGING_INFO 1
17 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
18-#define DWARF2_ADDR_SIZE 4
19+#define DWARF2_ADDR_SIZE (TARGET_MB_64 ? 8 : 4)
20
21 /* Target machine storage layout */
22
23--
242.34.1
25
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0038-fixing-the-typo-errors-in-umodsi3-file.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0038-fixing-the-typo-errors-in-umodsi3-file.patch
new file mode 100644
index 00000000..d7b78895
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0038-fixing-the-typo-errors-in-umodsi3-file.patch
@@ -0,0 +1,29 @@
1From 0c0b4fb378d9035f0c5f847321b543a5c2ff70e2 Mon Sep 17 00:00:00 2001
2From: Nagaraju Mekala <nmekala@xilix.com>
3Date: Tue, 16 Oct 2018 07:55:46 +0530
4Subject: [PATCH 38/54] fixing the typo errors in umodsi3 file
5
6---
7 libgcc/config/microblaze/umodsi3.S | 6 +++---
8 1 file changed, 3 insertions(+), 3 deletions(-)
9
10diff --git a/libgcc/config/microblaze/umodsi3.S b/libgcc/config/microblaze/umodsi3.S
11index fffc784b4cb..a706017c634 100644
12--- a/libgcc/config/microblaze/umodsi3.S
13+++ b/libgcc/config/microblaze/umodsi3.S
14@@ -47,9 +47,9 @@ __umodsi3:
15 .frame r1,0,r15
16
17 addik r1,r1,-24
18- swi r29,r1,0
19- swi r30,r1,8
20- swi r31,r1,16
21+ sli r29,r1,0
22+ sli r30,r1,8
23+ sli r31,r1,16
24 #else
25 __umodsi3:
26 .frame r1,0,r15
27--
282.34.1
29
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0039-fixing-the-32bit-LTO-related-issue9-1014024.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0039-fixing-the-32bit-LTO-related-issue9-1014024.patch
new file mode 100644
index 00000000..27b6efd1
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0039-fixing-the-32bit-LTO-related-issue9-1014024.patch
@@ -0,0 +1,68 @@
1From 8dfc5e76a3b0388bb5c88c5c0072256f3062f3c8 Mon Sep 17 00:00:00 2001
2From: Nagaraju Mekala <nmekala@xilix.com>
3Date: Wed, 17 Oct 2018 16:56:14 +0530
4Subject: [PATCH 39/54] fixing the 32bit LTO related issue9(1014024)
5
6---
7 gcc/config/microblaze/microblaze.h | 24 ++++++++++++++----------
8 1 file changed, 14 insertions(+), 10 deletions(-)
9
10diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
11index 4258dcde0d1..4d6babfe9c4 100644
12--- a/gcc/config/microblaze/microblaze.h
13+++ b/gcc/config/microblaze/microblaze.h
14@@ -265,12 +265,14 @@ extern enum pipeline_type microblaze_pipe;
15 #define WORD_REGISTER_OPERATIONS 1
16
17 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
18-/*
19-#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
20- if (GET_MODE_CLASS (MODE) == MODE_INT \
21- && GET_MODE_SIZE (MODE) < (TARGET_MB_64 ? 8 : 4)) \
22- (MODE) = TARGET_MB_64 ? DImode : SImode;
23-*/
24+
25+#ifndef __arch64__
26+#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
27+ if (GET_MODE_CLASS (MODE) == MODE_INT \
28+ && GET_MODE_SIZE (MODE) < 4) \
29+ (MODE) = SImode;
30+#endif
31+
32 /* Standard register usage. */
33
34 /* On the MicroBlaze, we have 32 integer registers */
35@@ -469,16 +471,18 @@ extern struct microblaze_frame_info current_frame_info;
36
37 #define MAX_ARGS_IN_REGISTERS MB_ABI_MAX_ARG_REGS
38
39+#ifdef __aarch64__
40 #define LIBCALL_VALUE(MODE) \
41 gen_rtx_REG (MODE,GP_RETURN)
42-
43-/*#define LIBCALL_VALUE(MODE) \
44+#else
45+#define LIBCALL_VALUE(MODE) \
46 gen_rtx_REG ( \
47 ((GET_MODE_CLASS (MODE) != MODE_INT \
48 || GET_MODE_SIZE (MODE) >= 4) \
49 ? (MODE) \
50 : SImode), GP_RETURN)
51-*/
52+#endif
53+
54 /* 1 if N is a possible register number for a function value.
55 On the MicroBlaze, R2 R3 are the only register thus used.
56 Currently, R2 are only implemented here (C has no complex type) */
57@@ -518,7 +522,7 @@ typedef struct microblaze_args
58 /* 4 insns + 2 words of data. */
59 #define TRAMPOLINE_SIZE (6 * 4)
60
61-#define TRAMPOLINE_ALIGNMENT 64
62+#define TRAMPOLINE_ALIGNMENT (TARGET_MB_64 ? 64 : 32)
63
64 #define REGNO_OK_FOR_BASE_P(regno) microblaze_regno_ok_for_base_p ((regno), 1)
65
66--
672.34.1
68
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0040-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0040-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch
new file mode 100644
index 00000000..35251ff8
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0040-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch
@@ -0,0 +1,25 @@
1From 411324e0340a32b4a84094b38e5d74f38cf391bc Mon Sep 17 00:00:00 2001
2From: Nagaraju Mekala <nmekala@xilix.com>
3Date: Fri, 19 Oct 2018 14:26:25 +0530
4Subject: [PATCH 40/54] Fixed the missing stack adjustment in prologue of
5 modsi3 function
6
7---
8 libgcc/config/microblaze/modsi3.S | 1 +
9 1 file changed, 1 insertion(+)
10
11diff --git a/libgcc/config/microblaze/modsi3.S b/libgcc/config/microblaze/modsi3.S
12index d2f9dc770e4..f8684db721e 100644
13--- a/libgcc/config/microblaze/modsi3.S
14+++ b/libgcc/config/microblaze/modsi3.S
15@@ -119,6 +119,7 @@ $LaRETURN_HERE:
16 lwi r30,r1,8
17 lwi r31,r1,12
18 rtsd r15,8
19+ addik r1,r1,16
20 #endif
21 .end __modsi3
22 .size __modsi3, . - __modsi3
23--
242.34.1
25
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0041-corrected-SPN-for-dlong-instruction-mapping.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0041-corrected-SPN-for-dlong-instruction-mapping.patch
new file mode 100644
index 00000000..bb797a4a
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0041-corrected-SPN-for-dlong-instruction-mapping.patch
@@ -0,0 +1,28 @@
1From b03e3a75a37213823c062bb72e4f6f470c516222 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Wed, 24 Oct 2018 18:31:04 +0530
4Subject: [PATCH 41/54] corrected SPN for dlong instruction mapping.
5
6---
7 gcc/config/microblaze/microblaze.md | 4 ++--
8 1 file changed, 2 insertions(+), 2 deletions(-)
9
10diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
11index 6ada55ac2bc..36b050670b8 100644
12--- a/gcc/config/microblaze/microblaze.md
13+++ b/gcc/config/microblaze/microblaze.md
14@@ -602,9 +602,9 @@
15 (set_attr "mode" "DF")
16 (set_attr "length" "4")])
17
18-(define_insn "floatdfdi2"
19+(define_insn "fix_truncdfdi2"
20 [(set (match_operand:DI 0 "register_operand" "=d")
21- (float:DI (match_operand:DF 1 "register_operand" "d")))]
22+ (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "d"))))]
23 "TARGET_MB_64"
24 "dlong\t%0,%1"
25 [(set_attr "type" "fcvt")
26--
272.34.1
28
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0042-fixing-the-long-long-long-mingw-toolchain-issue.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0042-fixing-the-long-long-long-mingw-toolchain-issue.patch
new file mode 100644
index 00000000..cbafaafc
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0042-fixing-the-long-long-long-mingw-toolchain-issue.patch
@@ -0,0 +1,59 @@
1From b926d05a0cdd32d9821a48f62eef49c5b1025f73 Mon Sep 17 00:00:00 2001
2From: Nagaraju Mekala <nmekala@xilix.com>
3Date: Thu, 29 Nov 2018 17:55:08 +0530
4Subject: [PATCH 42/54] fixing the long & long long mingw toolchain issue
5
6---
7 gcc/config/microblaze/constraints.md | 2 +-
8 gcc/config/microblaze/microblaze.md | 8 ++++----
9 2 files changed, 5 insertions(+), 5 deletions(-)
10
11diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md
12index 7bb1e0b4c8d..fa605831bfe 100644
13--- a/gcc/config/microblaze/constraints.md
14+++ b/gcc/config/microblaze/constraints.md
15@@ -55,7 +55,7 @@
16 (define_constraint "K"
17 "A constant in the range 0xffffff8000000000L to 0x0000007fffffffffL (inclusive)."
18 (and (match_code "const_int")
19- (match_test "ival > (long)-549755813888 && ival < (long)549755813887")))
20+ (match_test "ival > (long long)-549755813888 && ival < (long long)549755813887")))
21
22
23 ;; Define floating point constraints
24diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
25index 36b050670b8..e123bf3a7d1 100644
26--- a/gcc/config/microblaze/microblaze.md
27+++ b/gcc/config/microblaze/microblaze.md
28@@ -648,8 +648,8 @@
29 if (TARGET_MB_64)
30 {
31 if (GET_CODE (operands[2]) == CONST_INT &&
32- INTVAL(operands[2]) < (long)-549755813888 &&
33- INTVAL(operands[2]) > (long)549755813887)
34+ INTVAL(operands[2]) < (long long)-549755813888 &&
35+ INTVAL(operands[2]) > (long long)549755813887)
36 FAIL;
37 }
38 })
39@@ -1264,7 +1264,7 @@
40 (match_operand:DI 1 "immediate_operand" "J,I,Mnis"))]
41 "TARGET_MB_64 && (register_operand (operands[0], DImode) &&
42 (GET_CODE (operands[1]) == CONST_INT &&
43- (INTVAL (operands[1]) <= (long)549755813887 && INTVAL (operands[1]) >= (long)-549755813888)))"
44+ (INTVAL (operands[1]) <= (long long)549755813887 && INTVAL (operands[1]) >= (long long)-549755813888)))"
45 "@
46 addlk\t%0,r0,r0\t
47 addlik\t%0,r0,%1\t #N1 %X1
48@@ -1298,7 +1298,7 @@
49 case 1:
50 case 2:
51 if (GET_CODE (operands[1]) == CONST_INT &&
52- (INTVAL (operands[1]) > (long)549755813887 || INTVAL (operands[1]) < (long)-549755813888))
53+ (INTVAL (operands[1]) > (long long)549755813887 || INTVAL (operands[1]) < (long long)-549755813888))
54 return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
55 else
56 return "addlik\t%0,r0,%1";
57--
582.34.1
59
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0043-Fix-the-MB-64-bug-of-handling-QI-objects.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0043-Fix-the-MB-64-bug-of-handling-QI-objects.patch
new file mode 100644
index 00000000..af8c684f
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0043-Fix-the-MB-64-bug-of-handling-QI-objects.patch
@@ -0,0 +1,47 @@
1From 854371934116e5197d627cebaf274f431205b914 Mon Sep 17 00:00:00 2001
2From: Nagaraju <nmekala@xilinx.com>
3Date: Thu, 14 Mar 2019 18:11:04 +0530
4Subject: [PATCH 43/54] Fix the MB-64 bug of handling QI objects
5
6---
7 gcc/config/microblaze/microblaze.md | 14 +++++++-------
8 1 file changed, 7 insertions(+), 7 deletions(-)
9
10diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
11index e123bf3a7d1..0f81b0ed58c 100644
12--- a/gcc/config/microblaze/microblaze.md
13+++ b/gcc/config/microblaze/microblaze.md
14@@ -2345,11 +2345,11 @@ else
15
16 (define_insn "branch_zero_64"
17 [(set (pc)
18- (if_then_else (match_operator:SI 0 "ordered_comparison_operator"
19+ (if_then_else (match_operator 0 "ordered_comparison_operator"
20 [(match_operand:SI 1 "register_operand" "d")
21 (const_int 0)])
22- (match_operand:SI 2 "pc_or_label_operand" "")
23- (match_operand:SI 3 "pc_or_label_operand" "")))
24+ (match_operand 2 "pc_or_label_operand" "")
25+ (match_operand 3 "pc_or_label_operand" "")))
26 ]
27 "TARGET_MB_64"
28 {
29@@ -2365,11 +2365,11 @@ else
30
31 (define_insn "long_branch_zero"
32 [(set (pc)
33- (if_then_else (match_operator 0 "ordered_comparison_operator"
34- [(match_operand 1 "register_operand" "d")
35+ (if_then_else (match_operator:DI 0 "ordered_comparison_operator"
36+ [(match_operand:DI 1 "register_operand" "d")
37 (const_int 0)])
38- (match_operand 2 "pc_or_label_operand" "")
39- (match_operand 3 "pc_or_label_operand" "")))
40+ (match_operand:DI 2 "pc_or_label_operand" "")
41+ (match_operand:DI 3 "pc_or_label_operand" "")))
42 ]
43 "TARGET_MB_64"
44 {
45--
462.34.1
47
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0044-We-will-check-the-possibility-of-peephole2-optimizat.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0044-We-will-check-the-possibility-of-peephole2-optimizat.patch
new file mode 100644
index 00000000..277e5be2
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0044-We-will-check-the-possibility-of-peephole2-optimizat.patch
@@ -0,0 +1,87 @@
1From 5527cec8136440a1edea87b2bb6dafa8e78d07b0 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Fri, 29 Mar 2019 12:08:39 +0530
4Subject: [PATCH 44/54] We will check the possibility of peephole2
5 optimization,if we can then we will fix the compiler issue.
6
7---
8 gcc/config/microblaze/microblaze.md | 63 +++++++++++++++++------------
9 1 file changed, 38 insertions(+), 25 deletions(-)
10
11diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
12index 0f81b0ed58c..f661ba1c241 100644
13--- a/gcc/config/microblaze/microblaze.md
14+++ b/gcc/config/microblaze/microblaze.md
15@@ -882,31 +882,44 @@
16 (set_attr "mode" "SI")
17 (set_attr "length" "4")])
18
19-(define_peephole2
20- [(set (match_operand:SI 0 "register_operand")
21- (fix:SI (match_operand:SF 1 "register_operand")))
22- (set (pc)
23- (if_then_else (match_operator 2 "ordered_comparison_operator"
24- [(match_operand:SI 3 "register_operand")
25- (match_operand:SI 4 "arith_operand")])
26- (label_ref (match_operand 5))
27- (pc)))]
28- "TARGET_HARD_FLOAT && !TARGET_MB_64"
29- [(set (match_dup 1) (match_dup 3))]
30-
31- {
32- rtx condition;
33- rtx cmp_op0 = operands[3];
34- rtx cmp_op1 = operands[4];
35- rtx comp_reg = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
36-
37- emit_insn (gen_cstoresf4 (comp_reg, operands[2],
38- gen_rtx_REG (SFmode, REGNO (cmp_op0)),
39- gen_rtx_REG (SFmode, REGNO (cmp_op1))));
40- condition = gen_rtx_NE (SImode, comp_reg, const0_rtx);
41- emit_jump_insn (gen_condjump (condition, operands[5]));
42- }
43-)
44+;; peephole2 optimization will be done only if fint and if-then-else
45+;; are dependent.added condition for the same.
46+;; if they are dependent then gcc is giving "flow control insn inside a basic block"
47+;; testcase:
48+;; volatile float vec = 1.0;
49+;; volatile int ci = 2;
50+;; register int cj = (int)(vec);
51+;;// ci=cj;
52+;;// if (ci <0) {
53+;; if (cj < 0) {
54+;; ci = 0;
55+;; }
56+;; commenting for now.we will check the possibility of this optimization later
57+
58+;;(define_peephole2
59+;; [(set (match_operand:SI 0 "register_operand")
60+;; (fix:SI (match_operand:SF 1 "register_operand")))
61+;; (set (pc)
62+;; (if_then_else (match_operator 2 "ordered_comparison_operator"
63+;; [(match_operand:SI 3 "register_operand")
64+;; (match_operand:SI 4 "arith_operand")])
65+;; (label_ref (match_operand 5))
66+;; (pc)))]
67+;; "TARGET_HARD_FLOAT && !TARGET_MB_64 && ((REGNO (operands[0])) == (REGNO (operands[3])))"
68+;; [(set (match_dup 1) (match_dup 3))]
69+;; {
70+;; rtx condition;
71+;; rtx cmp_op0 = operands[3];
72+;; rtx cmp_op1 = operands[4];
73+;; rtx comp_reg = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
74+;;
75+;; emit_insn (gen_cstoresf4 (comp_reg, operands[2],
76+;; gen_rtx_REG (SFmode, REGNO (cmp_op0)),
77+;; gen_rtx_REG (SFmode, REGNO (cmp_op1))));
78+;; condition = gen_rtx_NE (SImode, comp_reg, const0_rtx);
79+;; emit_jump_insn (gen_condjump (condition, operands[5]));
80+;; }
81+;;)
82
83 ;;----------------------------------------------------------------
84 ;; Negation and one's complement
85--
862.34.1
87
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0045-fixed-typos-in-mul-div-and-mod-assembly-files.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0045-fixed-typos-in-mul-div-and-mod-assembly-files.patch
new file mode 100644
index 00000000..4760926f
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0045-fixed-typos-in-mul-div-and-mod-assembly-files.patch
@@ -0,0 +1,465 @@
1From 3c6f051ce41f06eab29932859be52ed864bef52f Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Wed, 17 Apr 2019 12:36:16 +0530
4Subject: [PATCH 45/54] fixed typos in mul,div and mod assembly files.
5
6---
7 libgcc/config/microblaze/divsi3.S | 47 ++++++++++++++++++++----
8 libgcc/config/microblaze/modsi3.S | 40 ++++++++++++++++++---
9 libgcc/config/microblaze/mulsi3.S | 33 ++++++++++++++++-
10 libgcc/config/microblaze/udivsi3.S | 54 +++++++++++++++++++++++++---
11 libgcc/config/microblaze/umodsi3.S | 58 +++++++++++++++++++++++++++---
12 5 files changed, 212 insertions(+), 20 deletions(-)
13
14diff --git a/libgcc/config/microblaze/divsi3.S b/libgcc/config/microblaze/divsi3.S
15index 9f04f59104e..e1dfccbf257 100644
16--- a/libgcc/config/microblaze/divsi3.S
17+++ b/libgcc/config/microblaze/divsi3.S
18@@ -46,7 +46,7 @@
19 __divsi3:
20 .frame r1,0,r15
21
22- ADDIK r1,r1,-32
23+ ADDLIK r1,r1,-32
24 SLI r28,r1,0
25 SLI r29,r1,8
26 SLI r30,r1,16
27@@ -61,13 +61,23 @@ __divsi3:
28 SWI r30,r1,8
29 SWI r31,r1,12
30 #endif
31- BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error
32- BEQI r5,$LaResult_Is_Zero # Result is Zero
33- BGEID r5,$LaR5_Pos
34+#ifdef __arch64__
35+ BEAEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error
36+ BEAEQI r5,$LaResult_Is_Zero # Result is Zero
37+ BEAGEID r5,$LaR5_Pos
38+#else
39+ BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error
40+ BEQI r5,$LaResult_Is_Zero # Result is Zero
41+ BGEID r5,$LaR5_Pos
42+#endif
43 XOR r28,r5,r6 # Get the sign of the result
44 RSUBI r5,r5,0 # Make r5 positive
45 $LaR5_Pos:
46- BGEI r6,$LaR6_Pos
47+#ifdef __arch64__
48+ BEAGEI r6,$LaR6_Pos
49+#else
50+ BGEI r6,$LaR6_Pos
51+#endif
52 RSUBI r6,r6,0 # Make r6 positive
53 $LaR6_Pos:
54 ADDIK r30,r0,0 # Clear mod
55@@ -76,26 +86,51 @@ $LaR6_Pos:
56
57 # First part try to find the first '1' in the r5
58 $LaDIV0:
59- BLTI r5,$LaDIV2 # This traps r5 == 0x80000000
60+#ifdef __arch64__
61+ BEALTI r5,$LaDIV2 # This traps r5 == 0x80000000
62+#else
63+ BLTI r5,$LaDIV2 # This traps r5 == 0x80000000
64+#endif
65 $LaDIV1:
66 ADD r5,r5,r5 # left shift logical r5
67+#ifdef __arch64__
68+ BEAGTID r5,$LaDIV1
69+#else
70 BGTID r5,$LaDIV1
71+#endif
72 ADDIK r29,r29,-1
73 $LaDIV2:
74 ADD r5,r5,r5 # left shift logical r5 get the '1' into the Carry
75 ADDC r30,r30,r30 # Move that bit into the Mod register
76 RSUB r31,r6,r30 # Try to subtract (r30 a r6)
77+#ifdef __arch64__
78+ BEALTI r31,$LaMOD_TOO_SMALL
79+#else
80 BLTI r31,$LaMOD_TOO_SMALL
81+#endif
82 OR r30,r0,r31 # Move the r31 to mod since the result was positive
83 ADDIK r3,r3,1
84 $LaMOD_TOO_SMALL:
85 ADDIK r29,r29,-1
86+#ifdef __arch64__
87+ BEAEQi r29,$LaLOOP_END
88+#else
89 BEQi r29,$LaLOOP_END
90+#endif
91 ADD r3,r3,r3 # Shift in the '1' into div
92+#ifdef __arch64__
93+ BREAI $LaDIV2 # Div2
94+#else
95 BRI $LaDIV2 # Div2
96+#endif
97 $LaLOOP_END:
98+#ifdef __arch64__
99+ BEAGEI r28,$LaRETURN_HERE
100+ BREAID $LaRETURN_HERE
101+#else
102 BGEI r28,$LaRETURN_HERE
103 BRID $LaRETURN_HERE
104+#endif
105 RSUBI r3,r3,0 # Negate the result
106 $LaDiv_By_Zero:
107 $LaResult_Is_Zero:
108diff --git a/libgcc/config/microblaze/modsi3.S b/libgcc/config/microblaze/modsi3.S
109index f8684db721e..3bf9b10ec3e 100644
110--- a/libgcc/config/microblaze/modsi3.S
111+++ b/libgcc/config/microblaze/modsi3.S
112@@ -62,40 +62,72 @@ __modsi3:
113 swi r31,r1,12
114 #endif
115
116+#ifdef __arch64__
117+ BEAEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error
118+ BEAEQI r5,$LaResult_Is_Zero # Result is Zero
119+ BEAGEId r5,$LaR5_Pos
120+#else
121 BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error
122 BEQI r5,$LaResult_Is_Zero # Result is Zero
123 BGEId r5,$LaR5_Pos
124+#endif
125 ADD r28,r5,r0 # Get the sign of the result [ Depends only on the first arg]
126 RSUBI r5,r5,0 # Make r5 positive
127 $LaR5_Pos:
128- BGEI r6,$LaR6_Pos
129+#ifdef __arch64__
130+ BEAGEI r6,$LaR6_Pos
131+#else
132+ BGEI r6,$LaR6_Pos
133+#endif
134 RSUBI r6,r6,0 # Make r6 positive
135 $LaR6_Pos:
136 ADDIK r3,r0,0 # Clear mod
137 ADDIK r30,r0,0 # clear div
138- BLTId r5,$LaDIV2 # If r5 is still negative (0x80000000), skip
139+#ifdef __arch64__
140+ BEALTId r5,$LaDIV2 # If r5 is still negative (0x80000000), skip
141 # the first bit search.
142+#else
143+ BLTId r5,$LaDIV2 # If r5 is still negative (0x80000000), skip
144+ # the first bit search.
145+#endif
146 ADDIK r29,r0,32 # Initialize the loop count
147 # First part try to find the first '1' in the r5
148 $LaDIV1:
149 ADD r5,r5,r5 # left shift logical r5
150- BGEID r5,$LaDIV1 #
151+#ifdef __arch64__
152+ BEAGEID r5,$LaDIV1 #
153+#else
154+ BGEID r5,$LaDIV1 #
155+#endif
156 ADDIK r29,r29,-1
157 $LaDIV2:
158 ADD r5,r5,r5 # left shift logical r5 get the '1' into the Carry
159 ADDC r3,r3,r3 # Move that bit into the Mod register
160 rSUB r31,r6,r3 # Try to subtract (r30 a r6)
161+#ifdef __arch64__
162+ BEALTi r31,$LaMOD_TOO_SMALL
163+#else
164 BLTi r31,$LaMOD_TOO_SMALL
165+#endif
166 OR r3,r0,r31 # Move the r31 to mod since the result was positive
167 ADDIK r30,r30,1
168 $LaMOD_TOO_SMALL:
169 ADDIK r29,r29,-1
170+#ifdef __arch64__
171+ BEAEQi r29,$LaLOOP_END
172+ ADD r30,r30,r30 # Shift in the '1' into div
173+ BREAI $LaDIV2 # Div2
174+$LaLOOP_END:
175+ BEAGEI r28,$LaRETURN_HERE
176+ BREAId $LaRETURN_HERE
177+#else
178 BEQi r29,$LaLOOP_END
179 ADD r30,r30,r30 # Shift in the '1' into div
180 BRI $LaDIV2 # Div2
181 $LaLOOP_END:
182 BGEI r28,$LaRETURN_HERE
183 BRId $LaRETURN_HERE
184+#endif
185 rsubi r3,r3,0 # Negate the result
186 $LaDiv_By_Zero:
187 $LaResult_Is_Zero:
188@@ -108,7 +140,7 @@ $LaRETURN_HERE:
189 lli r29,r1,8
190 lli r30,r1,16
191 lli r31,r1,24
192- addik r1,r1,32
193+ addlik r1,r1,32
194 rtsd r15,8
195 nop
196 #else
197diff --git a/libgcc/config/microblaze/mulsi3.S b/libgcc/config/microblaze/mulsi3.S
198index 437e2bc309e..bc9ff9cdc89 100644
199--- a/libgcc/config/microblaze/mulsi3.S
200+++ b/libgcc/config/microblaze/mulsi3.S
201@@ -43,7 +43,37 @@
202 .type __mulsi3,@function
203 #ifdef __arch64__
204 .align 3
205-#endif
206+__mulsi3:
207+ .frame r1,0,r15
208+ add r3,r0,r0
209+ BEAEQI r5,$L_Result_Is_Zero # Multiply by Zero
210+ BEAEQI r6,$L_Result_Is_Zero # Multiply by Zero
211+ BEAGEId r5,$L_R5_Pos
212+ XOR r4,r5,r6 # Get the sign of the result
213+ RSUBI r5,r5,0 # Make r5 positive
214+$L_R5_Pos:
215+ BEAGEI r6,$L_R6_Pos
216+ RSUBI r6,r6,0 # Make r6 positive
217+$L_R6_Pos:
218+ breai $L1
219+$L2:
220+ add r5,r5,r5
221+$L1:
222+ srl r6,r6
223+ addc r7,r0,r0
224+ beaeqi r7,$L2
225+ beaneid r6,$L2
226+ add r3,r3,r5
227+ bealti r4,$L_NegateResult
228+ rtsd r15,8
229+ nop
230+$L_NegateResult:
231+ rtsd r15,8
232+ rsub r3,r3,r0
233+$L_Result_Is_Zero:
234+ rtsd r15,8
235+ addi r3,r0,0
236+#else
237 __mulsi3:
238 .frame r1,0,r15
239 add r3,r0,r0
240@@ -74,5 +104,6 @@ $L_NegateResult:
241 $L_Result_Is_Zero:
242 rtsd r15,8
243 addi r3,r0,0
244+#endif
245 .end __mulsi3
246 .size __mulsi3, . - __mulsi3
247diff --git a/libgcc/config/microblaze/udivsi3.S b/libgcc/config/microblaze/udivsi3.S
248index 496dd6794bf..486bc8f0819 100644
249--- a/libgcc/config/microblaze/udivsi3.S
250+++ b/libgcc/config/microblaze/udivsi3.S
251@@ -59,52 +59,96 @@ __udivsi3:
252 SWI r30,r1,4
253 SWI r31,r1,8
254 #endif
255+#ifdef __arch64__
256+ BEAEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error
257+ BEAEQID r5,$LaResult_Is_Zero # Result is Zero
258+#else
259 BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error
260 BEQID r5,$LaResult_Is_Zero # Result is Zero
261+#endif
262 ADDIK r30,r0,0 # Clear mod
263 ADDIK r29,r0,32 # Initialize the loop count
264
265 # Check if r6 and r5 are equal # if yes, return 1
266 RSUB r18,r5,r6
267+#ifdef __arch64__
268+ BEAEQID r18,$LaRETURN_HERE
269+#else
270 BEQID r18,$LaRETURN_HERE
271+#endif
272 ADDIK r3,r0,1
273
274 # Check if (uns)r6 is greater than (uns)r5. In that case, just return 0
275 XOR r18,r5,r6
276- BGEID r18,16
277+#ifdef __arch64__
278+ BEAGEID r18,16
279+#else
280+ BGEID r18,16
281+#endif
282 ADD r3,r0,r0 # We would anyways clear r3
283+#ifdef __arch64__
284+ BEALTI r6,$LaRETURN_HERE # r6[bit 31 = 1] hence is greater
285+ BREAI $LCheckr6
286+ RSUB r18,r6,r5 # MICROBLAZEcmp
287+ BEALTI r18,$LaRETURN_HERE
288+#else
289 BLTI r6,$LaRETURN_HERE # r6[bit 31 = 1] hence is greater
290 BRI $LCheckr6
291 RSUB r18,r6,r5 # MICROBLAZEcmp
292 BLTI r18,$LaRETURN_HERE
293-
294+#endif
295 # If r6 [bit 31] is set, then return result as 1
296 $LCheckr6:
297- BGTI r6,$LaDIV0
298- BRID $LaRETURN_HERE
299+#ifdef __arch64__
300+ BEAGTI r6,$LaDIV0
301+ BREAID $LaRETURN_HERE
302+#else
303+ BGTI r6,$LaDIV0
304+ BRID $LaRETURN_HERE
305+#endif
306 ADDIK r3,r0,1
307
308 # First part try to find the first '1' in the r5
309 $LaDIV0:
310+#ifdef __arch64__
311+ BEALTI r5,$LaDIV2
312+#else
313 BLTI r5,$LaDIV2
314+#endif
315 $LaDIV1:
316 ADD r5,r5,r5 # left shift logical r5
317+#ifdef __arch64__
318+ BEAGTID r5,$LaDIV1
319+#else
320 BGTID r5,$LaDIV1
321+#endif
322 ADDIK r29,r29,-1
323 $LaDIV2:
324 ADD r5,r5,r5 # left shift logical r5 get the '1' into the Carry
325 ADDC r30,r30,r30 # Move that bit into the Mod register
326 RSUB r31,r6,r30 # Try to subtract (r30 a r6)
327+#ifdef __arch64__
328+ BEALTI r31,$LaMOD_TOO_SMALL
329+#else
330 BLTI r31,$LaMOD_TOO_SMALL
331+#endif
332 OR r30,r0,r31 # Move the r31 to mod since the result was positive
333 ADDIK r3,r3,1
334 $LaMOD_TOO_SMALL:
335 ADDIK r29,r29,-1
336+#ifdef __arch64__
337+ BEAEQi r29,$LaLOOP_END
338+ ADD r3,r3,r3 # Shift in the '1' into div
339+ BREAI $LaDIV2 # Div2
340+$LaLOOP_END:
341+ BREAI $LaRETURN_HERE
342+#else
343 BEQi r29,$LaLOOP_END
344 ADD r3,r3,r3 # Shift in the '1' into div
345 BRI $LaDIV2 # Div2
346 $LaLOOP_END:
347 BRI $LaRETURN_HERE
348+#endif
349 $LaDiv_By_Zero:
350 $LaResult_Is_Zero:
351 OR r3,r0,r0 # set result to 0
352@@ -115,7 +159,7 @@ $LaRETURN_HERE:
353 LLI r29,r1,0
354 LLI r30,r1,8
355 LLI r31,r1,16
356- ADDIK r1,r1,24
357+ ADDLIK r1,r1,24
358 RTSD r15,8
359 NOP
360 #else
361diff --git a/libgcc/config/microblaze/umodsi3.S b/libgcc/config/microblaze/umodsi3.S
362index a706017c634..1d8e2921745 100644
363--- a/libgcc/config/microblaze/umodsi3.S
364+++ b/libgcc/config/microblaze/umodsi3.S
365@@ -46,7 +46,7 @@
366 __umodsi3:
367 .frame r1,0,r15
368
369- addik r1,r1,-24
370+ addlik r1,r1,-24
371 sli r29,r1,0
372 sli r30,r1,8
373 sli r31,r1,16
374@@ -59,27 +59,77 @@ __umodsi3:
375 swi r30,r1,4
376 swi r31,r1,8
377 #endif
378+#ifdef __arch64__
379+ BEAEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error
380+ BEAEQId r5,$LaResult_Is_Zero # Result is Zero
381+#else
382 BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error
383 BEQId r5,$LaResult_Is_Zero # Result is Zero
384+#endif
385 ADDIK r3,r0,0 # Clear div
386 ADDIK r30,r0,0 # clear mod
387 ADDIK r29,r0,32 # Initialize the loop count
388
389 # Check if r6 and r5 are equal # if yes, return 0
390 rsub r18,r5,r6
391- beqi r18,$LaRETURN_HERE
392
393+#ifdef __arch64__
394+ beaeqi r18,$LaRETURN_HERE
395+#else
396+ beqi r18,$LaRETURN_HERE
397+#endif
398 # Check if (uns)r6 is greater than (uns)r5. In that case, just return r5
399 xor r18,r5,r6
400+#ifdef __arch64__
401+ beageid r18,16
402+ addik r3,r5,0
403+ bealti r6,$LaRETURN_HERE
404+ breai $LCheckr6
405+ rsub r18,r5,r6 # MICROBLAZEcmp
406+ beagti r18,$LaRETURN_HERE
407+#else
408 bgeid r18,16
409 addik r3,r5,0
410 blti r6,$LaRETURN_HERE
411 bri $LCheckr6
412 rsub r18,r5,r6 # MICROBLAZEcmp
413 bgti r18,$LaRETURN_HERE
414-
415+#endif
416 # If r6 [bit 31] is set, then return result as r5-r6
417 $LCheckr6:
418+#ifdef __arch64__
419+ beagtid r6,$LaDIV0
420+ addik r3,r0,0
421+ addik r18,r0,0x7fffffff
422+ and r5,r5,r18
423+ and r6,r6,r18
424+ breaid $LaRETURN_HERE
425+ rsub r3,r6,r5
426+# First part: try to find the first '1' in the r5
427+$LaDIV0:
428+ BEALTI r5,$LaDIV2
429+$LaDIV1:
430+ ADD r5,r5,r5 # left shift logical r5
431+ BEAGEID r5,$LaDIV1 #
432+ ADDIK r29,r29,-1
433+$LaDIV2:
434+ ADD r5,r5,r5 # left shift logical r5 get the '1' into the Carry
435+ ADDC r3,r3,r3 # Move that bit into the Mod register
436+ rSUB r31,r6,r3 # Try to subtract (r3 a r6)
437+ BEALTi r31,$LaMOD_TOO_SMALL
438+ OR r3,r0,r31 # Move the r31 to mod since the result was positive
439+ ADDIK r30,r30,1
440+$LaMOD_TOO_SMALL:
441+ ADDIK r29,r29,-1
442+ BEAEQi r29,$LaLOOP_END
443+ ADD r30,r30,r30 # Shift in the '1' into div
444+ BREAI $LaDIV2 # Div2
445+$LaLOOP_END:
446+ BREAI $LaRETURN_HERE
447+$LaDiv_By_Zero:
448+$LaResult_Is_Zero:
449+ or r3,r0,r0 # set result to 0
450+#else
451 bgtid r6,$LaDIV0
452 addik r3,r0,0
453 addik r18,r0,0x7fffffff
454@@ -111,7 +161,7 @@ $LaLOOP_END:
455 $LaDiv_By_Zero:
456 $LaResult_Is_Zero:
457 or r3,r0,r0 # set result to 0
458-
459+#endif
460 #ifdef __arch64__
461 $LaRETURN_HERE:
462 # Restore values of CSRs and that of r3 and the divisor and the dividend
463--
4642.34.1
465
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0046-MB-64-removal-of-barrel-shift-instructions-from-defa.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0046-MB-64-removal-of-barrel-shift-instructions-from-defa.patch
new file mode 100644
index 00000000..5f45d03f
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0046-MB-64-removal-of-barrel-shift-instructions-from-defa.patch
@@ -0,0 +1,476 @@
1From 0776495e85a15c1ad84fd90736059902bb3ea152 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Tue, 13 Sep 2022 15:59:12 +0530
4Subject: [PATCH 46/54] MB-64 removal of barrel-shift instructions from default
5 By default MB-64 is generatting barrel-shift instructions. It has been
6 removed from default. Barrel-shift instructions will be generated only if
7 barrel-shifter is enabled. Similarly to double instructions as well.
8
9 Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
10---
11 gcc/config/microblaze/microblaze.cc | 2 +-
12 gcc/config/microblaze/microblaze.md | 269 ++++++++++++++++++++++++++--
13 2 files changed, 252 insertions(+), 19 deletions(-)
14
15diff --git a/gcc/config/microblaze/microblaze.cc b/gcc/config/microblaze/microblaze.cc
16index 965a041ea8c..f949a8863d3 100644
17--- a/gcc/config/microblaze/microblaze.cc
18+++ b/gcc/config/microblaze/microblaze.cc
19@@ -3880,7 +3880,7 @@ microblaze_expand_divide (rtx operands[])
20 emit_insn (gen_rtx_CLOBBER (Pmode, reg18));
21
22 if (TARGET_MB_64) {
23- emit_insn (gen_ashldi3_long (regt1, operands[1], GEN_INT(4)));
24+ emit_insn (gen_ashldi3 (regt1, operands[1], GEN_INT(4)));
25 emit_insn (gen_adddi3 (regt1, regt1, operands[2]));
26 }
27 else {
28diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
29index f661ba1c241..9bc9512db8e 100644
30--- a/gcc/config/microblaze/microblaze.md
31+++ b/gcc/config/microblaze/microblaze.md
32@@ -547,7 +547,7 @@
33 [(set (match_operand:DF 0 "register_operand" "=d")
34 (plus:DF (match_operand:DF 1 "register_operand" "d")
35 (match_operand:DF 2 "register_operand" "d")))]
36- "TARGET_MB_64"
37+ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
38 "dadd\t%0,%1,%2"
39 [(set_attr "type" "fadd")
40 (set_attr "mode" "DF")
41@@ -557,7 +557,7 @@
42 [(set (match_operand:DF 0 "register_operand" "=d")
43 (minus:DF (match_operand:DF 1 "register_operand" "d")
44 (match_operand:DF 2 "register_operand" "d")))]
45- "TARGET_MB_64"
46+ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
47 "drsub\t%0,%2,%1"
48 [(set_attr "type" "frsub")
49 (set_attr "mode" "DF")
50@@ -567,7 +567,7 @@
51 [(set (match_operand:DF 0 "register_operand" "=d")
52 (mult:DF (match_operand:DF 1 "register_operand" "d")
53 (match_operand:DF 2 "register_operand" "d")))]
54- "TARGET_MB_64"
55+ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
56 "dmul\t%0,%1,%2"
57 [(set_attr "type" "fmul")
58 (set_attr "mode" "DF")
59@@ -577,7 +577,7 @@
60 [(set (match_operand:DF 0 "register_operand" "=d")
61 (div:DF (match_operand:DF 1 "register_operand" "d")
62 (match_operand:DF 2 "register_operand" "d")))]
63- "TARGET_MB_64"
64+ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
65 "ddiv\t%0,%2,%1"
66 [(set_attr "type" "fdiv")
67 (set_attr "mode" "DF")
68@@ -587,7 +587,7 @@
69 (define_insn "sqrtdf2"
70 [(set (match_operand:DF 0 "register_operand" "=d")
71 (sqrt:DF (match_operand:DF 1 "register_operand" "d")))]
72- "TARGET_MB_64"
73+ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
74 "dsqrt\t%0,%1"
75 [(set_attr "type" "fsqrt")
76 (set_attr "mode" "DF")
77@@ -596,7 +596,7 @@
78 (define_insn "floatdidf2"
79 [(set (match_operand:DF 0 "register_operand" "=d")
80 (float:DF (match_operand:DI 1 "register_operand" "d")))]
81- "TARGET_MB_64"
82+ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
83 "dbl\t%0,%1"
84 [(set_attr "type" "fcvt")
85 (set_attr "mode" "DF")
86@@ -605,7 +605,7 @@
87 (define_insn "fix_truncdfdi2"
88 [(set (match_operand:DI 0 "register_operand" "=d")
89 (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "d"))))]
90- "TARGET_MB_64"
91+ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
92 "dlong\t%0,%1"
93 [(set_attr "type" "fcvt")
94 (set_attr "mode" "DI")
95@@ -1299,6 +1299,34 @@
96 (set_attr "mode" "DI")
97 (set_attr "length" "4")])
98
99+(define_insn "*movdi_internal2_bshift"
100+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d, d,d,R,m")
101+ (match_operand:DI 1 "move_src_operand" " d,I,Mnis,R,m,dJ,dJ"))]
102+ "TARGET_MB_64 && TARGET_BARREL_SHIFT"
103+ {
104+ switch (which_alternative)
105+ {
106+ case 0:
107+ return "addlk\t%0,%1,r0";
108+ case 1:
109+ case 2:
110+ if (GET_CODE (operands[1]) == CONST_INT &&
111+ (INTVAL (operands[1]) > (long long)549755813887 || INTVAL (operands[1]) < (long long)-549755813888))
112+ return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
113+ else
114+ return "addlik\t%0,r0,%1";
115+ case 3:
116+ case 4:
117+ return "ll%i1\t%0,%1";
118+ case 5:
119+ case 6:
120+ return "sl%i0\t%z1,%0";
121+ }
122+ }
123+ [(set_attr "type" "load,no_delay_load,no_delay_load,no_delay_load,no_delay_load,no_delay_store,no_delay_store")
124+ (set_attr "mode" "DI")
125+ (set_attr "length" "4,4,12,4,8,4,8")])
126+
127 (define_insn "*movdi_internal2"
128 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d, d,d,R,m")
129 (match_operand:DI 1 "move_src_operand" " d,I,Mnis,R,m,dJ,dJ"))]
130@@ -1312,7 +1340,15 @@
131 case 2:
132 if (GET_CODE (operands[1]) == CONST_INT &&
133 (INTVAL (operands[1]) > (long long)549755813887 || INTVAL (operands[1]) < (long long)-549755813888))
134- return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
135+ {
136+ operands[2] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
137+ output_asm_insn ("addlik\t%0,r0,%h1", operands);
138+ output_asm_insn ("addlik\t%2,r0,32", operands);
139+ output_asm_insn ("addlik\t%2,%2,-1", operands);
140+ output_asm_insn ("beaneid\t%2,.-8", operands);
141+ output_asm_insn ("addlk\t%0,%0,%0", operands);
142+ return "addlik\t%0,%0,%j1 #li => la";
143+ }
144 else
145 return "addlik\t%0,r0,%1";
146 case 3:
147@@ -1387,7 +1423,7 @@
148 (define_insn "movdi_long_int"
149 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
150 (match_operand:DI 1 "general_operand" "i"))]
151- "TARGET_MB_64"
152+ "TARGET_MB_64 && TARGET_BARREL_SHIFT"
153 "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
154 [(set_attr "type" "no_delay_arith")
155 (set_attr "mode" "DI")
156@@ -1654,6 +1690,33 @@
157 ;; movdf_internal
158 ;; Applies to both TARGET_SOFT_FLOAT and TARGET_HARD_FLOAT
159 ;;
160+(define_insn "*movdf_internal_64_bshift"
161+ [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,d,m")
162+ (match_operand:DF 1 "general_operand" "d,dG,m,F,T,d"))]
163+ "TARGET_MB_64 && TARGET_BARREL_SHIFT"
164+ {
165+ switch (which_alternative)
166+ {
167+ case 0:
168+ return "addlk\t%0,%1,r0";
169+ case 1:
170+ return "addlk\t%0,r0,r0";
171+ case 2:
172+ case 4:
173+ return "ll%i1\t%0,%1";
174+ case 3:
175+ {
176+ return "addlik\t%0,r0,%j1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%h1 #Xfer Lo";
177+ }
178+ case 5:
179+ return "sl%i0\t%1,%0";
180+ }
181+ gcc_unreachable ();
182+ }
183+ [(set_attr "type" "no_delay_move,no_delay_move,no_delay_load,no_delay_load,no_delay_load,no_delay_store")
184+ (set_attr "mode" "DF")
185+ (set_attr "length" "4,4,4,16,4,4")])
186+
187 (define_insn "*movdf_internal_64"
188 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,d,m")
189 (match_operand:DF 1 "general_operand" "d,dG,m,F,T,d"))]
190@@ -1670,7 +1733,13 @@
191 return "ll%i1\t%0,%1";
192 case 3:
193 {
194- return "addlik\t%0,r0,%j1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%h1 #Xfer Lo";
195+ operands[2] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
196+ output_asm_insn ("addlik\t%0,r0,%h1", operands);
197+ output_asm_insn ("addlik\t%2,r0,32", operands);
198+ output_asm_insn ("addlik\t%2,%2,-1", operands);
199+ output_asm_insn ("beaneid\t%2,.-8", operands);
200+ output_asm_insn ("addlk\t%0,%0,%0", operands);
201+ return "addlik\t%0,%0,%j1 #li => la";
202 }
203 case 5:
204 return "sl%i0\t%1,%0";
205@@ -1790,11 +1859,21 @@
206 "TARGET_MB_64"
207 {
208 ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
209-if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
210+if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && TARGET_BARREL_SHIFT)
211 {
212 emit_insn(gen_ashldi3_long (operands[0], operands[1],operands[2]));
213 DONE;
214 }
215+else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && CONST_INT_P (operands[2]))
216+ {
217+ emit_insn(gen_ashldi3_const (operands[0], operands[1],operands[2]));
218+ DONE;
219+ }
220+else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && GET_CODE (operands[2]) == REG)
221+ {
222+ emit_insn(gen_ashldi3_reg (operands[0], operands[1],operands[2]));
223+ DONE;
224+ }
225 else
226 FAIL;
227 }
228@@ -1804,7 +1883,7 @@ else
229 [(set (match_operand:DI 0 "register_operand" "=d,d")
230 (ashift:DI (match_operand:DI 1 "register_operand" "d,d")
231 (match_operand:DI 2 "arith_operand" "I,d")))]
232- "TARGET_MB_64"
233+ "TARGET_MB_64 && TARGET_BARREL_SHIFT"
234 "@
235 bsllli\t%0,%1,%2
236 bslll\t%0,%1,%2"
237@@ -1812,6 +1891,51 @@ else
238 (set_attr "mode" "DI,DI")
239 (set_attr "length" "4,4")]
240 )
241+
242+(define_insn "ashldi3_const"
243+ [(set (match_operand:DI 0 "register_operand" "=&d")
244+ (ashift:DI (match_operand:DI 1 "register_operand" "d")
245+ (match_operand:DI 2 "immediate_operand" "I")))]
246+ "TARGET_MB_64"
247+ {
248+ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
249+
250+ output_asm_insn ("orli\t%3,r0,%2", operands);
251+ if (REGNO (operands[0]) != REGNO (operands[1]))
252+ output_asm_insn ("addlk\t%0,%1,r0", operands);
253+
254+ output_asm_insn ("addlik\t%3,%3,-1", operands);
255+ output_asm_insn ("beaneid\t%3,.-8", operands);
256+ return "addlk\t%0,%0,%0";
257+ }
258+ [(set_attr "type" "multi")
259+ (set_attr "mode" "DI")
260+ (set_attr "length" "20")]
261+)
262+
263+(define_insn "ashldi3_reg"
264+ [(set (match_operand:DI 0 "register_operand" "=&d")
265+ (ashift:DI (match_operand:DI 1 "register_operand" "d")
266+ (match_operand:DI 2 "register_operand" "d")))]
267+ "TARGET_MB_64"
268+ {
269+ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
270+ output_asm_insn ("andli\t%3,%2,31", operands);
271+ if (REGNO (operands[0]) != REGNO (operands[1]))
272+ output_asm_insn ("addlk\t%0,r0,%1", operands);
273+ /* Exit the loop if zero shift. */
274+ output_asm_insn ("beaeqid\t%3,.+24", operands);
275+ /* Emit the loop. */
276+ output_asm_insn ("addlk\t%0,%0,r0", operands);
277+ output_asm_insn ("addlik\t%3,%3,-1", operands);
278+ output_asm_insn ("beaneid\t%3,.-8", operands);
279+ return "addlk\t%0,%0,%0";
280+ }
281+ [(set_attr "type" "multi")
282+ (set_attr "mode" "DI")
283+ (set_attr "length" "28")]
284+)
285+
286 ;; The following patterns apply when there is no barrel shifter present
287
288 (define_insn "*ashlsi3_with_mul_delay"
289@@ -1945,11 +2069,21 @@ else
290 "TARGET_MB_64"
291 {
292 ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
293-if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
294+if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && TARGET_BARREL_SHIFT)
295 {
296 emit_insn(gen_ashrdi3_long (operands[0], operands[1],operands[2]));
297 DONE;
298 }
299+else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && CONST_INT_P (operands[2]))
300+ {
301+ emit_insn(gen_ashrdi3_const (operands[0], operands[1],operands[2]));
302+ DONE;
303+ }
304+else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && GET_CODE (operands[2]) == REG)
305+ {
306+ emit_insn(gen_ashrdi3_reg (operands[0], operands[1],operands[2]));
307+ DONE;
308+ }
309 else
310 FAIL;
311 }
312@@ -1959,7 +2093,7 @@ else
313 [(set (match_operand:DI 0 "register_operand" "=d,d")
314 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
315 (match_operand:DI 2 "arith_operand" "I,d")))]
316- "TARGET_MB_64"
317+ "TARGET_MB_64 && TARGET_BARREL_SHIFT"
318 "@
319 bslrai\t%0,%1,%2
320 bslra\t%0,%1,%2"
321@@ -1967,6 +2101,51 @@ else
322 (set_attr "mode" "DI,DI")
323 (set_attr "length" "4,4")]
324 )
325+
326+(define_insn "ashrdi3_const"
327+ [(set (match_operand:DI 0 "register_operand" "=&d")
328+ (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
329+ (match_operand:DI 2 "immediate_operand" "I")))]
330+ "TARGET_MB_64"
331+ {
332+ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
333+
334+ output_asm_insn ("orli\t%3,r0,%2", operands);
335+ if (REGNO (operands[0]) != REGNO (operands[1]))
336+ output_asm_insn ("addlk\t%0,%1,r0", operands);
337+
338+ output_asm_insn ("addlik\t%3,%3,-1", operands);
339+ output_asm_insn ("beaneid\t%3,.-8", operands);
340+ return "srla\t%0,%0";
341+ }
342+ [(set_attr "type" "arith")
343+ (set_attr "mode" "DI")
344+ (set_attr "length" "20")]
345+)
346+
347+(define_insn "ashrdi3_reg"
348+ [(set (match_operand:DI 0 "register_operand" "=&d")
349+ (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
350+ (match_operand:DI 2 "register_operand" "d")))]
351+ "TARGET_MB_64"
352+ {
353+ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
354+ output_asm_insn ("andli\t%3,%2,31", operands);
355+ if (REGNO (operands[0]) != REGNO (operands[1]))
356+ output_asm_insn ("addlk\t%0,r0,%1", operands);
357+ /* Exit the loop if zero shift. */
358+ output_asm_insn ("beaeqid\t%3,.+24", operands);
359+ /* Emit the loop. */
360+ output_asm_insn ("addlk\t%0,%0,r0", operands);
361+ output_asm_insn ("addlik\t%3,%3,-1", operands);
362+ output_asm_insn ("beaneid\t%3,.-8", operands);
363+ return "srla\t%0,%0";
364+ }
365+ [(set_attr "type" "multi")
366+ (set_attr "mode" "DI")
367+ (set_attr "length" "28")]
368+)
369+
370 (define_expand "ashrsi3"
371 [(set (match_operand:SI 0 "register_operand" "=&d")
372 (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
373@@ -2084,11 +2263,21 @@ else
374 "TARGET_MB_64"
375 {
376 ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
377-if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
378+if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && TARGET_BARREL_SHIFT)
379 {
380 emit_insn(gen_lshrdi3_long (operands[0], operands[1],operands[2]));
381 DONE;
382 }
383+else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && CONST_INT_P (operands[2]))
384+ {
385+ emit_insn(gen_lshrdi3_const (operands[0], operands[1],operands[2]));
386+ DONE;
387+ }
388+else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && GET_CODE (operands[2]) == REG)
389+ {
390+ emit_insn(gen_lshrdi3_reg (operands[0], operands[1],operands[2]));
391+ DONE;
392+ }
393 else
394 FAIL;
395 }
396@@ -2098,7 +2287,7 @@ else
397 [(set (match_operand:DI 0 "register_operand" "=d,d")
398 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
399 (match_operand:DI 2 "arith_operand" "I,d")))]
400- "TARGET_MB_64"
401+ "TARGET_MB_64 && TARGET_BARREL_SHIFT"
402 "@
403 bslrli\t%0,%1,%2
404 bslrl\t%0,%1,%2"
405@@ -2107,6 +2296,50 @@ else
406 (set_attr "length" "4,4")]
407 )
408
409+(define_insn "lshrdi3_const"
410+ [(set (match_operand:DI 0 "register_operand" "=&d")
411+ (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
412+ (match_operand:DI 2 "immediate_operand" "I")))]
413+ "TARGET_MB_64"
414+ {
415+ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
416+
417+ output_asm_insn ("orli\t%3,r0,%2", operands);
418+ if (REGNO (operands[0]) != REGNO (operands[1]))
419+ output_asm_insn ("addlk\t%0,%1,r0", operands);
420+
421+ output_asm_insn ("addlik\t%3,%3,-1", operands);
422+ output_asm_insn ("beaneid\t%3,.-8", operands);
423+ return "srll\t%0,%0";
424+ }
425+ [(set_attr "type" "multi")
426+ (set_attr "mode" "DI")
427+ (set_attr "length" "20")]
428+)
429+
430+(define_insn "lshrdi3_reg"
431+ [(set (match_operand:DI 0 "register_operand" "=&d")
432+ (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
433+ (match_operand:DI 2 "register_operand" "d")))]
434+ "TARGET_MB_64"
435+ {
436+ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
437+ output_asm_insn ("andli\t%3,%2,31", operands);
438+ if (REGNO (operands[0]) != REGNO (operands[1]))
439+ output_asm_insn ("addlk\t%0,r0,%1", operands);
440+ /* Exit the loop if zero shift. */
441+ output_asm_insn ("beaeqid\t%3,.+24", operands);
442+ /* Emit the loop. */
443+ output_asm_insn ("addlk\t%0,%0,r0", operands);
444+ output_asm_insn ("addlik\t%3,%3,-1", operands);
445+ output_asm_insn ("beaneid\t%3,.-8", operands);
446+ return "srll\t%0,%0";
447+ }
448+ [(set_attr "type" "multi")
449+ (set_attr "mode" "SI")
450+ (set_attr "length" "28")]
451+)
452+
453 (define_expand "lshrsi3"
454 [(set (match_operand:SI 0 "register_operand" "=&d")
455 (lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
456@@ -2233,7 +2466,7 @@ else
457 (eq:DI
458 (match_operand:DI 1 "register_operand" "d")
459 (match_operand:DI 2 "register_operand" "d")))]
460- "TARGET_MB_64"
461+ "TARGET_MB_64 && TARGET_PATTERN_COMPARE"
462 "pcmpleq\t%0,%1,%2"
463 [(set_attr "type" "arith")
464 (set_attr "mode" "DI")
465@@ -2245,7 +2478,7 @@ else
466 (ne:DI
467 (match_operand:DI 1 "register_operand" "d")
468 (match_operand:DI 2 "register_operand" "d")))]
469- "TARGET_MB_64"
470+ "TARGET_MB_64 && TARGET_PATTERN_COMPARE"
471 "pcmplne\t%0,%1,%2"
472 [(set_attr "type" "arith")
473 (set_attr "mode" "DI")
474--
4752.34.1
476
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0047-Added-new-MB-64-single-register-arithmetic-instructi.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0047-Added-new-MB-64-single-register-arithmetic-instructi.patch
new file mode 100644
index 00000000..0272fd3c
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0047-Added-new-MB-64-single-register-arithmetic-instructi.patch
@@ -0,0 +1,107 @@
1From 003f60fa4eedddd15de6e9f633bffec1a887fe45 Mon Sep 17 00:00:00 2001
2From: Nagaraju <nmekala@xilinx.com>
3Date: Fri, 23 Aug 2019 16:16:53 +0530
4Subject: [PATCH 47/54] Added new MB-64 single register arithmetic instructions
5
6---
7 gcc/config/microblaze/microblaze.md | 56 +++++++++++++++++++++++++++++
8 1 file changed, 56 insertions(+)
9
10diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
11index 9bc9512db8e..9172f1bc209 100644
12--- a/gcc/config/microblaze/microblaze.md
13+++ b/gcc/config/microblaze/microblaze.md
14@@ -654,6 +654,18 @@
15 }
16 })
17
18+(define_insn "adddi3_int"
19+ [(set (match_operand:DI 0 "register_operand" "=d")
20+ (plus:DI (match_operand:DI 1 "register_operand" "%0")
21+ (match_operand:DI 2 "immediate_operand" "I")))]
22+ "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767)"
23+ "@
24+ addlik\t%0,%2"
25+ [(set_attr "type" "darith")
26+ (set_attr "mode" "DI")
27+ (set_attr "length" "4")]
28+)
29+
30 (define_insn "*adddi3_long"
31 [(set (match_operand:DI 0 "register_operand" "=d,d")
32 (plus:DI (match_operand:DI 1 "register_operand" "%d,d")
33@@ -719,6 +731,18 @@
34 {
35 }")
36
37+(define_insn "subdi316imm"
38+ [(set (match_operand:DI 0 "register_operand" "=d")
39+ (minus:DI (match_operand:DI 1 "register_operand" "d")
40+ (match_operand:DI 2 "arith_operand" "K")))]
41+ "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767) && (REGNO (operands[0]) == REGNO (operands[1]))"
42+ "@
43+ addlik\t%0,-%2"
44+ [(set_attr "type" "darith")
45+ (set_attr "mode" "DI")
46+ (set_attr "length" "4")])
47+
48+
49 (define_insn "subsidi3"
50 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
51 (minus:DI (match_operand:DI 1 "register_operand" "d,d,d")
52@@ -1015,6 +1039,17 @@
53 ;; Logical
54 ;;----------------------------------------------------------------
55
56+(define_insn "anddi3imm16"
57+ [(set (match_operand:DI 0 "register_operand" "=d")
58+ (and:DI (match_operand:DI 1 "arith_operand" "%0")
59+ (match_operand:DI 2 "arith_operand" "K")))]
60+ "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767)"
61+ "@
62+ andli\t%0,%2"
63+ [(set_attr "type" "darith")
64+ (set_attr "mode" "DI")
65+ (set_attr "length" "4")])
66+
67 (define_insn "anddi3"
68 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
69 (and:DI (match_operand:DI 1 "arith_operand" "d,d,d")
70@@ -1042,6 +1077,16 @@
71 (set_attr "mode" "SI,SI,SI,SI")
72 (set_attr "length" "4,8,8,8")])
73
74+(define_insn "iordi3imm16"
75+ [(set (match_operand:DI 0 "register_operand" "=d")
76+ (ior:DI (match_operand:DI 1 "arith_operand" "%0")
77+ (match_operand:DI 2 "arith_operand" "K")))]
78+ "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767)"
79+ "@
80+ orli\t%0,%2"
81+ [(set_attr "type" "darith")
82+ (set_attr "mode" "DI")
83+ (set_attr "length" "4")])
84
85 (define_insn "iordi3"
86 [(set (match_operand:DI 0 "register_operand" "=d,d")
87@@ -1069,6 +1114,17 @@
88 (set_attr "mode" "SI,SI,SI,SI")
89 (set_attr "length" "4,8,8,8")])
90
91+(define_insn "xordi3imm16"
92+ [(set (match_operand:DI 0 "register_operand" "=d")
93+ (xor:DI (match_operand:DI 1 "arith_operand" "%0")
94+ (match_operand:DI 2 "arith_operand" "K")))]
95+ "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767)"
96+ "@
97+ xorli\t%0,%2"
98+ [(set_attr "type" "darith")
99+ (set_attr "mode" "DI")
100+ (set_attr "length" "4")])
101+
102 (define_insn "xordi3"
103 [(set (match_operand:DI 0 "register_operand" "=d,d")
104 (xor:DI (match_operand:DI 1 "arith_operand" "%d,d")
105--
1062.34.1
107
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0048-Added-support-for-64-bit-Immediate-values.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0048-Added-support-for-64-bit-Immediate-values.patch
new file mode 100644
index 00000000..0be495a8
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0048-Added-support-for-64-bit-Immediate-values.patch
@@ -0,0 +1,43 @@
1From 8d20c82d95e22a42551b446c087d9e06958a3580 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Mon, 26 Aug 2019 15:55:22 +0530
4Subject: [PATCH 48/54] Added support for 64 bit Immediate values.
5
6---
7 gcc/config/microblaze/constraints.md | 4 ++--
8 gcc/config/microblaze/microblaze.md | 3 +--
9 2 files changed, 3 insertions(+), 4 deletions(-)
10
11diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md
12index fa605831bfe..40cd88a870c 100644
13--- a/gcc/config/microblaze/constraints.md
14+++ b/gcc/config/microblaze/constraints.md
15@@ -53,9 +53,9 @@
16 (match_test "ival > 0 && ival < 0x10000")))
17
18 (define_constraint "K"
19- "A constant in the range 0xffffff8000000000L to 0x0000007fffffffffL (inclusive)."
20+ "A constant in the range -9223372036854775808 to 9223372036854775807 (inclusive)."
21 (and (match_code "const_int")
22- (match_test "ival > (long long)-549755813888 && ival < (long long)549755813887")))
23+ (match_test "ival > (long long)-9223372036854775808 && ival < (long long)9223372036854775807")))
24
25
26 ;; Define floating point constraints
27diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
28index 9172f1bc209..f41474feca6 100644
29--- a/gcc/config/microblaze/microblaze.md
30+++ b/gcc/config/microblaze/microblaze.md
31@@ -1332,8 +1332,7 @@
32 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d")
33 (match_operand:DI 1 "immediate_operand" "J,I,Mnis"))]
34 "TARGET_MB_64 && (register_operand (operands[0], DImode) &&
35- (GET_CODE (operands[1]) == CONST_INT &&
36- (INTVAL (operands[1]) <= (long long)549755813887 && INTVAL (operands[1]) >= (long long)-549755813888)))"
37+ (GET_CODE (operands[1]) == CONST_INT))"
38 "@
39 addlk\t%0,r0,r0\t
40 addlik\t%0,r0,%1\t #N1 %X1
41--
422.34.1
43
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0049-Fix-Compiler-crash-with-freg-struct-return-This-patc.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0049-Fix-Compiler-crash-with-freg-struct-return-This-patc.patch
new file mode 100644
index 00000000..ca813796
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0049-Fix-Compiler-crash-with-freg-struct-return-This-patc.patch
@@ -0,0 +1,76 @@
1From 8107e0be46e5bdbfc353648ce5129afde5275ea9 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Tue, 13 Sep 2022 16:06:10 +0530
4Subject: [PATCH 49/54] Fix Compiler crash with -freg-struct-return This patch
5 fixes a bug in MB GCC regarding the passing struct values in registers.
6 Currently we are only handling SImode With this patch all other modes are
7 handled properly
8
9 Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
10---
11 gcc/config/microblaze/microblaze.cc | 11 ++++++++++-
12 gcc/config/microblaze/microblaze.h | 19 -------------------
13 2 files changed, 10 insertions(+), 20 deletions(-)
14
15diff --git a/gcc/config/microblaze/microblaze.cc b/gcc/config/microblaze/microblaze.cc
16index f949a8863d3..4748c8c1f0d 100644
17--- a/gcc/config/microblaze/microblaze.cc
18+++ b/gcc/config/microblaze/microblaze.cc
19@@ -3918,7 +3918,16 @@ microblaze_function_value (const_tree valtype,
20 const_tree func ATTRIBUTE_UNUSED,
21 bool outgoing ATTRIBUTE_UNUSED)
22 {
23- return LIBCALL_VALUE (TYPE_MODE (valtype));
24+ return gen_rtx_REG (TYPE_MODE (valtype), GP_RETURN);
25+}
26+
27+#undef TARGET_LIBCALL_VALUE
28+#define TARGET_LIBCALL_VALUE microblaze_libcall_value
29+
30+rtx
31+microblaze_libcall_value (machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
32+{
33+ return gen_rtx_REG (mode, GP_RETURN);
34 }
35
36 /* Implement TARGET_SCHED_ADJUST_COST. */
37diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
38index 4d6babfe9c4..eea360fda47 100644
39--- a/gcc/config/microblaze/microblaze.h
40+++ b/gcc/config/microblaze/microblaze.h
41@@ -266,13 +266,6 @@ extern enum pipeline_type microblaze_pipe;
42
43 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
44
45-#ifndef __arch64__
46-#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
47- if (GET_MODE_CLASS (MODE) == MODE_INT \
48- && GET_MODE_SIZE (MODE) < 4) \
49- (MODE) = SImode;
50-#endif
51-
52 /* Standard register usage. */
53
54 /* On the MicroBlaze, we have 32 integer registers */
55@@ -471,18 +464,6 @@ extern struct microblaze_frame_info current_frame_info;
56
57 #define MAX_ARGS_IN_REGISTERS MB_ABI_MAX_ARG_REGS
58
59-#ifdef __aarch64__
60-#define LIBCALL_VALUE(MODE) \
61- gen_rtx_REG (MODE,GP_RETURN)
62-#else
63-#define LIBCALL_VALUE(MODE) \
64- gen_rtx_REG ( \
65- ((GET_MODE_CLASS (MODE) != MODE_INT \
66- || GET_MODE_SIZE (MODE) >= 4) \
67- ? (MODE) \
68- : SImode), GP_RETURN)
69-#endif
70-
71 /* 1 if N is a possible register number for a function value.
72 On the MicroBlaze, R2 R3 are the only register thus used.
73 Currently, R2 are only implemented here (C has no complex type) */
74--
752.34.1
76
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0050-Add-TARGET_OPTION_OPTIMIZATION-and-disable-fivopts-b.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0050-Add-TARGET_OPTION_OPTIMIZATION-and-disable-fivopts-b.patch
new file mode 100644
index 00000000..3b8fad81
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0050-Add-TARGET_OPTION_OPTIMIZATION-and-disable-fivopts-b.patch
@@ -0,0 +1,50 @@
1From b7fb925d6277d11e4014aa1731fc58813e30761f Mon Sep 17 00:00:00 2001
2From: Nagaraju <nmekala@xilinx.com>
3Date: Wed, 8 May 2019 14:12:03 +0530
4Subject: [PATCH 50/54] Add TARGET_OPTION_OPTIMIZATION and disable fivopts by
5 default
6
7Added TARGET_OPTION_OPTIMIZATIONS and Turn off ivopts by default.
8
9 * gcc/common/config/microblaze/microblaze-common.c
10 (microblaze_option_optimization_table): Disable fivopts by default.
11
12Signed-off-by: Nagaraju Mekala <nmekala@xilinx.com>
13 Mahesh Bodapati <mbodapat@xilinx.com>
14Conflicts:
15 gcc/common/config/microblaze/microblaze-common.c
16
17Conflicts:
18 gcc/common/config/microblaze/microblaze-common.c
19---
20 gcc/common/config/microblaze/microblaze-common.cc | 13 +++++++++++++
21 1 file changed, 13 insertions(+)
22
23diff --git a/gcc/common/config/microblaze/microblaze-common.cc b/gcc/common/config/microblaze/microblaze-common.cc
24index 8750b022447..8a924e8a997 100644
25--- a/gcc/common/config/microblaze/microblaze-common.cc
26+++ b/gcc/common/config/microblaze/microblaze-common.cc
27@@ -24,7 +24,20 @@
28 #include "common/common-target.h"
29 #include "common/common-target-def.h"
30
31+/* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
32+static const struct default_options microblaze_option_optimization_table[] =
33+ {
34+ /* Turn off ivopts by default. It messes up cse.
35+ { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 }, */
36+ { OPT_LEVELS_ALL, OPT_fivopts, NULL, 0 },
37+ { OPT_LEVELS_NONE, 0, NULL, 0 }
38+ };
39+
40+
41 #undef TARGET_DEFAULT_TARGET_FLAGS
42 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
43
44+#undef TARGET_OPTION_OPTIMIZATION_TABLE
45+#define TARGET_OPTION_OPTIMIZATION_TABLE microblaze_option_optimization_table
46+
47 struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
48--
492.34.1
50
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0051-Reducing-Stack-space-for-arguments.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0051-Reducing-Stack-space-for-arguments.patch
new file mode 100644
index 00000000..648da43a
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0051-Reducing-Stack-space-for-arguments.patch
@@ -0,0 +1,189 @@
1From a464c0e6070cac9b40b7fe760e25cbd484a615a7 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Tue, 13 Sep 2022 16:35:00 +0530
4Subject: [PATCH 51/54] Reducing Stack space for arguments
5
6 Currently in Microblaze target stack space for arguments in register is being
7 allocated even if there are no arguments in the function.
8 This patch will optimize the extra 24 bytes that are being allocated.
9
10 Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
11 :Ajit Agarwal <ajitkum@xilinx.com>
12---
13 gcc/config/microblaze/microblaze-protos.h | 1 +
14 gcc/config/microblaze/microblaze.cc | 130 ++++++++++++++++++++++
15 gcc/config/microblaze/microblaze.h | 4 +-
16 3 files changed, 133 insertions(+), 2 deletions(-)
17
18diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h
19index 0e9f783c4a4..091d8d9a51b 100644
20--- a/gcc/config/microblaze/microblaze-protos.h
21+++ b/gcc/config/microblaze/microblaze-protos.h
22@@ -60,6 +60,7 @@ extern int symbol_mentioned_p (rtx);
23 extern int label_mentioned_p (rtx);
24 extern bool microblaze_cannot_force_const_mem (machine_mode, rtx);
25 extern void microblaze_eh_return (rtx op0);
26+int microblaze_reg_parm_stack_space(tree fun);
27 #endif /* RTX_CODE */
28
29 /* Declare functions in microblaze-c.cc. */
30diff --git a/gcc/config/microblaze/microblaze.cc b/gcc/config/microblaze/microblaze.cc
31index 4748c8c1f0d..e6d3f35370c 100644
32--- a/gcc/config/microblaze/microblaze.cc
33+++ b/gcc/config/microblaze/microblaze.cc
34@@ -2086,6 +2086,136 @@ microblaze_must_save_register (int regno)
35 return 0;
36 }
37
38+static bool
39+microblaze_parm_needs_stack (cumulative_args_t args_so_far, tree type)
40+{
41+ int unsignedp;
42+ rtx entry_parm;
43+
44+ /* Catch errors. */
45+ if (type == NULL || type == error_mark_node)
46+ return true;
47+
48+ if (TREE_CODE (type) == POINTER_TYPE)
49+ return true;
50+
51+ /* Handle types with no storage requirement. */
52+ if (TYPE_MODE (type) == VOIDmode)
53+ return false;
54+
55+ /* Handle complex types. */
56+ if (TREE_CODE (type) == COMPLEX_TYPE)
57+ return (microblaze_parm_needs_stack (args_so_far, TREE_TYPE (type))
58+ || microblaze_parm_needs_stack (args_so_far, TREE_TYPE (type)));
59+
60+ /* Handle transparent aggregates. */
61+ if ((TREE_CODE (type) == UNION_TYPE || TREE_CODE (type) == RECORD_TYPE)
62+ && TYPE_TRANSPARENT_AGGR (type))
63+ type = TREE_TYPE (first_field (type));
64+
65+ /* See if this arg was passed by invisible reference. */
66+ function_arg_info arg (type, /*named=*/true);
67+ apply_pass_by_reference_rules (get_cumulative_args (args_so_far), arg);
68+
69+ /* Find mode as it is passed by the ABI. */
70+ unsignedp = TYPE_UNSIGNED (type);
71+ arg.mode = promote_mode (arg.type, arg.mode, &unsignedp);
72+
73+ /* If there is no incoming register, we need a stack. */
74+ entry_parm = microblaze_function_arg (args_so_far, arg);
75+ if (entry_parm == NULL)
76+ return true;
77+
78+ /* Likewise if we need to pass both in registers and on the stack. */
79+ if (GET_CODE (entry_parm) == PARALLEL
80+ && XEXP (XVECEXP (entry_parm, 0, 0), 0) == NULL_RTX)
81+ return true;
82+
83+ /* Also true if we're partially in registers and partially not. */
84+ if (function_arg_partial_bytes (args_so_far, arg) != 0)
85+ return true;
86+
87+ /* Update info on where next arg arrives in registers. */
88+ microblaze_function_arg_advance (args_so_far, arg);
89+ return false;
90+}
91+
92+static bool
93+microblaze_function_parms_need_stack (tree fun, bool incoming)
94+{
95+ tree fntype, result;
96+ CUMULATIVE_ARGS args_so_far_v;
97+ cumulative_args_t args_so_far;
98+ int num_of_args = 0;
99+
100+ /* Must be a libcall, all of which only use reg parms. */
101+ if (!fun)
102+ return true;
103+
104+ fntype = fun;
105+ if (!TYPE_P (fun))
106+ fntype = TREE_TYPE (fun);
107+
108+ /* Varargs functions need the parameter save area. */
109+ if ((!incoming && !prototype_p (fntype)) || stdarg_p (fntype))
110+ return true;
111+
112+ INIT_CUMULATIVE_ARGS(args_so_far_v, fntype, NULL_RTX,0,0);
113+ args_so_far = pack_cumulative_args (&args_so_far_v);
114+
115+ /* When incoming, we will have been passed the function decl.
116+ * * It is necessary to use the decl to handle K&R style functions,
117+ * * where TYPE_ARG_TYPES may not be available. */
118+ if (incoming)
119+ {
120+ gcc_assert (DECL_P (fun));
121+ result = DECL_RESULT (fun);
122+ }
123+ else
124+ result = TREE_TYPE (fntype);
125+
126+ if (result && aggregate_value_p (result, fntype))
127+ {
128+ if (!TYPE_P (result))
129+ result = build_pointer_type (result);
130+ microblaze_parm_needs_stack (args_so_far, result);
131+ }
132+
133+ if (incoming)
134+ {
135+ tree parm;
136+ for (parm = DECL_ARGUMENTS (fun);
137+ parm && parm != void_list_node;
138+ parm = TREE_CHAIN (parm))
139+ if (microblaze_parm_needs_stack (args_so_far, TREE_TYPE (parm)))
140+ return true;
141+ }
142+ else
143+ {
144+ function_args_iterator args_iter;
145+ tree arg_type;
146+
147+ FOREACH_FUNCTION_ARGS (fntype, arg_type, args_iter)
148+ {
149+ num_of_args;
150+ if (microblaze_parm_needs_stack (args_so_far, arg_type))
151+ return true;
152+ }
153+ }
154+
155+ if (num_of_args > 3) return true;
156+
157+ return false;
158+}
159+
160+int microblaze_reg_parm_stack_space(tree fun)
161+{
162+ if (microblaze_function_parms_need_stack (fun,false))
163+ return MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD;
164+ else
165+ return 0;
166+}
167+
168 /* Return the bytes needed to compute the frame pointer from the current
169 stack pointer.
170
171diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
172index eea360fda47..f23805b1c03 100644
173--- a/gcc/config/microblaze/microblaze.h
174+++ b/gcc/config/microblaze/microblaze.h
175@@ -447,9 +447,9 @@ extern struct microblaze_frame_info current_frame_info;
176 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
177 #define DWARF_CIE_DATA_ALIGNMENT -1
178
179-#define REG_PARM_STACK_SPACE(FNDECL) (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD)
180+#define REG_PARM_STACK_SPACE(FNDECL) microblaze_reg_parm_stack_space(FNDECL)
181
182-#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
183+#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
184
185 #define STACK_BOUNDARY (TARGET_MB_64 ? 64 : 32)
186
187--
1882.34.1
189
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0052-If-we-use-break_handler-attribute-then-interrupt-vec.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0052-If-we-use-break_handler-attribute-then-interrupt-vec.patch
new file mode 100644
index 00000000..d0474dd9
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0052-If-we-use-break_handler-attribute-then-interrupt-vec.patch
@@ -0,0 +1,72 @@
1From b792943436857172e7a39e26a00602c7e6620860 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Tue, 13 Sep 2022 16:38:43 +0530
4Subject: [PATCH 52/54] If we use break_handler attribute then interrupt vector
5 call happened to break_handler instead of interrupt_handler. this fix will
6 resolve the issue CR-1081780. This fix will not change the behavior of
7 compiler unless there is a usage of break_handler attribute. signed-off-by :
8 Mahesh Bodapati <mbodapat@xilinx.com>
9
10---
11 gcc/config/microblaze/microblaze.cc | 13 +++++--------
12 1 file changed, 5 insertions(+), 8 deletions(-)
13
14diff --git a/gcc/config/microblaze/microblaze.cc b/gcc/config/microblaze/microblaze.cc
15index e6d3f35370c..58d091fbed2 100644
16--- a/gcc/config/microblaze/microblaze.cc
17+++ b/gcc/config/microblaze/microblaze.cc
18@@ -2025,7 +2025,7 @@ microblaze_save_volatiles (tree func)
19 int
20 microblaze_is_interrupt_variant (void)
21 {
22- return (interrupt_handler || fast_interrupt);
23+ return (interrupt_handler || fast_interrupt || break_handler);
24 }
25 int
26 microblaze_is_break_handler (void)
27@@ -2064,7 +2064,7 @@ microblaze_must_save_register (int regno)
28 {
29 if (df_regs_ever_live_p (regno)
30 || regno == MB_ABI_MSR_SAVE_REG
31- || ((interrupt_handler || fast_interrupt)
32+ || ((interrupt_handler || fast_interrupt || break_handler)
33 && (regno == MB_ABI_ASM_TEMP_REGNUM
34 || regno == MB_ABI_EXCEPTION_RETURN_ADDR_REGNUM)))
35 return 1;
36@@ -2280,9 +2280,6 @@ compute_frame_size (HOST_WIDE_INT size)
37 fast_interrupt =
38 microblaze_fast_interrupt_function_p (current_function_decl);
39 save_volatiles = microblaze_save_volatiles (current_function_decl);
40- if (break_handler)
41- interrupt_handler = break_handler;
42-
43 gp_reg_size = 0;
44 mask = 0;
45 var_size = size;
46@@ -3242,7 +3239,7 @@ microblaze_expand_prologue (void)
47 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
48 const0_rtx));
49
50- if (interrupt_handler)
51+ if (interrupt_handler || break_handler)
52 /* Do not optimize in flow analysis. */
53 MEM_VOLATILE_P (mem_rtx) = 1;
54
55@@ -3353,12 +3350,12 @@ microblaze_expand_epilogue (void)
56 a load-use stall cycle :) This is also important to handle alloca.
57 (See comments for if (frame_pointer_needed) below. */
58
59- if (!crtl->is_leaf || interrupt_handler)
60+ if (!crtl->is_leaf || interrupt_handler || break_handler)
61 {
62 mem_rtx =
63 gen_rtx_MEM (Pmode,
64 gen_rtx_PLUS (Pmode, stack_pointer_rtx, const0_rtx));
65- if (interrupt_handler)
66+ if (interrupt_handler || break_handler)
67 /* Do not optimize in flow analysis. */
68 MEM_VOLATILE_P (mem_rtx) = 1;
69 reg_rtx = gen_rtx_REG (Pmode, MB_ABI_SUB_RETURN_ADDR_REGNUM);
70--
712.34.1
72
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0053-Add-Zero_extended-instructions.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0053-Add-Zero_extended-instructions.patch
new file mode 100644
index 00000000..52017a9d
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0053-Add-Zero_extended-instructions.patch
@@ -0,0 +1,58 @@
1From fbf853f0b9571529dcc72fc53adf4a35abd3e050 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Tue, 13 Sep 2022 16:45:41 +0530
4Subject: [PATCH 53/54] Add Zero_extended instructions
5
6 Due to latest changes in GCC-10.2 MB64 perforamance has reduced
7 We have added zero_extended instructions to get rid of left shift
8 and right shift loops
9
10 [CR/TSR]: TSR-974519
11
12 Signed-off-by: Nagaraju Mekala<nmekala@xilinx.com>
13 Mahesh Bodapati<mbodapat@xilinx.com>
14---
15 gcc/config/microblaze/microblaze.md | 27 +++++++++++++++++++++++++++
16 1 file changed, 27 insertions(+)
17
18diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
19index f41474feca6..aff98604db7 100644
20--- a/gcc/config/microblaze/microblaze.md
21+++ b/gcc/config/microblaze/microblaze.md
22@@ -1191,6 +1191,33 @@
23 (set_attr "mode" "SI,SI,SI")
24 (set_attr "length" "4,4,8")])
25
26+(define_insn "zero_extendhidi2"
27+ [(set (match_operand:DI 0 "register_operand" "=d")
28+ (zero_extend:DI (match_operand:HI 1 "register_operand" "d")))]
29+ "TARGET_MB_64"
30+ "andli\t%0,%1,0xffff"
31+ [(set_attr "type" "no_delay_arith")
32+ (set_attr "mode" "DI")
33+ (set_attr "length" "8")])
34+
35+(define_insn "zero_extendsidi2"
36+ [(set (match_operand:DI 0 "register_operand" "=d")
37+ (zero_extend:DI (match_operand:SI 1 "register_operand" "d")))]
38+ "TARGET_MB_64"
39+ "andli\t%0,%1,0xffffffff"
40+ [(set_attr "type" "no_delay_arith")
41+ (set_attr "mode" "DI")
42+ (set_attr "length" "8")])
43+
44+(define_insn "zero_extendqidi2"
45+ [(set (match_operand:DI 0 "register_operand" "=d")
46+ (zero_extend:DI (match_operand:QI 1 "register_operand" "d")))]
47+ "TARGET_MB_64"
48+ "andli\t%0,%1,0x00ff"
49+ [(set_attr "type" "no_delay_arith")
50+ (set_attr "mode" "DI")
51+ (set_attr "length" "8")])
52+
53 ;;----------------------------------------------------------------
54 ;; Sign extension
55 ;;----------------------------------------------------------------
56--
572.34.1
58
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0054-Fix-failure-with-gcc.c-torture-execute-ashrdi-1.c-Os.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0054-Fix-failure-with-gcc.c-torture-execute-ashrdi-1.c-Os.patch
new file mode 100644
index 00000000..ec8bc0cf
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0054-Fix-failure-with-gcc.c-torture-execute-ashrdi-1.c-Os.patch
@@ -0,0 +1,42 @@
1From 79d007fea870a3b8d72faa90238cee2cdfaf5c85 Mon Sep 17 00:00:00 2001
2From: Gopi Kumar Bulusu <gopi@sankhya.com>
3Date: Fri, 28 Jun 2024 12:18:38 +0530
4Subject: [PATCH 54/54] Fix failure with gcc.c-torture/execute/ashrdi-1.c -Os
5 execution test
6
7The following tests fail with -Os option because a shift instruction
8in a branch delay slot gets replaced with multiple instructions when
9the processor has no barrel shifter. This fix addresses the problem
10by marking the responsible instruction pattern as type multi preventing
11it from being placed in a delay slot.
12
13> gcc.c-torture/execute/ashrdi-1.c -Os execution test
14> gcc.c-torture/execute/pr40057.c -Os execution test
15> gcc.c-torture/execute/pr79121.c -Os execution test
16> gcc.c-torture/execute/pr82524.c -Os execution test
17> c-c++-common/torture/vector-compare-1.c -Os execution test
18> gcc.dg/torture/vec-cvt-1.c -Os execution test
19
20These tests pass with this fix.
21
22Signed-off-by: Gopi Kumar Bulusu <gopi@sankhya.com>
23---
24 gcc/config/microblaze/microblaze.md | 2 +-
25 1 file changed, 1 insertion(+), 1 deletion(-)
26
27diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
28index aff98604db7..0e3981390c8 100644
29--- a/gcc/config/microblaze/microblaze.md
30+++ b/gcc/config/microblaze/microblaze.md
31@@ -2286,7 +2286,7 @@ else
32 output_asm_insn ("bneid\t%3,.-4", operands);
33 return "sra\t%0,%0";
34 }
35- [(set_attr "type" "arith")
36+ [(set_attr "type" "multi")
37 (set_attr "mode" "SI")
38 (set_attr "length" "20")]
39 )
40--
412.34.1
42
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/microblaze-mulitlib-hack.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/microblaze-mulitlib-hack.patch
new file mode 100644
index 00000000..56d8c223
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/microblaze-mulitlib-hack.patch
@@ -0,0 +1,58 @@
1Microblaze Mulitlib hack
2
3Based on the patch:
4
5From c2081c51db589471ea713870c72f13999abda815 Mon Sep 17 00:00:00 2001
6From: Khem Raj <raj.khem@gmail.com>
7Date: Fri, 29 Mar 2013 09:10:06 +0400
8Subject: [PATCH 04/36] 64-bit multilib hack.
9
10GCC has internal multilib handling code but it assumes a very specific rigid directory
11layout. The build system implementation of multilib layout is very generic and allows
12complete customisation of the library directories.
13
14This patch is a partial solution to allow any custom directories to be passed into gcc
15and handled correctly. It forces gcc to use the base_libdir (which is the current
16directory, "."). We need to do this for each multilib that is configured as we don't
17know which compiler options may be being passed into the compiler. Since we have a compiler
18per mulitlib at this point that isn't an issue.
19
20The one problem is the target compiler is only going to work for the default multlilib at
21this point. Ideally we'd figure out which multilibs were being enabled with which paths
22and be able to patch these entries with a complete set of correct paths but this we
23don't have such code at this point. This is something the target gcc recipe should do
24and override these platform defaults in its build config.
25
26Do same for riscv64 and aarch64
27
28RP 15/8/11
29
30Upstream-Status: Inappropriate [OE-Specific]
31
32Signed-off-by: Khem Raj <raj.khem@gmail.com>
33Signed-off-by: Elvis Dowson <elvis.dowson@gmail.com>
34Signed-off-by: Mark Hatle <mark.hatle@windriver.com>
35Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
36
37Index: gcc-9.2.0/gcc/config/microblaze/t-microblaze
38===================================================================
39--- gcc-9.2.0.orig/gcc/config/microblaze/t-microblaze
40+++ gcc-9.2.0/gcc/config/microblaze/t-microblaze
41@@ -1,5 +1,6 @@
42 MULTILIB_OPTIONS = m64 mxl-barrel-shift mlittle-endian mno-xl-soft-mul mxl-multiply-high
43-MULTILIB_DIRNAMES = m64 bs le m mh
44+#MULTILIB_DIRNAMES = m64 bs le m mh
45+MULTILIB_DIRNAMES = . . . . .
46 MULTILIB_EXCEPTIONS = *m64/mxl-multiply-high mxl-multiply-high
47 MULTILIB_EXCEPTIONS += *m64
48 MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift
49Index: gcc-9.2.0/gcc/config/microblaze/t-microblaze-linux
50===================================================================
51--- gcc-9.2.0.orig/gcc/config/microblaze/t-microblaze-linux
52+++ gcc-9.2.0/gcc/config/microblaze/t-microblaze-linux
53@@ -1,3 +1,4 @@
54 MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high
55-MULTILIB_DIRNAMES = bs m mh
56+#MULTILIB_DIRNAMES = bs m mh
57+MULTILIB_DIRNAMES = . . .
58 MULTILIB_EXCEPTIONS = *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2026-05-30 08:54:46 +0000