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-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-13/0046-MB-64-removal-of-barrel-shift-instructions-from-defa.patch476
1 files changed, 476 insertions, 0 deletions
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0046-MB-64-removal-of-barrel-shift-instructions-from-defa.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0046-MB-64-removal-of-barrel-shift-instructions-from-defa.patch
new file mode 100644
index 00000000..5f45d03f
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0046-MB-64-removal-of-barrel-shift-instructions-from-defa.patch
@@ -0,0 +1,476 @@
1From 0776495e85a15c1ad84fd90736059902bb3ea152 Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Tue, 13 Sep 2022 15:59:12 +0530
4Subject: [PATCH 46/54] MB-64 removal of barrel-shift instructions from default
5 By default MB-64 is generatting barrel-shift instructions. It has been
6 removed from default. Barrel-shift instructions will be generated only if
7 barrel-shifter is enabled. Similarly to double instructions as well.
8
9 Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
10---
11 gcc/config/microblaze/microblaze.cc | 2 +-
12 gcc/config/microblaze/microblaze.md | 269 ++++++++++++++++++++++++++--
13 2 files changed, 252 insertions(+), 19 deletions(-)
14
15diff --git a/gcc/config/microblaze/microblaze.cc b/gcc/config/microblaze/microblaze.cc
16index 965a041ea8c..f949a8863d3 100644
17--- a/gcc/config/microblaze/microblaze.cc
18+++ b/gcc/config/microblaze/microblaze.cc
19@@ -3880,7 +3880,7 @@ microblaze_expand_divide (rtx operands[])
20 emit_insn (gen_rtx_CLOBBER (Pmode, reg18));
21
22 if (TARGET_MB_64) {
23- emit_insn (gen_ashldi3_long (regt1, operands[1], GEN_INT(4)));
24+ emit_insn (gen_ashldi3 (regt1, operands[1], GEN_INT(4)));
25 emit_insn (gen_adddi3 (regt1, regt1, operands[2]));
26 }
27 else {
28diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
29index f661ba1c241..9bc9512db8e 100644
30--- a/gcc/config/microblaze/microblaze.md
31+++ b/gcc/config/microblaze/microblaze.md
32@@ -547,7 +547,7 @@
33 [(set (match_operand:DF 0 "register_operand" "=d")
34 (plus:DF (match_operand:DF 1 "register_operand" "d")
35 (match_operand:DF 2 "register_operand" "d")))]
36- "TARGET_MB_64"
37+ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
38 "dadd\t%0,%1,%2"
39 [(set_attr "type" "fadd")
40 (set_attr "mode" "DF")
41@@ -557,7 +557,7 @@
42 [(set (match_operand:DF 0 "register_operand" "=d")
43 (minus:DF (match_operand:DF 1 "register_operand" "d")
44 (match_operand:DF 2 "register_operand" "d")))]
45- "TARGET_MB_64"
46+ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
47 "drsub\t%0,%2,%1"
48 [(set_attr "type" "frsub")
49 (set_attr "mode" "DF")
50@@ -567,7 +567,7 @@
51 [(set (match_operand:DF 0 "register_operand" "=d")
52 (mult:DF (match_operand:DF 1 "register_operand" "d")
53 (match_operand:DF 2 "register_operand" "d")))]
54- "TARGET_MB_64"
55+ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
56 "dmul\t%0,%1,%2"
57 [(set_attr "type" "fmul")
58 (set_attr "mode" "DF")
59@@ -577,7 +577,7 @@
60 [(set (match_operand:DF 0 "register_operand" "=d")
61 (div:DF (match_operand:DF 1 "register_operand" "d")
62 (match_operand:DF 2 "register_operand" "d")))]
63- "TARGET_MB_64"
64+ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
65 "ddiv\t%0,%2,%1"
66 [(set_attr "type" "fdiv")
67 (set_attr "mode" "DF")
68@@ -587,7 +587,7 @@
69 (define_insn "sqrtdf2"
70 [(set (match_operand:DF 0 "register_operand" "=d")
71 (sqrt:DF (match_operand:DF 1 "register_operand" "d")))]
72- "TARGET_MB_64"
73+ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
74 "dsqrt\t%0,%1"
75 [(set_attr "type" "fsqrt")
76 (set_attr "mode" "DF")
77@@ -596,7 +596,7 @@
78 (define_insn "floatdidf2"
79 [(set (match_operand:DF 0 "register_operand" "=d")
80 (float:DF (match_operand:DI 1 "register_operand" "d")))]
81- "TARGET_MB_64"
82+ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
83 "dbl\t%0,%1"
84 [(set_attr "type" "fcvt")
85 (set_attr "mode" "DF")
86@@ -605,7 +605,7 @@
87 (define_insn "fix_truncdfdi2"
88 [(set (match_operand:DI 0 "register_operand" "=d")
89 (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "d"))))]
90- "TARGET_MB_64"
91+ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
92 "dlong\t%0,%1"
93 [(set_attr "type" "fcvt")
94 (set_attr "mode" "DI")
95@@ -1299,6 +1299,34 @@
96 (set_attr "mode" "DI")
97 (set_attr "length" "4")])
98
99+(define_insn "*movdi_internal2_bshift"
100+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d, d,d,R,m")
101+ (match_operand:DI 1 "move_src_operand" " d,I,Mnis,R,m,dJ,dJ"))]
102+ "TARGET_MB_64 && TARGET_BARREL_SHIFT"
103+ {
104+ switch (which_alternative)
105+ {
106+ case 0:
107+ return "addlk\t%0,%1,r0";
108+ case 1:
109+ case 2:
110+ if (GET_CODE (operands[1]) == CONST_INT &&
111+ (INTVAL (operands[1]) > (long long)549755813887 || INTVAL (operands[1]) < (long long)-549755813888))
112+ return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
113+ else
114+ return "addlik\t%0,r0,%1";
115+ case 3:
116+ case 4:
117+ return "ll%i1\t%0,%1";
118+ case 5:
119+ case 6:
120+ return "sl%i0\t%z1,%0";
121+ }
122+ }
123+ [(set_attr "type" "load,no_delay_load,no_delay_load,no_delay_load,no_delay_load,no_delay_store,no_delay_store")
124+ (set_attr "mode" "DI")
125+ (set_attr "length" "4,4,12,4,8,4,8")])
126+
127 (define_insn "*movdi_internal2"
128 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d, d,d,R,m")
129 (match_operand:DI 1 "move_src_operand" " d,I,Mnis,R,m,dJ,dJ"))]
130@@ -1312,7 +1340,15 @@
131 case 2:
132 if (GET_CODE (operands[1]) == CONST_INT &&
133 (INTVAL (operands[1]) > (long long)549755813887 || INTVAL (operands[1]) < (long long)-549755813888))
134- return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
135+ {
136+ operands[2] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
137+ output_asm_insn ("addlik\t%0,r0,%h1", operands);
138+ output_asm_insn ("addlik\t%2,r0,32", operands);
139+ output_asm_insn ("addlik\t%2,%2,-1", operands);
140+ output_asm_insn ("beaneid\t%2,.-8", operands);
141+ output_asm_insn ("addlk\t%0,%0,%0", operands);
142+ return "addlik\t%0,%0,%j1 #li => la";
143+ }
144 else
145 return "addlik\t%0,r0,%1";
146 case 3:
147@@ -1387,7 +1423,7 @@
148 (define_insn "movdi_long_int"
149 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
150 (match_operand:DI 1 "general_operand" "i"))]
151- "TARGET_MB_64"
152+ "TARGET_MB_64 && TARGET_BARREL_SHIFT"
153 "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
154 [(set_attr "type" "no_delay_arith")
155 (set_attr "mode" "DI")
156@@ -1654,6 +1690,33 @@
157 ;; movdf_internal
158 ;; Applies to both TARGET_SOFT_FLOAT and TARGET_HARD_FLOAT
159 ;;
160+(define_insn "*movdf_internal_64_bshift"
161+ [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,d,m")
162+ (match_operand:DF 1 "general_operand" "d,dG,m,F,T,d"))]
163+ "TARGET_MB_64 && TARGET_BARREL_SHIFT"
164+ {
165+ switch (which_alternative)
166+ {
167+ case 0:
168+ return "addlk\t%0,%1,r0";
169+ case 1:
170+ return "addlk\t%0,r0,r0";
171+ case 2:
172+ case 4:
173+ return "ll%i1\t%0,%1";
174+ case 3:
175+ {
176+ return "addlik\t%0,r0,%j1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%h1 #Xfer Lo";
177+ }
178+ case 5:
179+ return "sl%i0\t%1,%0";
180+ }
181+ gcc_unreachable ();
182+ }
183+ [(set_attr "type" "no_delay_move,no_delay_move,no_delay_load,no_delay_load,no_delay_load,no_delay_store")
184+ (set_attr "mode" "DF")
185+ (set_attr "length" "4,4,4,16,4,4")])
186+
187 (define_insn "*movdf_internal_64"
188 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,d,m")
189 (match_operand:DF 1 "general_operand" "d,dG,m,F,T,d"))]
190@@ -1670,7 +1733,13 @@
191 return "ll%i1\t%0,%1";
192 case 3:
193 {
194- return "addlik\t%0,r0,%j1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%h1 #Xfer Lo";
195+ operands[2] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
196+ output_asm_insn ("addlik\t%0,r0,%h1", operands);
197+ output_asm_insn ("addlik\t%2,r0,32", operands);
198+ output_asm_insn ("addlik\t%2,%2,-1", operands);
199+ output_asm_insn ("beaneid\t%2,.-8", operands);
200+ output_asm_insn ("addlk\t%0,%0,%0", operands);
201+ return "addlik\t%0,%0,%j1 #li => la";
202 }
203 case 5:
204 return "sl%i0\t%1,%0";
205@@ -1790,11 +1859,21 @@
206 "TARGET_MB_64"
207 {
208 ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
209-if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
210+if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && TARGET_BARREL_SHIFT)
211 {
212 emit_insn(gen_ashldi3_long (operands[0], operands[1],operands[2]));
213 DONE;
214 }
215+else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && CONST_INT_P (operands[2]))
216+ {
217+ emit_insn(gen_ashldi3_const (operands[0], operands[1],operands[2]));
218+ DONE;
219+ }
220+else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && GET_CODE (operands[2]) == REG)
221+ {
222+ emit_insn(gen_ashldi3_reg (operands[0], operands[1],operands[2]));
223+ DONE;
224+ }
225 else
226 FAIL;
227 }
228@@ -1804,7 +1883,7 @@ else
229 [(set (match_operand:DI 0 "register_operand" "=d,d")
230 (ashift:DI (match_operand:DI 1 "register_operand" "d,d")
231 (match_operand:DI 2 "arith_operand" "I,d")))]
232- "TARGET_MB_64"
233+ "TARGET_MB_64 && TARGET_BARREL_SHIFT"
234 "@
235 bsllli\t%0,%1,%2
236 bslll\t%0,%1,%2"
237@@ -1812,6 +1891,51 @@ else
238 (set_attr "mode" "DI,DI")
239 (set_attr "length" "4,4")]
240 )
241+
242+(define_insn "ashldi3_const"
243+ [(set (match_operand:DI 0 "register_operand" "=&d")
244+ (ashift:DI (match_operand:DI 1 "register_operand" "d")
245+ (match_operand:DI 2 "immediate_operand" "I")))]
246+ "TARGET_MB_64"
247+ {
248+ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
249+
250+ output_asm_insn ("orli\t%3,r0,%2", operands);
251+ if (REGNO (operands[0]) != REGNO (operands[1]))
252+ output_asm_insn ("addlk\t%0,%1,r0", operands);
253+
254+ output_asm_insn ("addlik\t%3,%3,-1", operands);
255+ output_asm_insn ("beaneid\t%3,.-8", operands);
256+ return "addlk\t%0,%0,%0";
257+ }
258+ [(set_attr "type" "multi")
259+ (set_attr "mode" "DI")
260+ (set_attr "length" "20")]
261+)
262+
263+(define_insn "ashldi3_reg"
264+ [(set (match_operand:DI 0 "register_operand" "=&d")
265+ (ashift:DI (match_operand:DI 1 "register_operand" "d")
266+ (match_operand:DI 2 "register_operand" "d")))]
267+ "TARGET_MB_64"
268+ {
269+ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
270+ output_asm_insn ("andli\t%3,%2,31", operands);
271+ if (REGNO (operands[0]) != REGNO (operands[1]))
272+ output_asm_insn ("addlk\t%0,r0,%1", operands);
273+ /* Exit the loop if zero shift. */
274+ output_asm_insn ("beaeqid\t%3,.+24", operands);
275+ /* Emit the loop. */
276+ output_asm_insn ("addlk\t%0,%0,r0", operands);
277+ output_asm_insn ("addlik\t%3,%3,-1", operands);
278+ output_asm_insn ("beaneid\t%3,.-8", operands);
279+ return "addlk\t%0,%0,%0";
280+ }
281+ [(set_attr "type" "multi")
282+ (set_attr "mode" "DI")
283+ (set_attr "length" "28")]
284+)
285+
286 ;; The following patterns apply when there is no barrel shifter present
287
288 (define_insn "*ashlsi3_with_mul_delay"
289@@ -1945,11 +2069,21 @@ else
290 "TARGET_MB_64"
291 {
292 ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
293-if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
294+if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && TARGET_BARREL_SHIFT)
295 {
296 emit_insn(gen_ashrdi3_long (operands[0], operands[1],operands[2]));
297 DONE;
298 }
299+else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && CONST_INT_P (operands[2]))
300+ {
301+ emit_insn(gen_ashrdi3_const (operands[0], operands[1],operands[2]));
302+ DONE;
303+ }
304+else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && GET_CODE (operands[2]) == REG)
305+ {
306+ emit_insn(gen_ashrdi3_reg (operands[0], operands[1],operands[2]));
307+ DONE;
308+ }
309 else
310 FAIL;
311 }
312@@ -1959,7 +2093,7 @@ else
313 [(set (match_operand:DI 0 "register_operand" "=d,d")
314 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
315 (match_operand:DI 2 "arith_operand" "I,d")))]
316- "TARGET_MB_64"
317+ "TARGET_MB_64 && TARGET_BARREL_SHIFT"
318 "@
319 bslrai\t%0,%1,%2
320 bslra\t%0,%1,%2"
321@@ -1967,6 +2101,51 @@ else
322 (set_attr "mode" "DI,DI")
323 (set_attr "length" "4,4")]
324 )
325+
326+(define_insn "ashrdi3_const"
327+ [(set (match_operand:DI 0 "register_operand" "=&d")
328+ (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
329+ (match_operand:DI 2 "immediate_operand" "I")))]
330+ "TARGET_MB_64"
331+ {
332+ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
333+
334+ output_asm_insn ("orli\t%3,r0,%2", operands);
335+ if (REGNO (operands[0]) != REGNO (operands[1]))
336+ output_asm_insn ("addlk\t%0,%1,r0", operands);
337+
338+ output_asm_insn ("addlik\t%3,%3,-1", operands);
339+ output_asm_insn ("beaneid\t%3,.-8", operands);
340+ return "srla\t%0,%0";
341+ }
342+ [(set_attr "type" "arith")
343+ (set_attr "mode" "DI")
344+ (set_attr "length" "20")]
345+)
346+
347+(define_insn "ashrdi3_reg"
348+ [(set (match_operand:DI 0 "register_operand" "=&d")
349+ (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
350+ (match_operand:DI 2 "register_operand" "d")))]
351+ "TARGET_MB_64"
352+ {
353+ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
354+ output_asm_insn ("andli\t%3,%2,31", operands);
355+ if (REGNO (operands[0]) != REGNO (operands[1]))
356+ output_asm_insn ("addlk\t%0,r0,%1", operands);
357+ /* Exit the loop if zero shift. */
358+ output_asm_insn ("beaeqid\t%3,.+24", operands);
359+ /* Emit the loop. */
360+ output_asm_insn ("addlk\t%0,%0,r0", operands);
361+ output_asm_insn ("addlik\t%3,%3,-1", operands);
362+ output_asm_insn ("beaneid\t%3,.-8", operands);
363+ return "srla\t%0,%0";
364+ }
365+ [(set_attr "type" "multi")
366+ (set_attr "mode" "DI")
367+ (set_attr "length" "28")]
368+)
369+
370 (define_expand "ashrsi3"
371 [(set (match_operand:SI 0 "register_operand" "=&d")
372 (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
373@@ -2084,11 +2263,21 @@ else
374 "TARGET_MB_64"
375 {
376 ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
377-if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
378+if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && TARGET_BARREL_SHIFT)
379 {
380 emit_insn(gen_lshrdi3_long (operands[0], operands[1],operands[2]));
381 DONE;
382 }
383+else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && CONST_INT_P (operands[2]))
384+ {
385+ emit_insn(gen_lshrdi3_const (operands[0], operands[1],operands[2]));
386+ DONE;
387+ }
388+else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && GET_CODE (operands[2]) == REG)
389+ {
390+ emit_insn(gen_lshrdi3_reg (operands[0], operands[1],operands[2]));
391+ DONE;
392+ }
393 else
394 FAIL;
395 }
396@@ -2098,7 +2287,7 @@ else
397 [(set (match_operand:DI 0 "register_operand" "=d,d")
398 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
399 (match_operand:DI 2 "arith_operand" "I,d")))]
400- "TARGET_MB_64"
401+ "TARGET_MB_64 && TARGET_BARREL_SHIFT"
402 "@
403 bslrli\t%0,%1,%2
404 bslrl\t%0,%1,%2"
405@@ -2107,6 +2296,50 @@ else
406 (set_attr "length" "4,4")]
407 )
408
409+(define_insn "lshrdi3_const"
410+ [(set (match_operand:DI 0 "register_operand" "=&d")
411+ (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
412+ (match_operand:DI 2 "immediate_operand" "I")))]
413+ "TARGET_MB_64"
414+ {
415+ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
416+
417+ output_asm_insn ("orli\t%3,r0,%2", operands);
418+ if (REGNO (operands[0]) != REGNO (operands[1]))
419+ output_asm_insn ("addlk\t%0,%1,r0", operands);
420+
421+ output_asm_insn ("addlik\t%3,%3,-1", operands);
422+ output_asm_insn ("beaneid\t%3,.-8", operands);
423+ return "srll\t%0,%0";
424+ }
425+ [(set_attr "type" "multi")
426+ (set_attr "mode" "DI")
427+ (set_attr "length" "20")]
428+)
429+
430+(define_insn "lshrdi3_reg"
431+ [(set (match_operand:DI 0 "register_operand" "=&d")
432+ (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
433+ (match_operand:DI 2 "register_operand" "d")))]
434+ "TARGET_MB_64"
435+ {
436+ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
437+ output_asm_insn ("andli\t%3,%2,31", operands);
438+ if (REGNO (operands[0]) != REGNO (operands[1]))
439+ output_asm_insn ("addlk\t%0,r0,%1", operands);
440+ /* Exit the loop if zero shift. */
441+ output_asm_insn ("beaeqid\t%3,.+24", operands);
442+ /* Emit the loop. */
443+ output_asm_insn ("addlk\t%0,%0,r0", operands);
444+ output_asm_insn ("addlik\t%3,%3,-1", operands);
445+ output_asm_insn ("beaneid\t%3,.-8", operands);
446+ return "srll\t%0,%0";
447+ }
448+ [(set_attr "type" "multi")
449+ (set_attr "mode" "SI")
450+ (set_attr "length" "28")]
451+)
452+
453 (define_expand "lshrsi3"
454 [(set (match_operand:SI 0 "register_operand" "=&d")
455 (lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
456@@ -2233,7 +2466,7 @@ else
457 (eq:DI
458 (match_operand:DI 1 "register_operand" "d")
459 (match_operand:DI 2 "register_operand" "d")))]
460- "TARGET_MB_64"
461+ "TARGET_MB_64 && TARGET_PATTERN_COMPARE"
462 "pcmpleq\t%0,%1,%2"
463 [(set_attr "type" "arith")
464 (set_attr "mode" "DI")
465@@ -2245,7 +2478,7 @@ else
466 (ne:DI
467 (match_operand:DI 1 "register_operand" "d")
468 (match_operand:DI 2 "register_operand" "d")))]
469- "TARGET_MB_64"
470+ "TARGET_MB_64 && TARGET_PATTERN_COMPARE"
471 "pcmplne\t%0,%1,%2"
472 [(set_attr "type" "arith")
473 (set_attr "mode" "DI")
474--
4752.34.1
476
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2026-05-30 06:58:08 +0000