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| author | Sivaprasad Addepalli <sivaprasad.addepalli@xilinx.com> | 2023-12-27 15:51:02 +0530 |
|---|---|---|
| committer | Siva Addepalli <sivaprasad.addepalli@xilinx.com> | 2023-12-27 16:47:10 +0530 |
| commit | 14bb5ea55fb1b71a799bdcf9852c90e850eebf0b (patch) | |
| tree | f266fa99a04c382dc07004671c90f99151564e99 /meta-xilinx-standalone/classes/xlnx-standalone.bbclass | |
| parent | 453912ea7cf9e86ebdcc78b9c2a56a28dcfb4e79 (diff) | |
| download | meta-xilinx-14bb5ea55fb1b71a799bdcf9852c90e850eebf0b.tar.gz | |
embeddedsw : Updated SRCREV for 2024.1_8447
csi2tx Driver: csi2tx driver migrated to decoupling flow.
csi2txss Driver: csi2txss Driver migrate to decoupling flow
Xilsem:Protect error injection test with macro and add XilSEM status prints
sw_services: xilpm: assign value to IOCTL ID
sw_services:xilnvm:Added Microblaze support for versalnet
can: Update the interrupt example for ECC enablement
can: Add ECC enablement for CAN driver
can: Modify XCan_InterruptEnable to enable only the interrupts passed as argument
can: Add new member to config structure
can: Increment driver version
ddrcpsu:Fix compilation warnings
ddrcpsu: Update the driver version to v1.6
canps:Fix compilation warnings
xilpm: versal: server: Fix Mbist clear trigger sequence for XRAM block
Revert "lwip: metadata changes for timestamp"
drivers: Update the compatibility string for the cframe and cfupmc drivers for VersalNet platform
scripts: pyesw: create_bsp.py: Update the compiler flags for psx_pmc microblaze
dp21:Fix Link_Count_Variable updation in RX MST Sideband reply message.
sw_services: xilpki: Correct the PKI_ECC_NIST_P384_KEY_PRIV_GEN_CMD value
lwip: metadata changes for timestamp
Diffstat (limited to 'meta-xilinx-standalone/classes/xlnx-standalone.bbclass')
0 files changed, 0 insertions, 0 deletions