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authorSivaprasad Addepalli <sivaprasad.addepalli@xilinx.com>2023-12-27 15:51:02 +0530
committerSiva Addepalli <sivaprasad.addepalli@xilinx.com>2023-12-27 16:47:10 +0530
commit14bb5ea55fb1b71a799bdcf9852c90e850eebf0b (patch)
treef266fa99a04c382dc07004671c90f99151564e99 /meta-xilinx-standalone/classes
parent453912ea7cf9e86ebdcc78b9c2a56a28dcfb4e79 (diff)
downloadmeta-xilinx-14bb5ea55fb1b71a799bdcf9852c90e850eebf0b.tar.gz
embeddedsw : Updated SRCREV for 2024.1_8447
csi2tx Driver: csi2tx driver migrated to decoupling flow. csi2txss Driver: csi2txss Driver migrate to decoupling flow Xilsem:Protect error injection test with macro and add XilSEM status prints sw_services: xilpm: assign value to IOCTL ID sw_services:xilnvm:Added Microblaze support for versalnet can: Update the interrupt example for ECC enablement can: Add ECC enablement for CAN driver can: Modify XCan_InterruptEnable to enable only the interrupts passed as argument can: Add new member to config structure can: Increment driver version ddrcpsu:Fix compilation warnings ddrcpsu: Update the driver version to v1.6 canps:Fix compilation warnings xilpm: versal: server: Fix Mbist clear trigger sequence for XRAM block Revert "lwip: metadata changes for timestamp" drivers: Update the compatibility string for the cframe and cfupmc drivers for VersalNet platform scripts: pyesw: create_bsp.py: Update the compiler flags for psx_pmc microblaze dp21:Fix Link_Count_Variable updation in RX MST Sideband reply message. sw_services: xilpki: Correct the PKI_ECC_NIST_P384_KEY_PRIV_GEN_CMD value lwip: metadata changes for timestamp
Diffstat (limited to 'meta-xilinx-standalone/classes')
-rw-r--r--meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass2
1 files changed, 1 insertions, 1 deletions
diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass
index 1c1a6fdb..2f67e9fb 100644
--- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass
+++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass
@@ -12,7 +12,7 @@ BRANCH ??= "${@d.getVarFlag('ESW_BRANCH', d.getVar('ESW_VER')) or '${ESW_VER}'}"
12ESW_REV[git] = "${AUTOREV}" 12ESW_REV[git] = "${AUTOREV}"
13ESW_REV[2023.1] = "af784f742dad0ca6e69e05baf8de51152c396b9a" 13ESW_REV[2023.1] = "af784f742dad0ca6e69e05baf8de51152c396b9a"
14ESW_REV[2023.2] = "c9a0ee31b2a14cbcfcb56ca369037319b4ad4847" 14ESW_REV[2023.2] = "c9a0ee31b2a14cbcfcb56ca369037319b4ad4847"
15ESW_REV[2024.1] = "c57d3512a6bc34427c7d948289cb3c5a89b37537" 15ESW_REV[2024.1] = "38d0309fc2f2b9946c3ce1e1aed5aa52b6799374"
16SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" 16SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}"
17 17
18EMBEDDEDSW_BRANCHARG ?= "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH') != '']}" 18EMBEDDEDSW_BRANCHARG ?= "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH') != '']}"