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| author | Sivaprasad Addepalli <sivaprasad.addepalli@xilinx.com> | 2023-09-26 12:53:04 +0530 |
|---|---|---|
| committer | Siva Addepalli <sivaprasad.addepalli@xilinx.com> | 2023-09-26 14:07:11 +0530 |
| commit | 90f3a2744676c70ce9d67db3398416ee48cfe4cd (patch) | |
| tree | 83f538157811ef27c343a1e85619e206fb04c9e4 /.gitmodules | |
| parent | ae34e7bcdad506013a1212609e55dadea0dfe150 (diff) | |
| download | meta-xilinx-90f3a2744676c70ce9d67db3398416ee48cfe4cd.tar.gz | |
dts : Updated SRCREV for 2023.2_9163
versal: Rename VEK280 cosim board
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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