1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
|
From 6209a572f4ec70608564fa7aa0270d640aa421f0 Mon Sep 17 00:00:00 2001
From: Mahesh Bodapati <mbodapat@xilinx.com>
Date: Tue, 2 Nov 2021 17:28:24 +0530
Subject: [PATCH 18/34] [Patch,MicroBlaze : Adding new relocation to support
64bit rodata.
---
bfd/elf64-microblaze.c | 11 +++++++--
gas/config/tc-microblaze.c | 49 ++++++++++++++++++++++++++++++++++----
2 files changed, 54 insertions(+), 6 deletions(-)
diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c
index f16b544b1fc..355e9131987 100644
--- a/bfd/elf64-microblaze.c
+++ b/bfd/elf64-microblaze.c
@@ -1529,6 +1529,7 @@ microblaze_elf_relocate_section (bfd *output_bfd,
case (int) R_MICROBLAZE_64_PCREL :
case (int) R_MICROBLAZE_64:
case (int) R_MICROBLAZE_32:
+ case (int) R_MICROBLAZE_IMML_64:
{
/* r_symndx will be STN_UNDEF (zero) only for relocs against symbols
from removed linkonce sections, or sections discarded by
@@ -1538,6 +1539,8 @@ microblaze_elf_relocate_section (bfd *output_bfd,
relocation += addend;
if (r_type == R_MICROBLAZE_32)// || r_type == R_MICROBLAZE_IMML_64)
bfd_put_32 (input_bfd, relocation, contents + offset);
+ else if (r_type == R_MICROBLAZE_IMML_64)
+ bfd_put_64 (input_bfd, relocation, contents + offset);
else
{
if (r_type == R_MICROBLAZE_64_PCREL)
@@ -1626,7 +1629,7 @@ microblaze_elf_relocate_section (bfd *output_bfd,
}
else
{
- if (r_type == R_MICROBLAZE_32)
+ if (r_type == R_MICROBLAZE_32 || r_type == R_MICROBLAZE_IMML_64)
{
outrel.r_info = ELF64_R_INFO (0, R_MICROBLAZE_REL);
outrel.r_addend = relocation + addend;
@@ -1652,6 +1655,8 @@ microblaze_elf_relocate_section (bfd *output_bfd,
relocation += addend;
if (r_type == R_MICROBLAZE_32)
bfd_put_32 (input_bfd, relocation, contents + offset);
+ else if (r_type == R_MICROBLAZE_IMML_64)
+ bfd_put_64 (input_bfd, relocation, contents + offset + endian);
else
{
if (r_type == R_MICROBLAZE_64_PCREL)
@@ -2166,7 +2171,8 @@ microblaze_elf_relax_section (bfd *abfd,
microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset,
irelscan->r_addend);
}
- if (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)
+ if (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32
+ || ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_IMML_64)
{
isym = isymbuf + ELF64_R_SYM (irelscan->r_info);
@@ -2633,6 +2639,7 @@ microblaze_elf_check_relocs (bfd * abfd,
case R_MICROBLAZE_64:
case R_MICROBLAZE_64_PCREL:
case R_MICROBLAZE_32:
+ case R_MICROBLAZE_IMML_64:
{
if (h != NULL && !bfd_link_pic (info))
{
diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
index d3de049e9c0..76ce516d8aa 100644
--- a/gas/config/tc-microblaze.c
+++ b/gas/config/tc-microblaze.c
@@ -1119,6 +1119,13 @@ md_assemble (char * str)
as_fatal (_("smi pseudo instruction should not use a label in imm field"));
if(streq (name, "lli") || streq (name, "sli"))
opc = str_microblaze_64;
+ else if ((microblaze_arch_size == 64) && ((streq (name, "lbui")
+ || streq (name, "lhui") || streq (name, "lwi") || streq (name, "sbi")
+ || streq (name, "shi") || streq (name, "swi"))))
+ {
+ opc = str_microblaze_64;
+ subtype = opcode->inst_offset_type;
+ }
else if (reg2 == REG_ROSDP)
opc = str_microblaze_ro_anchor;
else if (reg2 == REG_RWSDP)
@@ -1186,7 +1193,10 @@ md_assemble (char * str)
inst |= (immed << IMM_LOW) & IMM_MASK;
}
}
- else if (streq (name, "lli") || streq (name, "sli"))
+ else if (streq (name, "lli") || streq (name, "sli") || ((microblaze_arch_size == 64)
+ && ((streq (name, "lbui")) || streq (name, "lhui")
+ || streq (name, "lwi") || streq (name, "sbi")
+ || streq (name, "shi") || streq (name, "swi"))))
{
temp = immed & 0xFFFFFF8000;
if (temp != 0 && temp != 0xFFFFFF8000)
@@ -1802,6 +1812,11 @@ md_assemble (char * str)
if (exp.X_md != 0)
subtype = get_imm_otype(exp.X_md);
+ else if (streq (name, "brealid") || streq (name, "breaid") || streq (name, "breai"))
+ {
+ opc = str_microblaze_64;
+ subtype = opcode->inst_offset_type;
+ }
else
subtype = opcode->inst_offset_type;
@@ -1819,6 +1834,31 @@ md_assemble (char * str)
output = frag_more (isize);
immed = exp.X_add_number;
}
+ if (streq (name, "brealid") || streq (name, "breaid") || streq (name, "breai"))
+ {
+ temp = immed & 0xFFFFFF8000;
+ if (temp != 0 && temp != 0xFFFFFF8000)
+ {
+ /* Needs an immediate inst. */
+ opcode1 = (struct op_code_struct *) str_hash_find (opcode_hash_control, "imml");
+ if (opcode1 == NULL)
+ {
+ as_bad (_("unknown opcode \"%s\""), "imml");
+ return;
+ }
+ inst1 = opcode1->bit_sequence;
+ inst1 |= ((immed & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK;
+ output[0] = INST_BYTE0 (inst1);
+ output[1] = INST_BYTE1 (inst1);
+ output[2] = INST_BYTE2 (inst1);
+ output[3] = INST_BYTE3 (inst1);
+ output = frag_more (isize);
+ }
+ inst |= (reg1 << RD_LOW) & RD_MASK;
+ inst |= (immed << IMM_LOW) & IMM_MASK;
+ }
+ else
+ {
temp = immed & 0xFFFF8000;
if ((temp != 0) && (temp != 0xFFFF8000))
@@ -1844,6 +1884,7 @@ md_assemble (char * str)
inst |= (reg1 << RD_LOW) & RD_MASK;
inst |= (immed << IMM_LOW) & IMM_MASK;
+ }
break;
case INST_TYPE_R2:
@@ -3090,10 +3131,10 @@ cons_fix_new_microblaze (fragS * frag,
r = BFD_RELOC_32;
break;
case 8:
- /*if (microblaze_arch_size == 64)
- r = BFD_RELOC_32;
- else*/
+ if (microblaze_arch_size == 64)
r = BFD_RELOC_MICROBLAZE_EA64;
+ else
+ r = BFD_RELOC_64;
break;
default:
as_bad (_("unsupported BFD relocation size %u"), size);
--
2.37.1 (Apple Git-137.1)
|
