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author | Adrian Dudau <adrian.dudau@enea.com> | 2014-06-26 14:29:42 +0200 |
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committer | Adrian Dudau <adrian.dudau@enea.com> | 2014-06-26 14:29:42 +0200 |
commit | 99ac0639fff61cbdcfe58668eb9b0083d624504f (patch) | |
tree | f9142a48899bace9dda4f48c80e9a6f4b123c504 /recipes-devtools/gcc/files/0002-Patch-microblaze-Add-4-byte-implementation-for-atomi.patch | |
download | meta-xilinx-99ac0639fff61cbdcfe58668eb9b0083d624504f.tar.gz |
initial commit for Enea Linux 4.0
Migrated from the internal git server on the daisy-enea branch
Signed-off-by: Adrian Dudau <adrian.dudau@enea.com>
Diffstat (limited to 'recipes-devtools/gcc/files/0002-Patch-microblaze-Add-4-byte-implementation-for-atomi.patch')
-rw-r--r-- | recipes-devtools/gcc/files/0002-Patch-microblaze-Add-4-byte-implementation-for-atomi.patch | 157 |
1 files changed, 157 insertions, 0 deletions
diff --git a/recipes-devtools/gcc/files/0002-Patch-microblaze-Add-4-byte-implementation-for-atomi.patch b/recipes-devtools/gcc/files/0002-Patch-microblaze-Add-4-byte-implementation-for-atomi.patch new file mode 100644 index 00000000..aefa13b0 --- /dev/null +++ b/recipes-devtools/gcc/files/0002-Patch-microblaze-Add-4-byte-implementation-for-atomi.patch | |||
@@ -0,0 +1,157 @@ | |||
1 | From: David Holsgrove <david.holsgrove@xilinx.com> | ||
2 | Subject: [PATCH 2/8] [Patch, microblaze]: Add 4 byte implementation for | ||
3 | atomic builtin | ||
4 | |||
5 | By providing this initial atomic implementation, gcc is able to generate the other atomic | ||
6 | builtins by using a __sync_compare_and_swap loop | ||
7 | |||
8 | Add __sync_lock_test_and_set 4 byte atomic builtin | ||
9 | |||
10 | Changelog | ||
11 | |||
12 | 2013-03-18 David Holsgrove <david.holsgrove@xilinx.com> | ||
13 | |||
14 | * gcc/config/microblaze/sync.md: New file. | ||
15 | * gcc/config/microblaze/microblaze.md: Add UNSPEC_SYNC_CAS, | ||
16 | UNSPEC_SYNC_XCHG and include sync.md. | ||
17 | * gcc/config/microblaze/microblaze.c: Add print_operand 'y'. | ||
18 | * gcc/config/microblaze/constraints.md: Add memory_contraint | ||
19 | 'Q' which is a single register. | ||
20 | |||
21 | Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> | ||
22 | Upstream-Status: Pending | ||
23 | |||
24 | diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md | ||
25 | index c6fbc98..c9c1649 100644 | ||
26 | --- a/gcc/config/microblaze/constraints.md | ||
27 | +++ b/gcc/config/microblaze/constraints.md | ||
28 | @@ -70,3 +70,8 @@ | ||
29 | "Double word operand." | ||
30 | (and (match_code "mem") | ||
31 | (match_test "double_memory_operand (op, GET_MODE (op))"))) | ||
32 | + | ||
33 | +(define_memory_constraint "Q" | ||
34 | + "Memory operand which is a single register." | ||
35 | + (and (match_code "mem") | ||
36 | + (match_test "GET_CODE ( XEXP (op, 0)) == REG"))) | ||
37 | diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c | ||
38 | index 5f4bc60..1562e60 100644 | ||
39 | --- a/gcc/config/microblaze/microblaze.c | ||
40 | +++ b/gcc/config/microblaze/microblaze.c | ||
41 | @@ -2130,6 +2130,7 @@ microblaze_initial_elimination_offset (int from, int to) | ||
42 | 't' print 't' for EQ, 'f' for NE | ||
43 | 'm' Print 1<<operand. | ||
44 | 'i' Print 'i' if MEM operand has immediate value | ||
45 | + 'y' Print 'y' if MEM operand is single register | ||
46 | 'o' Print operand address+4 | ||
47 | '?' Print 'd' if we use a branch with delay slot instead of normal branch. | ||
48 | 'h' Print high word of const_double (int or float) value as hex | ||
49 | @@ -2300,6 +2301,15 @@ print_operand (FILE * file, rtx op, int letter) | ||
50 | rtx op4 = adjust_address (op, GET_MODE (op), 4); | ||
51 | output_address (XEXP (op4, 0)); | ||
52 | } | ||
53 | + else if (letter == 'y') | ||
54 | + { | ||
55 | + rtx mem_reg = XEXP (op, 0); | ||
56 | + if (GET_CODE (mem_reg) == REG) | ||
57 | + { | ||
58 | + register int regnum = REGNO (mem_reg); | ||
59 | + fprintf (file, "%s", reg_names[regnum]); | ||
60 | + } | ||
61 | + } | ||
62 | else | ||
63 | output_address (XEXP (op, 0)); | ||
64 | |||
65 | diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md | ||
66 | index 4e7fe3b..55cc730 100644 | ||
67 | --- a/gcc/config/microblaze/microblaze.md | ||
68 | +++ b/gcc/config/microblaze/microblaze.md | ||
69 | @@ -41,6 +41,8 @@ | ||
70 | (UNSPEC_CMP 104) ;; signed compare | ||
71 | (UNSPEC_CMPU 105) ;; unsigned compare | ||
72 | (UNSPEC_TLS 106) ;; jump table | ||
73 | + (UNSPEC_SYNC_CAS 107) ;; Represent atomic compare swap. | ||
74 | + (UNSPEC_SYNC_XCHG 108) ;; Represent atomic exchange. | ||
75 | ]) | ||
76 | |||
77 | |||
78 | @@ -2231,3 +2233,5 @@ | ||
79 | microblaze_eh_return(operands[0]); | ||
80 | DONE; | ||
81 | }") | ||
82 | + | ||
83 | +(include "sync.md") | ||
84 | diff --git a/gcc/config/microblaze/sync.md b/gcc/config/microblaze/sync.md | ||
85 | new file mode 100644 | ||
86 | index 0000000..0923825 | ||
87 | --- /dev/null | ||
88 | +++ b/gcc/config/microblaze/sync.md | ||
89 | @@ -0,0 +1,65 @@ | ||
90 | +;; Machine description for Xilinx MicroBlaze synchronization instructions. | ||
91 | +;; Copyright (C) 2011, 2012 | ||
92 | +;; Free Software Foundation, Inc. | ||
93 | +;; | ||
94 | +;; This file is part of GCC. | ||
95 | +;; | ||
96 | +;; GCC is free software; you can redistribute it and/or modify | ||
97 | +;; it under the terms of the GNU General Public License as published by | ||
98 | +;; the Free Software Foundation; either version 3, or (at your option) | ||
99 | +;; any later version. | ||
100 | +;; | ||
101 | +;; GCC is distributed in the hope that it will be useful, | ||
102 | +;; but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
103 | +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
104 | +;; GNU General Public License for more details. | ||
105 | +;; | ||
106 | +;; You should have received a copy of the GNU General Public License | ||
107 | +;; along with GCC; see the file COPYING3. If not see | ||
108 | +;; <http://www.gnu.org/licenses/>. | ||
109 | + | ||
110 | + | ||
111 | +(define_insn "sync_compare_and_swapsi" | ||
112 | + [(set (match_operand:SI 0 "register_operand" "=&d") ;; retval | ||
113 | + (match_operand:SI 1 "nonimmediate_operand" "+Q")) ;; mem | ||
114 | + (set (match_dup 1) | ||
115 | + (unspec | ||
116 | + [(match_operand:SI 2 "register_operand" "d") ;; oldval | ||
117 | + (match_operand:SI 3 "register_operand" "d")] ;; newval | ||
118 | + UNSPEC_SYNC_CAS)) | ||
119 | + (clobber (match_scratch:SI 4 "=&d"))] ;; scratch | ||
120 | + "" | ||
121 | + { | ||
122 | + output_asm_insn ("addc \tr0,r0,r0", operands); | ||
123 | + output_asm_insn ("lwx \t%0,%y1,r0", operands); | ||
124 | + output_asm_insn ("addic\t%4,r0,0", operands); | ||
125 | + output_asm_insn ("bnei \t%4,.-8", operands); | ||
126 | + output_asm_insn ("cmp \t%4,%0,%2", operands); | ||
127 | + output_asm_insn ("bnei \t%4,.+16", operands); | ||
128 | + output_asm_insn ("swx \t%3,%y1,r0", operands); | ||
129 | + output_asm_insn ("addic\t%4,r0,0", operands); | ||
130 | + output_asm_insn ("bnei \t%4,.-28", operands); | ||
131 | + return ""; | ||
132 | + } | ||
133 | +) | ||
134 | + | ||
135 | +(define_insn "sync_test_and_setsi" | ||
136 | + [(set (match_operand:SI 0 "register_operand" "=&d") ;; retval | ||
137 | + (match_operand:SI 1 "nonimmediate_operand" "+Q")) ;; mem | ||
138 | + (set (match_dup 1) | ||
139 | + (unspec | ||
140 | + [(match_operand:SI 2 "register_operand" "d")] ;; value | ||
141 | + UNSPEC_SYNC_XCHG)) | ||
142 | + (clobber (match_scratch:SI 3 "=&d"))] ;; scratch | ||
143 | + "" | ||
144 | + { | ||
145 | + output_asm_insn ("addc \tr0,r0,r0", operands); | ||
146 | + output_asm_insn ("lwx \t%0,%y1,r0", operands); | ||
147 | + output_asm_insn ("addic\t%3,r0,0", operands); | ||
148 | + output_asm_insn ("bnei \t%3,.-8", operands); | ||
149 | + output_asm_insn ("swx \t%2,%y1,r0", operands); | ||
150 | + output_asm_insn ("addic\t%3,r0,0", operands); | ||
151 | + output_asm_insn ("bnei \t%3,.-20", operands); | ||
152 | + return ""; | ||
153 | + } | ||
154 | +) | ||
155 | -- | ||
156 | 1.7.5.4 | ||
157 | |||