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authorMark Hatle <mark.hatle@amd.com>2023-10-23 08:51:20 -0600
committerMark Hatle <mark.hatle@amd.com>2023-10-23 08:56:37 -0600
commiteb42c7caeac33f42096673522e650441f05ca8da (patch)
tree33f97fe41ec8855cf591c2692c7c7038b6bc1ae3 /meta-xilinx-core/recipes-bsp/bootbin/xilinx-bootbin_1.0.bb
parent387b31acf85b84bd34f339c87c0b51a9af4e16e4 (diff)
parent05911e19d85fd98c42054238392afe95a5125265 (diff)
downloadmeta-xilinx-eb42c7caeac33f42096673522e650441f05ca8da.tar.gz
Merge remote-tracking branch 'origin/rel-v2023.2' into nanbield
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
Diffstat (limited to 'meta-xilinx-core/recipes-bsp/bootbin/xilinx-bootbin_1.0.bb')
-rw-r--r--meta-xilinx-core/recipes-bsp/bootbin/xilinx-bootbin_1.0.bb21
1 files changed, 17 insertions, 4 deletions
diff --git a/meta-xilinx-core/recipes-bsp/bootbin/xilinx-bootbin_1.0.bb b/meta-xilinx-core/recipes-bsp/bootbin/xilinx-bootbin_1.0.bb
index 5133fbd8..4c8bfa0e 100644
--- a/meta-xilinx-core/recipes-bsp/bootbin/xilinx-bootbin_1.0.bb
+++ b/meta-xilinx-core/recipes-bsp/bootbin/xilinx-bootbin_1.0.bb
@@ -44,6 +44,10 @@ BOOTGEN_EXTRA_ARGS ?= ""
44do_patch[noexec] = "1" 44do_patch[noexec] = "1"
45 45
46def create_bif(config, attrflags, attrimage, ids, common_attr, biffd, d): 46def create_bif(config, attrflags, attrimage, ids, common_attr, biffd, d):
47 arch = d.getVar("SOC_FAMILY")
48 bb.error("create_bif function not defined for arch: %s" % (arch))
49
50def create_zynq_bif(config, attrflags, attrimage, ids, common_attr, biffd, d):
47 import re, os 51 import re, os
48 for cfg in config: 52 for cfg in config:
49 if cfg not in attrflags and common_attr: 53 if cfg not in attrflags and common_attr:
@@ -117,23 +121,32 @@ def create_versal_bif(config, attrflags, attrimage, ids, common_attr, biffd, d):
117python do_configure() { 121python do_configure() {
118 fp = d.getVar("BIF_FILE_PATH") 122 fp = d.getVar("BIF_FILE_PATH")
119 if fp == (d.getVar('B') + '/bootgen.bif'): 123 if fp == (d.getVar('B') + '/bootgen.bif'):
120 arch = d.getVar("SOC_FAMILY")
121 biffunc = {'versal':create_versal_bif, 'zynq':create_bif, 'zynqmp':create_bif}
122 biffd = open(fp, 'w') 124 biffd = open(fp, 'w')
123 biffd.write("the_ROM_image:\n") 125 biffd.write("the_ROM_image:\n")
124 biffd.write("{\n") 126 biffd.write("{\n")
125 127
128 arch = d.getVar("SOC_FAMILY")
126 bifattr = (d.getVar("BIF_COMMON_ATTR") or "").split() 129 bifattr = (d.getVar("BIF_COMMON_ATTR") or "").split()
127 if bifattr: 130 if bifattr:
128 attrflags = d.getVarFlags("BIF_COMMON_ATTR") or {} 131 attrflags = d.getVarFlags("BIF_COMMON_ATTR") or {}
129 biffunc[arch](bifattr, attrflags,'','', 1, biffd, d) 132 if arch in ['zynq', 'zynqmp']:
133 create_zynq_bif(bifattr, attrflags,'','', 1, biffd, d)
134 elif arch in ['versal']:
135 create_versal_bif(bifattr, attrflags,'','', 1, biffd, d)
136 else:
137 create_bif(bifattr, attrflags,'','', 1, biffd, d)
130 138
131 bifpartition = (d.getVar("BIF_PARTITION_ATTR") or "").split() 139 bifpartition = (d.getVar("BIF_PARTITION_ATTR") or "").split()
132 if bifpartition: 140 if bifpartition:
133 attrflags = d.getVarFlags("BIF_PARTITION_ATTR") or {} 141 attrflags = d.getVarFlags("BIF_PARTITION_ATTR") or {}
134 attrimage = d.getVarFlags("BIF_PARTITION_IMAGE") or {} 142 attrimage = d.getVarFlags("BIF_PARTITION_IMAGE") or {}
135 ids = d.getVarFlags("BIF_PARTITION_ID") or {} 143 ids = d.getVarFlags("BIF_PARTITION_ID") or {}
136 biffunc[arch](bifpartition, attrflags, attrimage, ids, 0, biffd, d) 144 if arch in ['zynq', 'zynqmp']:
145 create_zynq_bif(bifpartition, attrflags, attrimage, ids, 0, biffd, d)
146 elif arch in ['versal']:
147 create_versal_bif(bifpartition, attrflags, attrimage, ids, 0, biffd, d)
148 else:
149 create_bif(bifpartition, attrflags, attrimage, ids, 0, biffd, d)
137 150
138 biffd.write("}") 151 biffd.write("}")
139 biffd.close() 152 biffd.close()