diff options
Diffstat (limited to 'recipes-kernel/linux/linux-3.0/bias/0001-OMAP3630-PRM-add-ABB-PRM-register-definitions.patch')
-rw-r--r-- | recipes-kernel/linux/linux-3.0/bias/0001-OMAP3630-PRM-add-ABB-PRM-register-definitions.patch | 93 |
1 files changed, 0 insertions, 93 deletions
diff --git a/recipes-kernel/linux/linux-3.0/bias/0001-OMAP3630-PRM-add-ABB-PRM-register-definitions.patch b/recipes-kernel/linux/linux-3.0/bias/0001-OMAP3630-PRM-add-ABB-PRM-register-definitions.patch deleted file mode 100644 index 8dd595a8..00000000 --- a/recipes-kernel/linux/linux-3.0/bias/0001-OMAP3630-PRM-add-ABB-PRM-register-definitions.patch +++ /dev/null | |||
@@ -1,93 +0,0 @@ | |||
1 | From 2deaccf427c0fa1e87ed764877c03c2b1ba9b913 Mon Sep 17 00:00:00 2001 | ||
2 | From: Mike Turquette <mturquette@ti.com> | ||
3 | Date: Wed, 29 Jun 2011 17:25:53 -0700 | ||
4 | Subject: [PATCH 1/8] OMAP3630: PRM: add ABB PRM register definitions | ||
5 | |||
6 | OMAP3630 supports an Adaptive Body-Bias ldo as well as some MPU interrupts | ||
7 | related to voltage control that are not present on OMAP34XX. This patch | ||
8 | adds the offsets, register addresses, bitfield shifts and masks to support | ||
9 | this feature. | ||
10 | |||
11 | Signed-off-by: Mike Turquette <mturquette@ti.com> | ||
12 | --- | ||
13 | arch/arm/mach-omap2/prm-regbits-34xx.h | 34 ++++++++++++++++++++++++++++++++ | ||
14 | arch/arm/mach-omap2/prm2xxx_3xxx.h | 4 +++ | ||
15 | 2 files changed, 38 insertions(+), 0 deletions(-) | ||
16 | |||
17 | diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h | ||
18 | index 64c087a..0309ff6 100644 | ||
19 | --- a/arch/arm/mach-omap2/prm-regbits-34xx.h | ||
20 | +++ b/arch/arm/mach-omap2/prm-regbits-34xx.h | ||
21 | @@ -216,6 +216,12 @@ | ||
22 | /* PRM_SYSCONFIG specific bits */ | ||
23 | |||
24 | /* PRM_IRQSTATUS_MPU specific bits */ | ||
25 | +#define OMAP3630_VC_BYPASS_ACK_ST_SHIFT 28 | ||
26 | +#define OMAP3630_VC_BYPASS_ACK_ST_MASK (1 << 28) | ||
27 | +#define OMAP3630_VC_VP1_ACK_ST_SHIFT 27 | ||
28 | +#define OMAP3630_VC_VP1_ACK_ST_MASK (1 << 27) | ||
29 | +#define OMAP3630_ABB_LDO_TRANXDONE_ST_SHIFT 26 | ||
30 | +#define OMAP3630_ABB_LDO_TRANXDONE_ST_MASK (1 << 26) | ||
31 | #define OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT 25 | ||
32 | #define OMAP3430ES2_SND_PERIPH_DPLL_ST_MASK (1 << 25) | ||
33 | #define OMAP3430_VC_TIMEOUTERR_ST_MASK (1 << 24) | ||
34 | @@ -248,6 +254,12 @@ | ||
35 | #define OMAP3430_FS_USB_WKUP_ST_MASK (1 << 1) | ||
36 | |||
37 | /* PRM_IRQENABLE_MPU specific bits */ | ||
38 | +#define OMAP3630_VC_BYPASS_ACK_EN_SHIFT 28 | ||
39 | +#define OMAP3630_VC_BYPASS_ACK_EN_MASK (1 << 28) | ||
40 | +#define OMAP3630_VC_VP1_ACK_EN_SHIFT 27 | ||
41 | +#define OMAP3630_VC_VP1_ACK_EN_MASK (1 << 27) | ||
42 | +#define OMAP3630_ABB_LDO_TRANXDONE_EN_SHIFT 26 | ||
43 | +#define OMAP3630_ABB_LDO_TRANXDONE_EN_MASK (1 << 26) | ||
44 | #define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT 25 | ||
45 | #define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_MASK (1 << 25) | ||
46 | #define OMAP3430_VC_TIMEOUTERR_EN_MASK (1 << 24) | ||
47 | @@ -587,6 +599,28 @@ | ||
48 | |||
49 | /* PRM_VP2_STATUS specific bits */ | ||
50 | |||
51 | +/* PRM_LDO_ABB_SETUP specific bits */ | ||
52 | +#define OMAP3630_SR2_IN_TRANSITION_SHIFT 6 | ||
53 | +#define OMAP3630_SR2_IN_TRANSITION_MASK (1 << 6) | ||
54 | +#define OMAP3630_SR2_STATUS_SHIFT 3 | ||
55 | +#define OMAP3630_SR2_STATUS_MASK (3 << 3) | ||
56 | +#define OMAP3630_OPP_CHANGE_SHIFT 2 | ||
57 | +#define OMAP3630_OPP_CHANGE_MASK (1 << 2) | ||
58 | +#define OMAP3630_OPP_SEL_SHIFT 0 | ||
59 | +#define OMAP3630_OPP_SEL_MASK (3 << 0) | ||
60 | + | ||
61 | +/* PRM_LDO_ABB_CTRL specific bits */ | ||
62 | +#define OMAP3630_SR2_WTCNT_VALUE_SHIFT 8 | ||
63 | +#define OMAP3630_SR2_WTCNT_VALUE_MASK (0xff << 8) | ||
64 | +#define OMAP3630_SLEEP_RBB_SEL_SHIFT 3 | ||
65 | +#define OMAP3630_SLEEP_RBB_SEL_MASK (1 << 3) | ||
66 | +#define OMAP3630_ACTIVE_FBB_SEL_SHIFT 2 | ||
67 | +#define OMAP3630_ACTIVE_FBB_SEL_MASK (1 << 2) | ||
68 | +#define OMAP3630_ACTIVE_RBB_SEL_SHIFT 1 | ||
69 | +#define OMAP3630_ACTIVE_RBB_SEL_MASK (1 << 1) | ||
70 | +#define OMAP3630_SR2EN_SHIFT 0 | ||
71 | +#define OMAP3630_SR2EN_MASK (1 << 0) | ||
72 | + | ||
73 | /* RM_RSTST_NEON specific bits */ | ||
74 | |||
75 | /* PM_WKDEP_NEON specific bits */ | ||
76 | diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h | ||
77 | index cef533d..408d1c7 100644 | ||
78 | --- a/arch/arm/mach-omap2/prm2xxx_3xxx.h | ||
79 | +++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h | ||
80 | @@ -167,6 +167,10 @@ | ||
81 | #define OMAP3430_PRM_VP2_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0) | ||
82 | #define OMAP3_PRM_VP2_STATUS_OFFSET 0x00e4 | ||
83 | #define OMAP3430_PRM_VP2_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4) | ||
84 | +#define OMAP3_PRM_LDO_ABB_SETUP_OFFSET 0x00f0 | ||
85 | +#define OMAP3630_PRM_LDO_ABB_SETUP OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00f0) | ||
86 | +#define OMAP3_PRM_LDO_ABB_CTRL_OFFSET 0x00f4 | ||
87 | +#define OMAP3630_PRM_LDO_ABB_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00f4) | ||
88 | |||
89 | #define OMAP3_PRM_CLKSEL_OFFSET 0x0040 | ||
90 | #define OMAP3430_PRM_CLKSEL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040) | ||
91 | -- | ||
92 | 1.6.6.1 | ||
93 | |||