diff options
Diffstat (limited to 'recipes-bsp/u-boot')
18 files changed, 187 insertions, 198 deletions
diff --git a/recipes-bsp/u-boot/files/v2019.07/0001-ARM-socfpga-stratix10-Enable-PSCI-system-reset.patch b/recipes-bsp/u-boot/files/v2019.07/0001-ARM-socfpga-stratix10-Enable-PSCI-system-reset.patch index a4b7857..0b4fec1 100644 --- a/recipes-bsp/u-boot/files/v2019.07/0001-ARM-socfpga-stratix10-Enable-PSCI-system-reset.patch +++ b/recipes-bsp/u-boot/files/v2019.07/0001-ARM-socfpga-stratix10-Enable-PSCI-system-reset.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From 97f599b2a7b34d17067b4ccf6c468cdcc6805349 Mon Sep 17 00:00:00 2001 | 1 | From 5534368e77a2bfcb366eb158c72a751c28e377a7 Mon Sep 17 00:00:00 2001 |
2 | From: "Ang, Chee Hong" <chee.hong.ang@intel.com> | 2 | From: "Ang, Chee Hong" <chee.hong.ang@intel.com> |
3 | Date: Mon, 29 Apr 2019 23:35:30 -0700 | 3 | Date: Mon, 29 Apr 2019 23:35:30 -0700 |
4 | Subject: [PATCH 01/12] ARM: socfpga: stratix10: Enable PSCI system reset | 4 | Subject: [PATCH 01/14] ARM: socfpga: stratix10: Enable PSCI system reset |
5 | 5 | ||
6 | Enable psci_system_reset support for Stratix10. This PSCI function | 6 | Enable psci_system_reset support for Stratix10. This PSCI function |
7 | will eventually trigger the mailbox HPS_REBOOT to SDM. | 7 | will eventually trigger the mailbox HPS_REBOOT to SDM. |
diff --git a/recipes-bsp/u-boot/files/v2019.07/0002-ARM-socfpga-stratix10-Enable-PSCI-CPU_ON.patch b/recipes-bsp/u-boot/files/v2019.07/0002-ARM-socfpga-stratix10-Enable-PSCI-CPU_ON.patch index ebf6fe7..05d1e91 100644 --- a/recipes-bsp/u-boot/files/v2019.07/0002-ARM-socfpga-stratix10-Enable-PSCI-CPU_ON.patch +++ b/recipes-bsp/u-boot/files/v2019.07/0002-ARM-socfpga-stratix10-Enable-PSCI-CPU_ON.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From 257cff780ec1a50600a77cf361df27746801d684 Mon Sep 17 00:00:00 2001 | 1 | From 0d6fb850e5662ade636b0c7aa96de9d6ed653310 Mon Sep 17 00:00:00 2001 |
2 | From: "Ang, Chee Hong" <chee.hong.ang@intel.com> | 2 | From: "Ang, Chee Hong" <chee.hong.ang@intel.com> |
3 | Date: Mon, 14 Jan 2019 01:07:50 -0800 | 3 | Date: Mon, 14 Jan 2019 01:07:50 -0800 |
4 | Subject: [PATCH 02/12] ARM: socfpga: stratix10: Enable PSCI CPU_ON | 4 | Subject: [PATCH 02/14] ARM: socfpga: stratix10: Enable PSCI CPU_ON |
5 | 5 | ||
6 | Enable psci_cpu_on support for Stratix10. This PSCI function | 6 | Enable psci_cpu_on support for Stratix10. This PSCI function |
7 | will pass the cpu release address for CPU1-CPU3. Then send event | 7 | will pass the cpu release address for CPU1-CPU3. Then send event |
diff --git a/recipes-bsp/u-boot/files/v2019.07/0003-ARM-socfpga-stratix10-Enable-PSCI-support-for-Strati.patch b/recipes-bsp/u-boot/files/v2019.07/0003-ARM-socfpga-stratix10-Enable-PSCI-support-for-Strati.patch index ed60cc0..9b92117 100644 --- a/recipes-bsp/u-boot/files/v2019.07/0003-ARM-socfpga-stratix10-Enable-PSCI-support-for-Strati.patch +++ b/recipes-bsp/u-boot/files/v2019.07/0003-ARM-socfpga-stratix10-Enable-PSCI-support-for-Strati.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From 504f8bd14f703bfb2ffd5dccac7126d5fd22e0d1 Mon Sep 17 00:00:00 2001 | 1 | From d58eacb640040fc19b0939f4398829fa43e5601e Mon Sep 17 00:00:00 2001 |
2 | From: "Ang, Chee Hong" <chee.hong.ang@intel.com> | 2 | From: "Ang, Chee Hong" <chee.hong.ang@intel.com> |
3 | Date: Mon, 29 Apr 2019 23:18:38 -0700 | 3 | Date: Mon, 29 Apr 2019 23:18:38 -0700 |
4 | Subject: [PATCH 03/12] ARM: socfpga: stratix10: Enable PSCI support for | 4 | Subject: [PATCH 03/14] ARM: socfpga: stratix10: Enable PSCI support for |
5 | Stratix 10 | 5 | Stratix 10 |
6 | 6 | ||
7 | The address of PSCI text, data and stack sections start at | 7 | The address of PSCI text, data and stack sections start at |
@@ -13,10 +13,10 @@ Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com> | |||
13 | 1 file changed, 8 insertions(+), 1 deletion(-) | 13 | 1 file changed, 8 insertions(+), 1 deletion(-) |
14 | 14 | ||
15 | diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig | 15 | diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig |
16 | index 48f02f08d4..755bab5dd2 100644 | 16 | index 1d914648e3..dc4cba67ab 100644 |
17 | --- a/arch/arm/mach-socfpga/Kconfig | 17 | --- a/arch/arm/mach-socfpga/Kconfig |
18 | +++ b/arch/arm/mach-socfpga/Kconfig | 18 | +++ b/arch/arm/mach-socfpga/Kconfig |
19 | @@ -12,6 +12,12 @@ config SPL_SYS_MALLOC_F_LEN | 19 | @@ -18,6 +18,12 @@ config SPL_SYS_MALLOC_F_LEN |
20 | config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE | 20 | config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE |
21 | default 0xa2 | 21 | default 0xa2 |
22 | 22 | ||
@@ -29,7 +29,7 @@ index 48f02f08d4..755bab5dd2 100644 | |||
29 | config SYS_MALLOC_F_LEN | 29 | config SYS_MALLOC_F_LEN |
30 | default 0x2000 if TARGET_SOCFPGA_ARRIA10 | 30 | default 0x2000 if TARGET_SOCFPGA_ARRIA10 |
31 | default 0x2000 if TARGET_SOCFPGA_GEN5 | 31 | default 0x2000 if TARGET_SOCFPGA_GEN5 |
32 | @@ -56,8 +62,9 @@ config TARGET_SOCFPGA_GEN5 | 32 | @@ -64,8 +70,9 @@ config TARGET_SOCFPGA_GEN5 |
33 | config TARGET_SOCFPGA_STRATIX10 | 33 | config TARGET_SOCFPGA_STRATIX10 |
34 | bool | 34 | bool |
35 | select ARMV8_MULTIENTRY | 35 | select ARMV8_MULTIENTRY |
diff --git a/recipes-bsp/u-boot/files/v2019.07/0004-ARM-socfpga-stratix10-Enable-SMC-PSCI-calls-from-sla.patch b/recipes-bsp/u-boot/files/v2019.07/0004-ARM-socfpga-stratix10-Enable-SMC-PSCI-calls-from-sla.patch index 7d30706..55a9805 100644 --- a/recipes-bsp/u-boot/files/v2019.07/0004-ARM-socfpga-stratix10-Enable-SMC-PSCI-calls-from-sla.patch +++ b/recipes-bsp/u-boot/files/v2019.07/0004-ARM-socfpga-stratix10-Enable-SMC-PSCI-calls-from-sla.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From a859bc214aa913be022a7aa8f03723079a325b07 Mon Sep 17 00:00:00 2001 | 1 | From d6ac4f9f2756a14021f9cdc3c3305f950643d45f Mon Sep 17 00:00:00 2001 |
2 | From: Chee Hong Ang <chee.hong.ang@intel.com> | 2 | From: Chee Hong Ang <chee.hong.ang@intel.com> |
3 | Date: Fri, 20 Apr 2018 18:28:07 +0800 | 3 | Date: Fri, 20 Apr 2018 18:28:07 +0800 |
4 | Subject: [PATCH 04/12] ARM: socfpga: stratix10: Enable SMC/PSCI calls from | 4 | Subject: [PATCH 04/14] ARM: socfpga: stratix10: Enable SMC/PSCI calls from |
5 | slave CPUs | 5 | slave CPUs |
6 | 6 | ||
7 | Before this patch, only master CPU (CPU0) is able to | 7 | Before this patch, only master CPU (CPU0) is able to |
diff --git a/recipes-bsp/u-boot/files/v2019.07/0005-ARM-socfpga-stratix10-Add-SOCFPGA-bridges-reset-supp.patch b/recipes-bsp/u-boot/files/v2019.07/0005-ARM-socfpga-stratix10-Add-SOCFPGA-bridges-reset-supp.patch index fd43dd2..a6c2b2a 100644 --- a/recipes-bsp/u-boot/files/v2019.07/0005-ARM-socfpga-stratix10-Add-SOCFPGA-bridges-reset-supp.patch +++ b/recipes-bsp/u-boot/files/v2019.07/0005-ARM-socfpga-stratix10-Add-SOCFPGA-bridges-reset-supp.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From 16460c05fe576050cf485282151fd5623d6e862a Mon Sep 17 00:00:00 2001 | 1 | From 97cae73c90b57bbcf2b422ff142a3c9de6e9ea66 Mon Sep 17 00:00:00 2001 |
2 | From: Dalon Westergreen <dalon.westergreen@intel.com> | 2 | From: Dalon Westergreen <dalon.westergreen@intel.com> |
3 | Date: Wed, 22 May 2019 17:05:12 -0700 | 3 | Date: Wed, 22 May 2019 17:05:12 -0700 |
4 | Subject: [PATCH 05/12] ARM: socfpga: stratix10: Add SOCFPGA bridges reset | 4 | Subject: [PATCH 05/14] ARM: socfpga: stratix10: Add SOCFPGA bridges reset |
5 | support for PSCI call | 5 | support for PSCI call |
6 | 6 | ||
7 | Add SOCFPGA bridges reset support for FPGA configuration SMC services | 7 | Add SOCFPGA bridges reset support for FPGA configuration SMC services |
diff --git a/recipes-bsp/u-boot/files/v2019.07/0006-ARM-socfpga-stratix10-Add-Stratix10-FPGA-configurati.patch b/recipes-bsp/u-boot/files/v2019.07/0006-ARM-socfpga-stratix10-Add-Stratix10-FPGA-configurati.patch index cc0be27..5f58e52 100644 --- a/recipes-bsp/u-boot/files/v2019.07/0006-ARM-socfpga-stratix10-Add-Stratix10-FPGA-configurati.patch +++ b/recipes-bsp/u-boot/files/v2019.07/0006-ARM-socfpga-stratix10-Add-Stratix10-FPGA-configurati.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From 04187fba93e6d359ebb4dd8e397dff282f53ec5a Mon Sep 17 00:00:00 2001 | 1 | From 97b805b19ed529f389bf5899fbe1d99bd13ffd59 Mon Sep 17 00:00:00 2001 |
2 | From: "Ang, Chee Hong" <chee.hong.ang@intel.com> | 2 | From: "Ang, Chee Hong" <chee.hong.ang@intel.com> |
3 | Date: Mon, 29 Apr 2019 23:42:39 -0700 | 3 | Date: Mon, 29 Apr 2019 23:42:39 -0700 |
4 | Subject: [PATCH 06/12] ARM: socfpga: stratix10: Add Stratix10 FPGA | 4 | Subject: [PATCH 06/14] ARM: socfpga: stratix10: Add Stratix10 FPGA |
5 | configuration PSCI services | 5 | configuration PSCI services |
6 | 6 | ||
7 | Allow PSCI layer to handle the S10 FPGA configuration (SiP) service | 7 | Allow PSCI layer to handle the S10 FPGA configuration (SiP) service |
diff --git a/recipes-bsp/u-boot/files/v2019.07/0007-mmc-dwmmc-Enable-small-delay-before-returning-error.patch b/recipes-bsp/u-boot/files/v2019.07/0007-mmc-dwmmc-Enable-small-delay-before-returning-error.patch index 8da5892..71625cd 100644 --- a/recipes-bsp/u-boot/files/v2019.07/0007-mmc-dwmmc-Enable-small-delay-before-returning-error.patch +++ b/recipes-bsp/u-boot/files/v2019.07/0007-mmc-dwmmc-Enable-small-delay-before-returning-error.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From 17366d3b46cf70a8fa4d807519790ef4b1b03772 Mon Sep 17 00:00:00 2001 | 1 | From 5dd98b8e0aec2059863ae73d5c83fa043b0a6170 Mon Sep 17 00:00:00 2001 |
2 | From: "Ang, Chee Hong" <chee.hong.ang@intel.com> | 2 | From: "Ang, Chee Hong" <chee.hong.ang@intel.com> |
3 | Date: Wed, 30 Jan 2019 21:47:36 -0800 | 3 | Date: Wed, 30 Jan 2019 21:47:36 -0800 |
4 | Subject: [PATCH 07/12] mmc: dwmmc: Enable small delay before returning error | 4 | Subject: [PATCH 07/14] mmc: dwmmc: Enable small delay before returning error |
5 | 5 | ||
6 | 'SET_BLOCKLEN' may occasionally fail on first attempt. | 6 | 'SET_BLOCKLEN' may occasionally fail on first attempt. |
7 | This patch enable a small delay in dwmci_send_cmd() on | 7 | This patch enable a small delay in dwmci_send_cmd() on |
diff --git a/recipes-bsp/u-boot/files/v2019.07/0008-ARM-socfpga-stratix10-Enable-DMA330-DMA-controller.patch b/recipes-bsp/u-boot/files/v2019.07/0008-ARM-socfpga-stratix10-Enable-DMA330-DMA-controller.patch index 91505b7..8e0e907 100644 --- a/recipes-bsp/u-boot/files/v2019.07/0008-ARM-socfpga-stratix10-Enable-DMA330-DMA-controller.patch +++ b/recipes-bsp/u-boot/files/v2019.07/0008-ARM-socfpga-stratix10-Enable-DMA330-DMA-controller.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From da0bd33c8c8f6a1b77ecaa4c676f8ee14997b9e9 Mon Sep 17 00:00:00 2001 | 1 | From f4e6b02369f2a7daed5799f27e29198714bda848 Mon Sep 17 00:00:00 2001 |
2 | From: "Ang, Chee Hong" <chee.hong.ang@intel.com> | 2 | From: "Ang, Chee Hong" <chee.hong.ang@intel.com> |
3 | Date: Wed, 30 Jan 2019 21:29:09 -0800 | 3 | Date: Wed, 30 Jan 2019 21:29:09 -0800 |
4 | Subject: [PATCH 08/12] ARM: socfpga: stratix10: Enable DMA330 DMA controller | 4 | Subject: [PATCH 08/14] ARM: socfpga: stratix10: Enable DMA330 DMA controller |
5 | 5 | ||
6 | Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com> | 6 | Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com> |
7 | --- | 7 | --- |
diff --git a/recipes-bsp/u-boot/files/v2019.07/0009-ARM-socfpga-Stratix10-Fix-el3_exception_vectors-relo.patch b/recipes-bsp/u-boot/files/v2019.07/0009-ARM-socfpga-Stratix10-Fix-el3_exception_vectors-relo.patch index 54fa812..fb060bb 100644 --- a/recipes-bsp/u-boot/files/v2019.07/0009-ARM-socfpga-Stratix10-Fix-el3_exception_vectors-relo.patch +++ b/recipes-bsp/u-boot/files/v2019.07/0009-ARM-socfpga-Stratix10-Fix-el3_exception_vectors-relo.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From 8569e08a1a4b3bd810f60083058053a39b27534e Mon Sep 17 00:00:00 2001 | 1 | From b4807003314579b069877df69eefbace4c7b6efa Mon Sep 17 00:00:00 2001 |
2 | From: Chee Hong Ang <chee.hong.ang@intel.com> | 2 | From: Chee Hong Ang <chee.hong.ang@intel.com> |
3 | Date: Sat, 18 May 2019 16:42:10 +0800 | 3 | Date: Sat, 18 May 2019 16:42:10 +0800 |
4 | Subject: [PATCH 09/12] ARM: socfpga: Stratix10: Fix el3_exception_vectors | 4 | Subject: [PATCH 09/14] ARM: socfpga: Stratix10: Fix el3_exception_vectors |
5 | relocation issue | 5 | relocation issue |
6 | 6 | ||
7 | New toolchain has issue relocating the 32-bit pointer to address of | 7 | New toolchain has issue relocating the 32-bit pointer to address of |
diff --git a/recipes-bsp/u-boot/files/v2019.07/0001-ARM-socfpga-Stratix10-Disable-CONFIG_PSCI_RESET.patch b/recipes-bsp/u-boot/files/v2019.07/0010-ARM-socfpga-Stratix10-Disable-CONFIG_PSCI_RESET.patch index e954ac0..030c38b 100644 --- a/recipes-bsp/u-boot/files/v2019.07/0001-ARM-socfpga-Stratix10-Disable-CONFIG_PSCI_RESET.patch +++ b/recipes-bsp/u-boot/files/v2019.07/0010-ARM-socfpga-Stratix10-Disable-CONFIG_PSCI_RESET.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From 45dd1ac82881153c73bd4243cd20f3b13955ad21 Mon Sep 17 00:00:00 2001 | 1 | From 31bb5e5583e87e5bc6d7daa3647891374eec708b Mon Sep 17 00:00:00 2001 |
2 | From: Chee Hong Ang <chee.hong.ang@intel.com> | 2 | From: Chee Hong Ang <chee.hong.ang@intel.com> |
3 | Date: Sat, 11 May 2019 00:09:46 +0800 | 3 | Date: Sat, 11 May 2019 00:09:46 +0800 |
4 | Subject: [PATCH] ARM: socfpga: Stratix10: Disable CONFIG_PSCI_RESET | 4 | Subject: [PATCH 10/14] ARM: socfpga: Stratix10: Disable CONFIG_PSCI_RESET |
5 | 5 | ||
6 | Avoid invoking 'SYSTEM_RESET' PSCI function because PSCI | 6 | Avoid invoking 'SYSTEM_RESET' PSCI function because PSCI |
7 | function calls are not supported in u-boot running in EL3. | 7 | function calls are not supported in u-boot running in EL3. |
@@ -12,11 +12,11 @@ Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> | |||
12 | 1 file changed, 2 insertions(+), 1 deletion(-) | 12 | 1 file changed, 2 insertions(+), 1 deletion(-) |
13 | 13 | ||
14 | diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig | 14 | diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig |
15 | index 7405c3a4a1..409ee7ada0 100644 | 15 | index 92a2b58ed4..f3683bccb4 100644 |
16 | --- a/arch/arm/cpu/armv8/Kconfig | 16 | --- a/arch/arm/cpu/armv8/Kconfig |
17 | +++ b/arch/arm/cpu/armv8/Kconfig | 17 | +++ b/arch/arm/cpu/armv8/Kconfig |
18 | @@ -108,7 +108,8 @@ config PSCI_RESET | 18 | @@ -110,7 +110,8 @@ config PSCI_RESET |
19 | !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \ | 19 | !TARGET_LS1046AFRWY && \ |
20 | !TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \ | 20 | !TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \ |
21 | !TARGET_LX2160AQDS && \ | 21 | !TARGET_LX2160AQDS && \ |
22 | - !ARCH_UNIPHIER && !TARGET_S32V234EVB | 22 | - !ARCH_UNIPHIER && !TARGET_S32V234EVB |
@@ -26,5 +26,5 @@ index 7405c3a4a1..409ee7ada0 100644 | |||
26 | Most armv8 systems have PSCI support enabled in EL3, either through | 26 | Most armv8 systems have PSCI support enabled in EL3, either through |
27 | ARM Trusted Firmware or other firmware. | 27 | ARM Trusted Firmware or other firmware. |
28 | -- | 28 | -- |
29 | 2.13.0 | 29 | 2.21.0 |
30 | 30 | ||
diff --git a/recipes-bsp/u-boot/files/v2019.07/0010-Makefile-Add-target-to-generate-hex-output-for-combi.patch b/recipes-bsp/u-boot/files/v2019.07/0010-Makefile-Add-target-to-generate-hex-output-for-combi.patch deleted file mode 100644 index 113d767..0000000 --- a/recipes-bsp/u-boot/files/v2019.07/0010-Makefile-Add-target-to-generate-hex-output-for-combi.patch +++ /dev/null | |||
@@ -1,79 +0,0 @@ | |||
1 | From 939875d39e56d6d2c965c2b63d5d2f20dff532e0 Mon Sep 17 00:00:00 2001 | ||
2 | From: Dalon Westergreen <dalon.westergreen@intel.com> | ||
3 | Date: Wed, 20 Mar 2019 11:21:20 -0700 | ||
4 | Subject: [PATCH 10/12] Makefile: Add target to generate hex output for | ||
5 | combined spl and dtb | ||
6 | |||
7 | Some architectures, Stratix10, require a hex formatted spl that combines | ||
8 | the spl image and dtb. This adds a target to create said hex file with | ||
9 | and offset of SPL_TEXT_BASE. | ||
10 | |||
11 | Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com> | ||
12 | --- | ||
13 | Makefile | 12 +++++++----- | ||
14 | scripts/Makefile.spl | 8 ++++++++ | ||
15 | 2 files changed, 15 insertions(+), 5 deletions(-) | ||
16 | |||
17 | diff --git a/Makefile b/Makefile | ||
18 | index 059978bfe6..62d85ff279 100644 | ||
19 | --- a/Makefile | ||
20 | +++ b/Makefile | ||
21 | @@ -1121,11 +1121,6 @@ OBJCOPYFLAGS_u-boot-nodtb.bin := -O binary \ | ||
22 | $(if $(CONFIG_X86_16BIT_INIT),-R .start16 -R .resetvec) \ | ||
23 | $(if $(CONFIG_MPC85XX_HAVE_RESET_VECTOR),-R .bootpg -R .resetvec) | ||
24 | |||
25 | -OBJCOPYFLAGS_u-boot-spl.hex = $(OBJCOPYFLAGS_u-boot.hex) | ||
26 | - | ||
27 | -spl/u-boot-spl.hex: spl/u-boot-spl FORCE | ||
28 | - $(call if_changed,objcopy) | ||
29 | - | ||
30 | binary_size_check: u-boot-nodtb.bin FORCE | ||
31 | @file_size=$(shell wc -c u-boot-nodtb.bin | awk '{print $$1}') ; \ | ||
32 | map_size=$(shell cat u-boot.map | \ | ||
33 | @@ -1704,6 +1699,13 @@ u-boot.lds: $(LDSCRIPT) prepare FORCE | ||
34 | |||
35 | spl/u-boot-spl.bin: spl/u-boot-spl | ||
36 | @: | ||
37 | + | ||
38 | +spl/u-boot-spl-dtb.bin: spl/u-boot-spl | ||
39 | + @: | ||
40 | + | ||
41 | +spl/u-boot-spl-dtb.hex: spl/u-boot-spl | ||
42 | + @: | ||
43 | + | ||
44 | spl/u-boot-spl: tools prepare \ | ||
45 | $(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_SPL_OF_PLATDATA),dts/dt.dtb) \ | ||
46 | $(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_TPL_OF_PLATDATA),dts/dt.dtb) | ||
47 | diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl | ||
48 | index 7af6b120b6..3c90e2cd72 100644 | ||
49 | --- a/scripts/Makefile.spl | ||
50 | +++ b/scripts/Makefile.spl | ||
51 | @@ -216,6 +216,8 @@ ifneq ($(CONFIG_TARGET_SOCFPGA_GEN5)$(CONFIG_TARGET_SOCFPGA_ARRIA10),) | ||
52 | ALL-y += $(obj)/$(SPL_BIN).sfp | ||
53 | endif | ||
54 | |||
55 | +ALL-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += $(obj)/u-boot-spl-dtb.hex | ||
56 | + | ||
57 | ifdef CONFIG_ARCH_SUNXI | ||
58 | ALL-y += $(obj)/sunxi-spl.bin | ||
59 | |||
60 | @@ -363,6 +365,11 @@ endif | ||
61 | $(obj)/$(SPL_BIN).sfp: $(obj)/$(SPL_BIN).bin FORCE | ||
62 | $(call if_changed,mkimage) | ||
63 | |||
64 | +OBJCOPYFLAGS_u-boot-spl-dtb.hex := -I binary -O ihex --change-address=$(CONFIG_SPL_TEXT_BASE) | ||
65 | + | ||
66 | +$(obj)/u-boot-spl-dtb.hex: $(obj)/u-boot-spl-dtb.bin FORCE | ||
67 | + $(call if_changed,objcopy) | ||
68 | + | ||
69 | quiet_cmd_mksunxiboot = MKSUNXI $@ | ||
70 | cmd_mksunxiboot = $(objtree)/tools/mksunxiboot \ | ||
71 | --default-dt $(CONFIG_DEFAULT_DEVICE_TREE) $< $@ | ||
72 | @@ -463,3 +470,4 @@ ifdef CONFIG_ARCH_K3 | ||
73 | tispl.bin: $(obj)/u-boot-spl-nodtb.bin $(SHRUNK_ARCH_DTB) $(SPL_ITS) FORCE | ||
74 | $(call if_changed,mkfitimage) | ||
75 | endif | ||
76 | + | ||
77 | -- | ||
78 | 2.21.0 | ||
79 | |||
diff --git a/recipes-bsp/u-boot/files/v2019.07/0011-ARM-socfpga-stratix10-Remove-CONFIG_OF_EMBED.patch b/recipes-bsp/u-boot/files/v2019.07/0011-ARM-socfpga-stratix10-Remove-CONFIG_OF_EMBED.patch deleted file mode 100644 index 21794d2..0000000 --- a/recipes-bsp/u-boot/files/v2019.07/0011-ARM-socfpga-stratix10-Remove-CONFIG_OF_EMBED.patch +++ /dev/null | |||
@@ -1,52 +0,0 @@ | |||
1 | From 37814e55403a9ec5f852b58576618ba9a1936a20 Mon Sep 17 00:00:00 2001 | ||
2 | From: Dalon Westergreen <dalon.westergreen@intel.com> | ||
3 | Date: Fri, 10 May 2019 10:30:44 -0700 | ||
4 | Subject: [PATCH 11/12] ARM: socfpga: stratix10: Remove CONFIG_OF_EMBED | ||
5 | |||
6 | CONFIG_OF_EMBED was primarily enabled to support the stratix10 | ||
7 | spl hex file requirements. Since this option now produces a | ||
8 | warning during build, and the spl hex can be created using | ||
9 | alternate methods, CONFIG_OF_EMBED is no longer needed. | ||
10 | |||
11 | Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com> | ||
12 | --- | ||
13 | configs/socfpga_stratix10_defconfig | 1 - | ||
14 | include/configs/socfpga_stratix10_socdk.h | 4 ++-- | ||
15 | 2 files changed, 2 insertions(+), 3 deletions(-) | ||
16 | |||
17 | diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig | ||
18 | index fbab388b43..f27180385d 100644 | ||
19 | --- a/configs/socfpga_stratix10_defconfig | ||
20 | +++ b/configs/socfpga_stratix10_defconfig | ||
21 | @@ -26,7 +26,6 @@ CONFIG_CMD_CACHE=y | ||
22 | CONFIG_CMD_EXT4=y | ||
23 | CONFIG_CMD_FAT=y | ||
24 | CONFIG_CMD_FS_GENERIC=y | ||
25 | -CONFIG_OF_EMBED=y | ||
26 | CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk" | ||
27 | CONFIG_ENV_IS_IN_MMC=y | ||
28 | CONFIG_NET_RANDOM_ETHADDR=y | ||
29 | diff --git a/include/configs/socfpga_stratix10_socdk.h b/include/configs/socfpga_stratix10_socdk.h | ||
30 | index 39d757d737..e93c598be9 100644 | ||
31 | --- a/include/configs/socfpga_stratix10_socdk.h | ||
32 | +++ b/include/configs/socfpga_stratix10_socdk.h | ||
33 | @@ -197,7 +197,7 @@ unsigned int cm_get_l4_sys_free_clk_hz(void); | ||
34 | * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB) | ||
35 | * | ||
36 | */ | ||
37 | -#define CONFIG_SPL_TARGET "spl/u-boot-spl.hex" | ||
38 | +#define CONFIG_SPL_TARGET "spl/u-boot-spl-dtb.hex" | ||
39 | #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE | ||
40 | #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR | ||
41 | #define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */ | ||
42 | @@ -210,6 +210,6 @@ unsigned int cm_get_l4_sys_free_clk_hz(void); | ||
43 | |||
44 | /* SPL SDMMC boot support */ | ||
45 | #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 | ||
46 | -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" | ||
47 | +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" | ||
48 | |||
49 | #endif /* __CONFIG_H */ | ||
50 | -- | ||
51 | 2.21.0 | ||
52 | |||
diff --git a/recipes-bsp/u-boot/files/v2019.07/0011-Makefile-Add-target-to-generate-hex-output-for-combi.patch b/recipes-bsp/u-boot/files/v2019.07/0011-Makefile-Add-target-to-generate-hex-output-for-combi.patch new file mode 100644 index 0000000..640df20 --- /dev/null +++ b/recipes-bsp/u-boot/files/v2019.07/0011-Makefile-Add-target-to-generate-hex-output-for-combi.patch | |||
@@ -0,0 +1,87 @@ | |||
1 | From 56332c75a69a9f9ef7928e0f43d1fc509db9c866 Mon Sep 17 00:00:00 2001 | ||
2 | From: Dalon Westergreen <dalon.westergreen@intel.com> | ||
3 | Date: Wed, 20 Mar 2019 11:21:20 -0700 | ||
4 | Subject: [PATCH 11/14] Makefile: Add target to generate hex output for | ||
5 | combined spl and dtb | ||
6 | |||
7 | Stratix10 requires a hex image of the spl plus spl devicetree offset to | ||
8 | the Stratix10 onchip memory located at SPL_TEXT_BASE. This patch adds | ||
9 | a target to generate a hex file from the u-boot-spl binary including the | ||
10 | dtb offset at SPL_TEST_BASE. | ||
11 | |||
12 | Objcopy is used to convert the $(SPL_BIN).bin, which includes the spl | ||
13 | dtb, to a hex file. the --change-address option is used to offset the | ||
14 | hex to SPL_TEXT_BASE as objcopy on the spl binary will not result in | ||
15 | a hex file appropriately offset at SPL_TEXT_BASE. | ||
16 | |||
17 | Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com> | ||
18 | |||
19 | --- | ||
20 | Changes in v3: | ||
21 | -> Cleanup commit message and better describe the problem being | ||
22 | resolved | ||
23 | -> Remove extraneous hunk | ||
24 | -> use SPL_BIN instead of u-boot-spl | ||
25 | Changes in v2: | ||
26 | -> Move spl hex file generation to SPL Makefile | ||
27 | -> Create hexfile from $(SPL_BIN).bin which will include the dtb | ||
28 | ifneq(build_dtb,) | ||
29 | --- | ||
30 | Makefile | 8 +++----- | ||
31 | scripts/Makefile.spl | 7 +++++++ | ||
32 | 2 files changed, 10 insertions(+), 5 deletions(-) | ||
33 | |||
34 | diff --git a/Makefile b/Makefile | ||
35 | index 516260f46d..8236f095fc 100644 | ||
36 | --- a/Makefile | ||
37 | +++ b/Makefile | ||
38 | @@ -1136,11 +1136,6 @@ OBJCOPYFLAGS_u-boot-nodtb.bin := -O binary \ | ||
39 | $(if $(CONFIG_X86_16BIT_INIT),-R .start16 -R .resetvec) \ | ||
40 | $(if $(CONFIG_MPC85XX_HAVE_RESET_VECTOR),-R .bootpg -R .resetvec) | ||
41 | |||
42 | -OBJCOPYFLAGS_u-boot-spl.hex = $(OBJCOPYFLAGS_u-boot.hex) | ||
43 | - | ||
44 | -spl/u-boot-spl.hex: spl/u-boot-spl FORCE | ||
45 | - $(call if_changed,objcopy) | ||
46 | - | ||
47 | binary_size_check: u-boot-nodtb.bin FORCE | ||
48 | @file_size=$(shell wc -c u-boot-nodtb.bin | awk '{print $$1}') ; \ | ||
49 | map_size=$(shell cat u-boot.map | \ | ||
50 | @@ -1721,6 +1716,9 @@ spl/u-boot-spl.bin: spl/u-boot-spl | ||
51 | @: | ||
52 | $(SPL_SIZE_CHECK) | ||
53 | |||
54 | +spl/u-boot-spl.hex: spl/u-boot-spl | ||
55 | + @: | ||
56 | + | ||
57 | spl/u-boot-spl: tools prepare \ | ||
58 | $(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_SPL_OF_PLATDATA),dts/dt.dtb) \ | ||
59 | $(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_TPL_OF_PLATDATA),dts/dt.dtb) | ||
60 | diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl | ||
61 | index 7af6b120b6..551002194e 100644 | ||
62 | --- a/scripts/Makefile.spl | ||
63 | +++ b/scripts/Makefile.spl | ||
64 | @@ -216,6 +216,8 @@ ifneq ($(CONFIG_TARGET_SOCFPGA_GEN5)$(CONFIG_TARGET_SOCFPGA_ARRIA10),) | ||
65 | ALL-y += $(obj)/$(SPL_BIN).sfp | ||
66 | endif | ||
67 | |||
68 | +ALL-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += $(obj)/$(SPL_BIN).hex | ||
69 | + | ||
70 | ifdef CONFIG_ARCH_SUNXI | ||
71 | ALL-y += $(obj)/sunxi-spl.bin | ||
72 | |||
73 | @@ -363,6 +365,11 @@ endif | ||
74 | $(obj)/$(SPL_BIN).sfp: $(obj)/$(SPL_BIN).bin FORCE | ||
75 | $(call if_changed,mkimage) | ||
76 | |||
77 | +OBJCOPYFLAGS_$(SPL_BIN).hex := -I binary -O ihex --change-address=$(CONFIG_SPL_TEXT_BASE) | ||
78 | + | ||
79 | +$(obj)/$(SPL_BIN).hex: $(obj)/$(SPL_BIN).bin FORCE | ||
80 | + $(call if_changed,objcopy) | ||
81 | + | ||
82 | quiet_cmd_mksunxiboot = MKSUNXI $@ | ||
83 | cmd_mksunxiboot = $(objtree)/tools/mksunxiboot \ | ||
84 | --default-dt $(CONFIG_DEFAULT_DEVICE_TREE) $< $@ | ||
85 | -- | ||
86 | 2.21.0 | ||
87 | |||
diff --git a/recipes-bsp/u-boot/files/v2019.07/0012-ARM-socfpga-stratix10-Remove-CONFIG_OF_EMBED.patch b/recipes-bsp/u-boot/files/v2019.07/0012-ARM-socfpga-stratix10-Remove-CONFIG_OF_EMBED.patch new file mode 100644 index 0000000..40e7704 --- /dev/null +++ b/recipes-bsp/u-boot/files/v2019.07/0012-ARM-socfpga-stratix10-Remove-CONFIG_OF_EMBED.patch | |||
@@ -0,0 +1,36 @@ | |||
1 | From 708a2590681425da62f9027f5ed1144377a001bf Mon Sep 17 00:00:00 2001 | ||
2 | From: Dalon Westergreen <dalon.westergreen@intel.com> | ||
3 | Date: Fri, 10 May 2019 10:30:44 -0700 | ||
4 | Subject: [PATCH 12/14] ARM: socfpga: stratix10: Remove CONFIG_OF_EMBED | ||
5 | |||
6 | CONFIG_OF_EMBED was primarily enabled to support the stratix10 | ||
7 | spl hex file requirements. Since this option now produces a | ||
8 | warning during build, and the spl hex can be created using | ||
9 | alternate methods, CONFIG_OF_EMBED is no longer needed. | ||
10 | |||
11 | Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com> | ||
12 | |||
13 | --- | ||
14 | Changes in v3: | ||
15 | -> Revert to u-boot.img for SPL payload name | ||
16 | Changes in v2: | ||
17 | -> Change CONFIG_SPL_TARGET back to u-boot-spl.hex | ||
18 | --- | ||
19 | configs/socfpga_stratix10_defconfig | 1 - | ||
20 | 1 file changed, 1 deletion(-) | ||
21 | |||
22 | diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig | ||
23 | index fbab388b43..f27180385d 100644 | ||
24 | --- a/configs/socfpga_stratix10_defconfig | ||
25 | +++ b/configs/socfpga_stratix10_defconfig | ||
26 | @@ -26,7 +26,6 @@ CONFIG_CMD_CACHE=y | ||
27 | CONFIG_CMD_EXT4=y | ||
28 | CONFIG_CMD_FAT=y | ||
29 | CONFIG_CMD_FS_GENERIC=y | ||
30 | -CONFIG_OF_EMBED=y | ||
31 | CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk" | ||
32 | CONFIG_ENV_IS_IN_MMC=y | ||
33 | CONFIG_NET_RANDOM_ETHADDR=y | ||
34 | -- | ||
35 | 2.21.0 | ||
36 | |||
diff --git a/recipes-bsp/u-boot/files/v2019.07/0012-ARM-socfpga-stratix10-Temporarily-revert-to-2GB-DRAM.patch b/recipes-bsp/u-boot/files/v2019.07/0012-ARM-socfpga-stratix10-Temporarily-revert-to-2GB-DRAM.patch deleted file mode 100644 index c7f73ba..0000000 --- a/recipes-bsp/u-boot/files/v2019.07/0012-ARM-socfpga-stratix10-Temporarily-revert-to-2GB-DRAM.patch +++ /dev/null | |||
@@ -1,31 +0,0 @@ | |||
1 | From 97d491bda1dea7d2afe74a7c3fb4ea43a83a79ff Mon Sep 17 00:00:00 2001 | ||
2 | From: Dalon Westergreen <dalon.westergreen@intel.com> | ||
3 | Date: Fri, 10 May 2019 10:31:15 -0700 | ||
4 | Subject: [PATCH 12/12] ARM: socfpga: stratix10: Temporarily revert to 2GB DRAM | ||
5 | |||
6 | The current shipping GHRD still has the DDR configured as a | ||
7 | 2GB DDR. This reverts the devicetree to use 2GB instead of | ||
8 | 4GB. | ||
9 | |||
10 | Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com> | ||
11 | --- | ||
12 | arch/arm/dts/socfpga_stratix10_socdk.dts | 3 +-- | ||
13 | 1 file changed, 1 insertion(+), 2 deletions(-) | ||
14 | |||
15 | diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts | ||
16 | index 2745050810..1caae0ab6f 100755 | ||
17 | --- a/arch/arm/dts/socfpga_stratix10_socdk.dts | ||
18 | +++ b/arch/arm/dts/socfpga_stratix10_socdk.dts | ||
19 | @@ -37,8 +37,7 @@ | ||
20 | memory { | ||
21 | device_type = "memory"; | ||
22 | /* 4GB */ | ||
23 | - reg = <0 0x00000000 0 0x80000000>, | ||
24 | - <1 0x80000000 0 0x80000000>; | ||
25 | + reg = <0 0x00000000 0 0x80000000>; | ||
26 | u-boot,dm-pre-reloc; | ||
27 | }; | ||
28 | }; | ||
29 | -- | ||
30 | 2.21.0 | ||
31 | |||
diff --git a/recipes-bsp/u-boot/files/v2019.07/0013-ARM-socfpga-update-CONFIG_SPL_FS_LOAD_PAYLOAD_NAME-t.patch b/recipes-bsp/u-boot/files/v2019.07/0013-ARM-socfpga-update-CONFIG_SPL_FS_LOAD_PAYLOAD_NAME-t.patch new file mode 100644 index 0000000..3b34325 --- /dev/null +++ b/recipes-bsp/u-boot/files/v2019.07/0013-ARM-socfpga-update-CONFIG_SPL_FS_LOAD_PAYLOAD_NAME-t.patch | |||
@@ -0,0 +1,30 @@ | |||
1 | From 441ba6f4d508bf77cc543feb00d1d3fca9a80934 Mon Sep 17 00:00:00 2001 | ||
2 | From: Dalon Westergreen <dalon.westergreen@intel.com> | ||
3 | Date: Tue, 4 Jun 2019 13:43:59 -0700 | ||
4 | Subject: [PATCH 13/14] ARM: socfpga: update CONFIG_SPL_FS_LOAD_PAYLOAD_NAME to | ||
5 | u-boot.img | ||
6 | |||
7 | Bring cyclone5 / arria5 / arria10 in line with convention and use | ||
8 | u-boot.img as CONFIG_SPL_FS_LOAD_PAYLOAD_NAME. | ||
9 | |||
10 | Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com> | ||
11 | --- | ||
12 | include/configs/socfpga_common.h | 2 +- | ||
13 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
14 | |||
15 | diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h | ||
16 | index d1034ac280..36b0ed5459 100644 | ||
17 | --- a/include/configs/socfpga_common.h | ||
18 | +++ b/include/configs/socfpga_common.h | ||
19 | @@ -203,7 +203,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void); | ||
20 | /* SPL SDMMC boot support */ | ||
21 | #ifdef CONFIG_SPL_MMC_SUPPORT | ||
22 | #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4) | ||
23 | -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" | ||
24 | +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" | ||
25 | #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 | ||
26 | #endif | ||
27 | #else | ||
28 | -- | ||
29 | 2.21.0 | ||
30 | |||
diff --git a/recipes-bsp/u-boot/files/v2019.07/0001-fpga-arria10-Fix-error-in-fpga-pin-configuration.patch b/recipes-bsp/u-boot/files/v2019.07/0014-fpga-arria10-Fix-error-in-fpga-pin-configuration.patch index 2ea6e18..0255efc 100644 --- a/recipes-bsp/u-boot/files/v2019.07/0001-fpga-arria10-Fix-error-in-fpga-pin-configuration.patch +++ b/recipes-bsp/u-boot/files/v2019.07/0014-fpga-arria10-Fix-error-in-fpga-pin-configuration.patch | |||
@@ -1,7 +1,7 @@ | |||
1 | From 58b4cc1a3d1e4a989b65892b97af119c25d9a511 Mon Sep 17 00:00:00 2001 | 1 | From db2095305c0fb464f57b001464fb811a86f19834 Mon Sep 17 00:00:00 2001 |
2 | From: Dalon Westergreen <dalon.westergreen@intel.com> | 2 | From: Dalon Westergreen <dalon.westergreen@intel.com> |
3 | Date: Tue, 16 Jul 2019 09:12:53 -0700 | 3 | Date: Tue, 16 Jul 2019 09:12:53 -0700 |
4 | Subject: [PATCH] fpga: arria10: Fix error in fpga pin configuration | 4 | Subject: [PATCH 14/14] fpga: arria10: Fix error in fpga pin configuration |
5 | 5 | ||
6 | Pin configuration of the FPGA devicetree block should be done | 6 | Pin configuration of the FPGA devicetree block should be done |
7 | after core configuration in the arria10 fpga driver. This fix | 7 | after core configuration in the arria10 fpga driver. This fix |
diff --git a/recipes-bsp/u-boot/u-boot-socfpga_v2019.07.bb b/recipes-bsp/u-boot/u-boot-socfpga_v2019.07.bb index 0229a01..0fd1ff0 100644 --- a/recipes-bsp/u-boot/u-boot-socfpga_v2019.07.bb +++ b/recipes-bsp/u-boot/u-boot-socfpga_v2019.07.bb | |||
@@ -4,8 +4,6 @@ require ${COREBASE}/meta/recipes-bsp/u-boot/u-boot.inc | |||
4 | LICENSE = "GPLv2+" | 4 | LICENSE = "GPLv2+" |
5 | LIC_FILES_CHKSUM = "file://Licenses/README;md5=30503fd321432fc713238f582193b78e" | 5 | LIC_FILES_CHKSUM = "file://Licenses/README;md5=30503fd321432fc713238f582193b78e" |
6 | 6 | ||
7 | PR = "2" | ||
8 | |||
9 | FILESEXTRAPATHS =. "${THISDIR}/files/v2019.07:" | 7 | FILESEXTRAPATHS =. "${THISDIR}/files/v2019.07:" |
10 | 8 | ||
11 | SRCREV = "e5aee22e4be75e75a854ab64503fc80598bc2004" | 9 | SRCREV = "e5aee22e4be75e75a854ab64503fc80598bc2004" |
@@ -20,11 +18,11 @@ SRC_URI_append = "\ | |||
20 | file://0007-mmc-dwmmc-Enable-small-delay-before-returning-error.patch \ | 18 | file://0007-mmc-dwmmc-Enable-small-delay-before-returning-error.patch \ |
21 | file://0008-ARM-socfpga-stratix10-Enable-DMA330-DMA-controller.patch \ | 19 | file://0008-ARM-socfpga-stratix10-Enable-DMA330-DMA-controller.patch \ |
22 | file://0009-ARM-socfpga-Stratix10-Fix-el3_exception_vectors-relo.patch \ | 20 | file://0009-ARM-socfpga-Stratix10-Fix-el3_exception_vectors-relo.patch \ |
23 | file://0010-Makefile-Add-target-to-generate-hex-output-for-combi.patch \ | 21 | file://0010-ARM-socfpga-Stratix10-Disable-CONFIG_PSCI_RESET.patch \ |
24 | file://0011-ARM-socfpga-stratix10-Remove-CONFIG_OF_EMBED.patch \ | 22 | file://0011-Makefile-Add-target-to-generate-hex-output-for-combi.patch \ |
25 | file://0012-ARM-socfpga-stratix10-Temporarily-revert-to-2GB-DRAM.patch \ | 23 | file://0012-ARM-socfpga-stratix10-Remove-CONFIG_OF_EMBED.patch \ |
26 | file://0001-ARM-socfpga-Stratix10-Disable-CONFIG_PSCI_RESET.patch \ | 24 | file://0013-ARM-socfpga-update-CONFIG_SPL_FS_LOAD_PAYLOAD_NAME-t.patch \ |
27 | file://0001-fpga-arria10-Fix-error-in-fpga-pin-configuration.patch \ | 25 | file://0014-fpga-arria10-Fix-error-in-fpga-pin-configuration.patch \ |
28 | " | 26 | " |
29 | 27 | ||
30 | DEPENDS += "dtc-native bc-native bison-native u-boot-mkimage-native" | 28 | DEPENDS += "dtc-native bc-native bison-native u-boot-mkimage-native" |