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* The poky repository master branch is no longer being updated.Richard Purdie2025-11-071-23/+0
| | | | | | | | | | | | | | | | | | | | | You can either: a) switch to individual clones of bitbake, openembedded-core, meta-yocto and yocto-docs b) use the new bitbake-setup You can find information about either approach in our documentation: https://docs.yoctoproject.org/ Note that "poky" the distro setting is still available in meta-yocto as before and we continue to use and maintain that. Long live Poky! Some further information on the background of this change can be found in: https://lists.openembedded.org/g/openembedded-architecture/message/2179 Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* riscv tunes: ISA Implementation of RISC-V tune featuresMark Hatle2025-06-201-29/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This implements the following base ISAs: * rv32i, rv64i * rv32e, rv64i The following ABIs: * ilp32, ilp32e, ilp32f, ilp32d * lp64, lp64e, lp64f, lp64d The following ISA extension are also implemented: * M - Integer Multiplication and Division Extension * A - Atomic Memory Extension * F - Single-Precision Floating-Point Extension * D - Double-Precision Floating-Point Extension * C - Compressed Extension * B - Bit Manipulation Extension (implies Zba, Zbb, Zbs) * V - Vector Operations Extension * Zicsr - Control and Status Register Access Extension * Zifencei - Instruction-Fetch Fence Extension * Zba - Address bit manipulation extension * Zbb - Basic bit manipulation extension * Zbc - Carry-less multiplication extension * Zbs - Single-bit manipulation extension * Zicbom - Cache-block management extension The existing processors tunes are preserved: * riscv64 (rv64gc) * riscv32 (rv32gc) * riscv64nf (rv64imac_zicsr_zifencei) * riscv32nf (rv32imac_zicsr_zifencei) * riscv64nc (rv64imafd_zicsr_zifencei) Previously defined feature 'big-endian' has been removed as it was not used. (From OE-Core rev: bcaf298a146dfd10e4c8f44223ea083bc4baf45c) Signed-off-by: Mark Hatle <mark.hatle@amd.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* tune-riscv.inc: Add riscv64nc to available tunes listKhem Raj2023-02-241-1/+1
| | | | | | | | | This was missed when riscv64nc was added (From OE-Core rev: 0c549ef5732afdcd96407ceb045983eed2ca75f4) Signed-off-by: Khem Raj <raj.khem@gmail.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* riscv: Add tunes for rv64 without compressed instructionsKhem Raj2022-04-191-0/+8
| | | | | | | | (From OE-Core rev: 4790eaf98e030ffeecfbde6644137c9d6d1873d7) Signed-off-by: Khem Raj <raj.khem@gmail.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* Convert to new override syntaxRichard Purdie2021-08-021-17/+17
| | | | | | | | | | | | This is the result of automated script conversion: scripts/contrib/convert-overrides.py <oe-core directory> converting the metadata to use ":" as the override character instead of "_". (From OE-Core rev: 42344347be29f0997cc2f7636d9603b1fe1875ae) Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* tune-riscv.inc: use nf suffix also for TUNE_PKGARCHMartin Jansa2020-10-171-2/+2
| | | | | | | | | | | | | | | | | | * broken since introduction: commit 5263b2ebc57fe289d64c74bfb10da39ed7c98828 Author: Alistair Francis <alistair.francis@wdc.com> Date: Thu Dec 19 13:24:10 2019 -0800 tune-riscv: Add support for no float * fixes: scripts/tune/log.fake-riscv.riscv32nf: Error, the PACKAGE_ARCHS variable (all any noarch riscv32nf fake_riscv) for DEFAULTTUNE (riscv32nf) does not contain TUNE_PKGARCH (riscv32). scripts/tune/log.fake-riscv.riscv64nf: Error, the PACKAGE_ARCHS variable (all any noarch riscv64nf fake_riscv) for DEFAULTTUNE (riscv64nf) does not contain TUNE_PKGARCH (riscv64). (From OE-Core rev: 58088dce12775e325df8428b750e19616d264464) Signed-off-by: Martin Jansa <Martin.Jansa@gmail.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* tune-riscv: Add support for no floatAlistair Francis2019-12-301-1/+15
| | | | | | | (From OE-Core rev: 5263b2ebc57fe289d64c74bfb10da39ed7c98828) Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* tune-riscv: Drop littleendian and introduce bigendian tuneKhem Raj2019-09-031-3/+3
| | | | | | | | | | | Default riscv is little-endian moreover most of other arches define bigendian as tune and treats absense as litteendian, this make risc-v fall in line (From OE-Core rev: cd6f377591a7bd7b3c61ce580f997aaeffab3df3) Signed-off-by: Khem Raj <raj.khem@gmail.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* qemuriscv64: Add the QEMU RISC-V 64-bit machineAlistair Francis2019-06-191-0/+19
The include is split ready to add the 32-bit RISC-V machine as soon as glibc supports 32-bit RISC-V. This is based on the work in the meta-riscv layer, thanks to Khem for starting this. (From OE-Core rev: 11b6020dff4550fc3a42e04bc1e86baf37942c62) Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
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