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* The poky repository master branch is no longer being updated.Richard Purdie2025-11-071-142/+0
| | | | | | | | | | | | | | | | | | | | | You can either: a) switch to individual clones of bitbake, openembedded-core, meta-yocto and yocto-docs b) use the new bitbake-setup You can find information about either approach in our documentation: https://docs.yoctoproject.org/ Note that "poky" the distro setting is still available in meta-yocto as before and we continue to use and maintain that. Long live Poky! Some further information on the background of this change can be found in: https://lists.openembedded.org/g/openembedded-architecture/message/2179 Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* riscv tunes: ISA Implementation of RISC-V tune featuresMark Hatle2025-06-201-6/+132
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This implements the following base ISAs: * rv32i, rv64i * rv32e, rv64i The following ABIs: * ilp32, ilp32e, ilp32f, ilp32d * lp64, lp64e, lp64f, lp64d The following ISA extension are also implemented: * M - Integer Multiplication and Division Extension * A - Atomic Memory Extension * F - Single-Precision Floating-Point Extension * D - Double-Precision Floating-Point Extension * C - Compressed Extension * B - Bit Manipulation Extension (implies Zba, Zbb, Zbs) * V - Vector Operations Extension * Zicsr - Control and Status Register Access Extension * Zifencei - Instruction-Fetch Fence Extension * Zba - Address bit manipulation extension * Zbb - Basic bit manipulation extension * Zbc - Carry-less multiplication extension * Zbs - Single-bit manipulation extension * Zicbom - Cache-block management extension The existing processors tunes are preserved: * riscv64 (rv64gc) * riscv32 (rv32gc) * riscv64nf (rv64imac_zicsr_zifencei) * riscv32nf (rv32imac_zicsr_zifencei) * riscv64nc (rv64imafd_zicsr_zifencei) Previously defined feature 'big-endian' has been removed as it was not used. (From OE-Core rev: bcaf298a146dfd10e4c8f44223ea083bc4baf45c) Signed-off-by: Mark Hatle <mark.hatle@amd.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* tclibc-picolibc: Adds a new TCLIBC variant to build with picolibc as C libraryAlejandro Hernandez Samaniego2024-07-261-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enables usage of TCLIBC=picolibc extending OE functionality to build and use picolibc based toolchains to build baremetal applications. Picolibc is a set of standard C libraries, both libc and libm, designed for smaller embedded systems with limited ROM and RAM. Picolibc includes code from Newlib and AVR Libc, but adresses some of newlibs concerns, it retains newlibs directory structure, math, string and locale implementations, but removed the GPL bits used to build the library, swiches old C style code for C18 and replaces autotools with meson. This patch adds a picolibc recipe for the C library, a picolibc-helloworld recipe that contains an example application and a testcase that builds it. Picolibc can be built for ARM and RISCV architectures, its been tested both for 32 and 64 bits, the provided example recipe produces the following output: hello, world Runqemu does not automatically show any output since it hides QEMU stderr which is where the QEMU monitors output is directed to when using semihosting, but, manually running the same QEMU command does work properly. (From OE-Core rev: c7535ecaccb72ef21a61f9aec5c68e61fb4f6fb6) Signed-off-by: Alejandro Enedino Hernandez Samaniego <alejandro@enedino.org> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* riscv: Add tunes for rv64 without compressed instructionsKhem Raj2022-04-191-0/+2
| | | | | | | | (From OE-Core rev: 4790eaf98e030ffeecfbde6644137c9d6d1873d7) Signed-off-by: Khem Raj <raj.khem@gmail.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* Convert to new override syntaxRichard Purdie2021-08-021-6/+6
| | | | | | | | | | | | This is the result of automated script conversion: scripts/contrib/convert-overrides.py <oe-core directory> converting the metadata to use ":" as the override character instead of "_". (From OE-Core rev: 42344347be29f0997cc2f7636d9603b1fe1875ae) Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* arch-riscv: Enable qemu-usermode on rv32Khem Raj2020-11-171-3/+0
| | | | | | | | | | Current version of Qemu in OE-core now works fine in rv32/user-mode the said nvalid instruction errors are gone, so we can enable it now (From OE-Core rev: f3fa54f91eef5b1b967a6a14b53a07de052dd17a) Signed-off-by: Khem Raj <raj.khem@gmail.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* tune-riscv: Add support for no floatAlistair Francis2019-12-301-1/+2
| | | | | | | (From OE-Core rev: 5263b2ebc57fe289d64c74bfb10da39ed7c98828) Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* machine/arch-riscv: Fix newlib and baremetal buildsAlistair Francis2019-11-291-0/+5
| | | | | | | | | | | | Fix the following errors for newlib and baremetal libcs: ld: unrecognized option '--hash-style=sysv' ld: unrecognized option '--hash-style=gnu' (From OE-Core rev: 8ae998fa8dd216d008cc9ddbea98bbb945501e41) Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Ross Burton <ross.burton@intel.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
* qemuriscv64: Add the QEMU RISC-V 64-bit machineAlistair Francis2019-06-191-0/+10
The include is split ready to add the 32-bit RISC-V machine as soon as glibc supports 32-bit RISC-V. This is based on the work in the meta-riscv layer, thanks to Khem for starting this. (From OE-Core rev: 11b6020dff4550fc3a42e04bc1e86baf37942c62) Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>