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-rw-r--r--meta/recipes-devtools/elfutils/elfutils-0.164/arm_backend.diff600
1 files changed, 600 insertions, 0 deletions
diff --git a/meta/recipes-devtools/elfutils/elfutils-0.164/arm_backend.diff b/meta/recipes-devtools/elfutils/elfutils-0.164/arm_backend.diff
new file mode 100644
index 0000000000..9d47f95f26
--- /dev/null
+++ b/meta/recipes-devtools/elfutils/elfutils-0.164/arm_backend.diff
@@ -0,0 +1,600 @@
1Index: elfutils-0.164/backends/arm_init.c
2===================================================================
3--- elfutils-0.164.orig/backends/arm_init.c
4+++ elfutils-0.164/backends/arm_init.c
5@@ -35,20 +35,31 @@
6 #define RELOC_PREFIX R_ARM_
7 #include "libebl_CPU.h"
8
9+#include "libebl_arm.h"
10+
11 /* This defines the common reloc hooks based on arm_reloc.def. */
12 #include "common-reloc.c"
13
14
15 const char *
16-arm_init (Elf *elf __attribute__ ((unused)),
17+arm_init (Elf *elf,
18 GElf_Half machine __attribute__ ((unused)),
19 Ebl *eh,
20 size_t ehlen)
21 {
22+ int soft_float = 0;
23+
24 /* Check whether the Elf_BH object has a sufficent size. */
25 if (ehlen < sizeof (Ebl))
26 return NULL;
27
28+ if (elf) {
29+ GElf_Ehdr ehdr_mem;
30+ GElf_Ehdr *ehdr = gelf_getehdr (elf, &ehdr_mem);
31+ if (ehdr && (ehdr->e_flags & EF_ARM_SOFT_FLOAT))
32+ soft_float = 1;
33+ }
34+
35 /* We handle it. */
36 eh->name = "ARM";
37 arm_init_reloc (eh);
38@@ -60,7 +71,10 @@ arm_init (Elf *elf __attribute__ ((unuse
39 HOOK (eh, core_note);
40 HOOK (eh, auxv_info);
41 HOOK (eh, check_object_attribute);
42- HOOK (eh, return_value_location);
43+ if (soft_float)
44+ eh->return_value_location = arm_return_value_location_soft;
45+ else
46+ eh->return_value_location = arm_return_value_location_hard;
47 HOOK (eh, abi_cfi);
48 HOOK (eh, check_reloc_target_type);
49 HOOK (eh, symbol_type_name);
50Index: elfutils-0.164/backends/arm_regs.c
51===================================================================
52--- elfutils-0.164.orig/backends/arm_regs.c
53+++ elfutils-0.164/backends/arm_regs.c
54@@ -31,6 +31,7 @@
55 #endif
56
57 #include <string.h>
58+#include <stdio.h>
59 #include <dwarf.h>
60
61 #define BACKEND arm_
62@@ -76,6 +77,9 @@ arm_register_info (Ebl *ebl __attribute_
63 break;
64
65 case 16 + 0 ... 16 + 7:
66+ /* AADWARF says that there are no registers in that range,
67+ * but gcc maps FPA registers here
68+ */
69 regno += 96 - 16;
70 /* Fall through. */
71 case 96 + 0 ... 96 + 7:
72@@ -87,11 +91,139 @@ arm_register_info (Ebl *ebl __attribute_
73 namelen = 2;
74 break;
75
76+ case 64 + 0 ... 64 + 9:
77+ *setname = "VFP";
78+ *bits = 32;
79+ *type = DW_ATE_float;
80+ name[0] = 's';
81+ name[1] = regno - 64 + '0';
82+ namelen = 2;
83+ break;
84+
85+ case 64 + 10 ... 64 + 31:
86+ *setname = "VFP";
87+ *bits = 32;
88+ *type = DW_ATE_float;
89+ name[0] = 's';
90+ name[1] = (regno - 64) / 10 + '0';
91+ name[2] = (regno - 64) % 10 + '0';
92+ namelen = 3;
93+ break;
94+
95+ case 104 + 0 ... 104 + 7:
96+ /* XXX TODO:
97+ * This can be either intel wireless MMX general purpose/control
98+ * registers or xscale accumulator, which have different usage.
99+ * We only have the intel wireless MMX here now.
100+ * The name needs to be changed for the xscale accumulator too. */
101+ *setname = "MMX";
102+ *type = DW_ATE_unsigned;
103+ *bits = 32;
104+ memcpy(name, "wcgr", 4);
105+ name[4] = regno - 104 + '0';
106+ namelen = 5;
107+ break;
108+
109+ case 112 + 0 ... 112 + 9:
110+ *setname = "MMX";
111+ *type = DW_ATE_unsigned;
112+ *bits = 64;
113+ name[0] = 'w';
114+ name[1] = 'r';
115+ name[2] = regno - 112 + '0';
116+ namelen = 3;
117+ break;
118+
119+ case 112 + 10 ... 112 + 15:
120+ *setname = "MMX";
121+ *type = DW_ATE_unsigned;
122+ *bits = 64;
123+ name[0] = 'w';
124+ name[1] = 'r';
125+ name[2] = '1';
126+ name[3] = regno - 112 - 10 + '0';
127+ namelen = 4;
128+ break;
129+
130 case 128:
131+ *setname = "state";
132 *type = DW_ATE_unsigned;
133 return stpcpy (name, "spsr") + 1 - name;
134
135+ case 129:
136+ *setname = "state";
137+ *type = DW_ATE_unsigned;
138+ return stpcpy(name, "spsr_fiq") + 1 - name;
139+
140+ case 130:
141+ *setname = "state";
142+ *type = DW_ATE_unsigned;
143+ return stpcpy(name, "spsr_irq") + 1 - name;
144+
145+ case 131:
146+ *setname = "state";
147+ *type = DW_ATE_unsigned;
148+ return stpcpy(name, "spsr_abt") + 1 - name;
149+
150+ case 132:
151+ *setname = "state";
152+ *type = DW_ATE_unsigned;
153+ return stpcpy(name, "spsr_und") + 1 - name;
154+
155+ case 133:
156+ *setname = "state";
157+ *type = DW_ATE_unsigned;
158+ return stpcpy(name, "spsr_svc") + 1 - name;
159+
160+ case 144 ... 150:
161+ *setname = "integer";
162+ *type = DW_ATE_signed;
163+ *bits = 32;
164+ return sprintf(name, "r%d_usr", regno - 144 + 8) + 1;
165+
166+ case 151 ... 157:
167+ *setname = "integer";
168+ *type = DW_ATE_signed;
169+ *bits = 32;
170+ return sprintf(name, "r%d_fiq", regno - 151 + 8) + 1;
171+
172+ case 158 ... 159:
173+ *setname = "integer";
174+ *type = DW_ATE_signed;
175+ *bits = 32;
176+ return sprintf(name, "r%d_irq", regno - 158 + 13) + 1;
177+
178+ case 160 ... 161:
179+ *setname = "integer";
180+ *type = DW_ATE_signed;
181+ *bits = 32;
182+ return sprintf(name, "r%d_abt", regno - 160 + 13) + 1;
183+
184+ case 162 ... 163:
185+ *setname = "integer";
186+ *type = DW_ATE_signed;
187+ *bits = 32;
188+ return sprintf(name, "r%d_und", regno - 162 + 13) + 1;
189+
190+ case 164 ... 165:
191+ *setname = "integer";
192+ *type = DW_ATE_signed;
193+ *bits = 32;
194+ return sprintf(name, "r%d_svc", regno - 164 + 13) + 1;
195+
196+ case 192 ... 199:
197+ *setname = "MMX";
198+ *bits = 32;
199+ *type = DW_ATE_unsigned;
200+ name[0] = 'w';
201+ name[1] = 'c';
202+ name[2] = regno - 192 + '0';
203+ namelen = 3;
204+ break;
205+
206 case 256 + 0 ... 256 + 9:
207+ /* XXX TODO: Neon also uses those registers and can contain
208+ * both float and integers */
209 *setname = "VFP";
210 *type = DW_ATE_float;
211 *bits = 64;
212Index: elfutils-0.164/backends/arm_retval.c
213===================================================================
214--- elfutils-0.164.orig/backends/arm_retval.c
215+++ elfutils-0.164/backends/arm_retval.c
216@@ -48,6 +48,13 @@ static const Dwarf_Op loc_intreg[] =
217 #define nloc_intreg 1
218 #define nloc_intregs(n) (2 * (n))
219
220+/* f1 */ /* XXX TODO: f0 can also have number 96 if program was compiled with -mabi=aapcs */
221+static const Dwarf_Op loc_fpreg[] =
222+ {
223+ { .atom = DW_OP_reg16 },
224+ };
225+#define nloc_fpreg 1
226+
227 /* The return value is a structure and is actually stored in stack space
228 passed in a hidden argument by the caller. But, the compiler
229 helpfully returns the address of that space in r0. */
230@@ -58,8 +65,9 @@ static const Dwarf_Op loc_aggregate[] =
231 #define nloc_aggregate 1
232
233
234-int
235-arm_return_value_location (Dwarf_Die *functypedie, const Dwarf_Op **locp)
236+static int
237+arm_return_value_location_ (Dwarf_Die *functypedie, const Dwarf_Op **locp,
238+ int soft_float)
239 {
240 /* Start with the function's type, and get the DW_AT_type attribute,
241 which is the type of the return value. */
242@@ -98,6 +106,21 @@ arm_return_value_location (Dwarf_Die *fu
243 else
244 return -1;
245 }
246+ if (tag == DW_TAG_base_type)
247+ {
248+ Dwarf_Word encoding;
249+ if (dwarf_formudata (dwarf_attr_integrate (typedie, DW_AT_encoding,
250+ &attr_mem), &encoding) != 0)
251+ return -1;
252+
253+ if ((encoding == DW_ATE_float) && !soft_float)
254+ {
255+ *locp = loc_fpreg;
256+ if (size <= 8)
257+ return nloc_fpreg;
258+ goto aggregate;
259+ }
260+ }
261 if (size <= 16)
262 {
263 intreg:
264@@ -106,6 +129,7 @@ arm_return_value_location (Dwarf_Die *fu
265 }
266
267 aggregate:
268+ /* XXX TODO sometimes aggregates are returned in r0 (-mabi=aapcs) */
269 *locp = loc_aggregate;
270 return nloc_aggregate;
271 }
272@@ -125,3 +149,18 @@ arm_return_value_location (Dwarf_Die *fu
273 DWARF and might be valid. */
274 return -2;
275 }
276+
277+/* return location for -mabi=apcs-gnu -msoft-float */
278+int
279+arm_return_value_location_soft (Dwarf_Die *functypedie, const Dwarf_Op **locp)
280+{
281+ return arm_return_value_location_ (functypedie, locp, 1);
282+}
283+
284+/* return location for -mabi=apcs-gnu -mhard-float (current default) */
285+int
286+arm_return_value_location_hard (Dwarf_Die *functypedie, const Dwarf_Op **locp)
287+{
288+ return arm_return_value_location_ (functypedie, locp, 0);
289+}
290+
291Index: elfutils-0.164/libelf/elf.h
292===================================================================
293--- elfutils-0.164.orig/libelf/elf.h
294+++ elfutils-0.164/libelf/elf.h
295@@ -2450,6 +2450,9 @@ enum
296 #define EF_ARM_EABI_VER4 0x04000000
297 #define EF_ARM_EABI_VER5 0x05000000
298
299+/* EI_OSABI values */
300+#define ELFOSABI_ARM_AEABI 64 /* Contains symbol versioning. */
301+
302 /* Additional symbol types for Thumb. */
303 #define STT_ARM_TFUNC STT_LOPROC /* A Thumb function. */
304 #define STT_ARM_16BIT STT_HIPROC /* A Thumb label. */
305@@ -2467,12 +2470,19 @@ enum
306
307 /* Processor specific values for the Phdr p_type field. */
308 #define PT_ARM_EXIDX (PT_LOPROC + 1) /* ARM unwind segment. */
309+#define PT_ARM_UNWIND PT_ARM_EXIDX
310
311 /* Processor specific values for the Shdr sh_type field. */
312 #define SHT_ARM_EXIDX (SHT_LOPROC + 1) /* ARM unwind section. */
313 #define SHT_ARM_PREEMPTMAP (SHT_LOPROC + 2) /* Preemption details. */
314 #define SHT_ARM_ATTRIBUTES (SHT_LOPROC + 3) /* ARM attributes section. */
315
316+/* Processor specific values for the Dyn d_tag field. */
317+#define DT_ARM_RESERVED1 (DT_LOPROC + 0)
318+#define DT_ARM_SYMTABSZ (DT_LOPROC + 1)
319+#define DT_ARM_PREEMTMAB (DT_LOPROC + 2)
320+#define DT_ARM_RESERVED2 (DT_LOPROC + 3)
321+#define DT_ARM_NUM 4
322
323 /* AArch64 relocs. */
324
325@@ -2765,6 +2775,7 @@ enum
326 TLS block (LDR, STR). */
327 #define R_ARM_TLS_IE12GP 111 /* 12 bit GOT entry relative
328 to GOT origin (LDR). */
329+/* 112 - 127 private range */
330 #define R_ARM_ME_TOO 128 /* Obsolete. */
331 #define R_ARM_THM_TLS_DESCSEQ 129
332 #define R_ARM_THM_TLS_DESCSEQ16 129
333Index: elfutils-0.164/backends/libebl_arm.h
334===================================================================
335--- /dev/null
336+++ elfutils-0.164/backends/libebl_arm.h
337@@ -0,0 +1,9 @@
338+#ifndef _LIBEBL_ARM_H
339+#define _LIBEBL_ARM_H 1
340+
341+#include <libdw.h>
342+
343+extern int arm_return_value_location_soft(Dwarf_Die *, const Dwarf_Op **locp);
344+extern int arm_return_value_location_hard(Dwarf_Die *, const Dwarf_Op **locp);
345+
346+#endif
347Index: elfutils-0.164/tests/run-allregs.sh
348===================================================================
349--- elfutils-0.164.orig/tests/run-allregs.sh
350+++ elfutils-0.164/tests/run-allregs.sh
351@@ -2672,7 +2672,28 @@ integer registers:
352 13: sp (sp), address 32 bits
353 14: lr (lr), address 32 bits
354 15: pc (pc), address 32 bits
355- 128: spsr (spsr), unsigned 32 bits
356+ 144: r8_usr (r8_usr), signed 32 bits
357+ 145: r9_usr (r9_usr), signed 32 bits
358+ 146: r10_usr (r10_usr), signed 32 bits
359+ 147: r11_usr (r11_usr), signed 32 bits
360+ 148: r12_usr (r12_usr), signed 32 bits
361+ 149: r13_usr (r13_usr), signed 32 bits
362+ 150: r14_usr (r14_usr), signed 32 bits
363+ 151: r8_fiq (r8_fiq), signed 32 bits
364+ 152: r9_fiq (r9_fiq), signed 32 bits
365+ 153: r10_fiq (r10_fiq), signed 32 bits
366+ 154: r11_fiq (r11_fiq), signed 32 bits
367+ 155: r12_fiq (r12_fiq), signed 32 bits
368+ 156: r13_fiq (r13_fiq), signed 32 bits
369+ 157: r14_fiq (r14_fiq), signed 32 bits
370+ 158: r13_irq (r13_irq), signed 32 bits
371+ 159: r14_irq (r14_irq), signed 32 bits
372+ 160: r13_abt (r13_abt), signed 32 bits
373+ 161: r14_abt (r14_abt), signed 32 bits
374+ 162: r13_und (r13_und), signed 32 bits
375+ 163: r14_und (r14_und), signed 32 bits
376+ 164: r13_svc (r13_svc), signed 32 bits
377+ 165: r14_svc (r14_svc), signed 32 bits
378 FPA registers:
379 16: f0 (f0), float 96 bits
380 17: f1 (f1), float 96 bits
381@@ -2690,7 +2711,72 @@ FPA registers:
382 101: f5 (f5), float 96 bits
383 102: f6 (f6), float 96 bits
384 103: f7 (f7), float 96 bits
385+MMX registers:
386+ 104: wcgr0 (wcgr0), unsigned 32 bits
387+ 105: wcgr1 (wcgr1), unsigned 32 bits
388+ 106: wcgr2 (wcgr2), unsigned 32 bits
389+ 107: wcgr3 (wcgr3), unsigned 32 bits
390+ 108: wcgr4 (wcgr4), unsigned 32 bits
391+ 109: wcgr5 (wcgr5), unsigned 32 bits
392+ 110: wcgr6 (wcgr6), unsigned 32 bits
393+ 111: wcgr7 (wcgr7), unsigned 32 bits
394+ 112: wr0 (wr0), unsigned 64 bits
395+ 113: wr1 (wr1), unsigned 64 bits
396+ 114: wr2 (wr2), unsigned 64 bits
397+ 115: wr3 (wr3), unsigned 64 bits
398+ 116: wr4 (wr4), unsigned 64 bits
399+ 117: wr5 (wr5), unsigned 64 bits
400+ 118: wr6 (wr6), unsigned 64 bits
401+ 119: wr7 (wr7), unsigned 64 bits
402+ 120: wr8 (wr8), unsigned 64 bits
403+ 121: wr9 (wr9), unsigned 64 bits
404+ 122: wr10 (wr10), unsigned 64 bits
405+ 123: wr11 (wr11), unsigned 64 bits
406+ 124: wr12 (wr12), unsigned 64 bits
407+ 125: wr13 (wr13), unsigned 64 bits
408+ 126: wr14 (wr14), unsigned 64 bits
409+ 127: wr15 (wr15), unsigned 64 bits
410+ 192: wc0 (wc0), unsigned 32 bits
411+ 193: wc1 (wc1), unsigned 32 bits
412+ 194: wc2 (wc2), unsigned 32 bits
413+ 195: wc3 (wc3), unsigned 32 bits
414+ 196: wc4 (wc4), unsigned 32 bits
415+ 197: wc5 (wc5), unsigned 32 bits
416+ 198: wc6 (wc6), unsigned 32 bits
417+ 199: wc7 (wc7), unsigned 32 bits
418 VFP registers:
419+ 64: s0 (s0), float 32 bits
420+ 65: s1 (s1), float 32 bits
421+ 66: s2 (s2), float 32 bits
422+ 67: s3 (s3), float 32 bits
423+ 68: s4 (s4), float 32 bits
424+ 69: s5 (s5), float 32 bits
425+ 70: s6 (s6), float 32 bits
426+ 71: s7 (s7), float 32 bits
427+ 72: s8 (s8), float 32 bits
428+ 73: s9 (s9), float 32 bits
429+ 74: s10 (s10), float 32 bits
430+ 75: s11 (s11), float 32 bits
431+ 76: s12 (s12), float 32 bits
432+ 77: s13 (s13), float 32 bits
433+ 78: s14 (s14), float 32 bits
434+ 79: s15 (s15), float 32 bits
435+ 80: s16 (s16), float 32 bits
436+ 81: s17 (s17), float 32 bits
437+ 82: s18 (s18), float 32 bits
438+ 83: s19 (s19), float 32 bits
439+ 84: s20 (s20), float 32 bits
440+ 85: s21 (s21), float 32 bits
441+ 86: s22 (s22), float 32 bits
442+ 87: s23 (s23), float 32 bits
443+ 88: s24 (s24), float 32 bits
444+ 89: s25 (s25), float 32 bits
445+ 90: s26 (s26), float 32 bits
446+ 91: s27 (s27), float 32 bits
447+ 92: s28 (s28), float 32 bits
448+ 93: s29 (s29), float 32 bits
449+ 94: s30 (s30), float 32 bits
450+ 95: s31 (s31), float 32 bits
451 256: d0 (d0), float 64 bits
452 257: d1 (d1), float 64 bits
453 258: d2 (d2), float 64 bits
454@@ -2723,6 +2809,13 @@ VFP registers:
455 285: d29 (d29), float 64 bits
456 286: d30 (d30), float 64 bits
457 287: d31 (d31), float 64 bits
458+state registers:
459+ 128: spsr (spsr), unsigned 32 bits
460+ 129: spsr_fiq (spsr_fiq), unsigned 32 bits
461+ 130: spsr_irq (spsr_irq), unsigned 32 bits
462+ 131: spsr_abt (spsr_abt), unsigned 32 bits
463+ 132: spsr_und (spsr_und), unsigned 32 bits
464+ 133: spsr_svc (spsr_svc), unsigned 32 bits
465 EOF
466
467 # See run-readelf-mixed-corenote.sh for instructions to regenerate
468Index: elfutils-0.164/tests/run-readelf-mixed-corenote.sh
469===================================================================
470--- elfutils-0.164.orig/tests/run-readelf-mixed-corenote.sh
471+++ elfutils-0.164/tests/run-readelf-mixed-corenote.sh
472@@ -31,12 +31,11 @@ Note segment of 892 bytes at offset 0x27
473 pid: 11087, ppid: 11063, pgrp: 11087, sid: 11063
474 utime: 0.000000, stime: 0.010000, cutime: 0.000000, cstime: 0.000000
475 orig_r0: -1, fpvalid: 1
476- r0: 1 r1: -1091672508 r2: -1091672500
477- r3: 0 r4: 0 r5: 0
478- r6: 33728 r7: 0 r8: 0
479- r9: 0 r10: -1225703496 r11: -1091672844
480- r12: 0 sp: 0xbeee64f4 lr: 0xb6dc3f48
481- pc: 0x00008500 spsr: 0x60000010
482+ r0: 1 r1: -1091672508 r2: -1091672500 r3: 0
483+ r4: 0 r5: 0 r6: 33728 r7: 0
484+ r8: 0 r9: 0 r10: -1225703496 r11: -1091672844
485+ r12: 0 sp: 0xbeee64f4 lr: 0xb6dc3f48 pc: 0x00008500
486+ spsr: 0x60000010
487 CORE 124 PRPSINFO
488 state: 0, sname: R, zomb: 0, nice: 0, flag: 0x00400500
489 uid: 0, gid: 0, pid: 11087, ppid: 11063, pgrp: 11087, sid: 11063
490Index: elfutils-0.164/tests/run-addrcfi.sh
491===================================================================
492--- elfutils-0.164.orig/tests/run-addrcfi.sh
493+++ elfutils-0.164/tests/run-addrcfi.sh
494@@ -3554,6 +3554,38 @@ dwarf_cfi_addrframe (.eh_frame): no matc
495 FPA reg21 (f5): undefined
496 FPA reg22 (f6): undefined
497 FPA reg23 (f7): undefined
498+ VFP reg64 (s0): undefined
499+ VFP reg65 (s1): undefined
500+ VFP reg66 (s2): undefined
501+ VFP reg67 (s3): undefined
502+ VFP reg68 (s4): undefined
503+ VFP reg69 (s5): undefined
504+ VFP reg70 (s6): undefined
505+ VFP reg71 (s7): undefined
506+ VFP reg72 (s8): undefined
507+ VFP reg73 (s9): undefined
508+ VFP reg74 (s10): undefined
509+ VFP reg75 (s11): undefined
510+ VFP reg76 (s12): undefined
511+ VFP reg77 (s13): undefined
512+ VFP reg78 (s14): undefined
513+ VFP reg79 (s15): undefined
514+ VFP reg80 (s16): undefined
515+ VFP reg81 (s17): undefined
516+ VFP reg82 (s18): undefined
517+ VFP reg83 (s19): undefined
518+ VFP reg84 (s20): undefined
519+ VFP reg85 (s21): undefined
520+ VFP reg86 (s22): undefined
521+ VFP reg87 (s23): undefined
522+ VFP reg88 (s24): undefined
523+ VFP reg89 (s25): undefined
524+ VFP reg90 (s26): undefined
525+ VFP reg91 (s27): undefined
526+ VFP reg92 (s28): undefined
527+ VFP reg93 (s29): undefined
528+ VFP reg94 (s30): undefined
529+ VFP reg95 (s31): undefined
530 FPA reg96 (f0): undefined
531 FPA reg97 (f1): undefined
532 FPA reg98 (f2): undefined
533@@ -3562,7 +3594,66 @@ dwarf_cfi_addrframe (.eh_frame): no matc
534 FPA reg101 (f5): undefined
535 FPA reg102 (f6): undefined
536 FPA reg103 (f7): undefined
537- integer reg128 (spsr): undefined
538+ MMX reg104 (wcgr0): undefined
539+ MMX reg105 (wcgr1): undefined
540+ MMX reg106 (wcgr2): undefined
541+ MMX reg107 (wcgr3): undefined
542+ MMX reg108 (wcgr4): undefined
543+ MMX reg109 (wcgr5): undefined
544+ MMX reg110 (wcgr6): undefined
545+ MMX reg111 (wcgr7): undefined
546+ MMX reg112 (wr0): undefined
547+ MMX reg113 (wr1): undefined
548+ MMX reg114 (wr2): undefined
549+ MMX reg115 (wr3): undefined
550+ MMX reg116 (wr4): undefined
551+ MMX reg117 (wr5): undefined
552+ MMX reg118 (wr6): undefined
553+ MMX reg119 (wr7): undefined
554+ MMX reg120 (wr8): undefined
555+ MMX reg121 (wr9): undefined
556+ MMX reg122 (wr10): undefined
557+ MMX reg123 (wr11): undefined
558+ MMX reg124 (wr12): undefined
559+ MMX reg125 (wr13): undefined
560+ MMX reg126 (wr14): undefined
561+ MMX reg127 (wr15): undefined
562+ state reg128 (spsr): undefined
563+ state reg129 (spsr_fiq): undefined
564+ state reg130 (spsr_irq): undefined
565+ state reg131 (spsr_abt): undefined
566+ state reg132 (spsr_und): undefined
567+ state reg133 (spsr_svc): undefined
568+ integer reg144 (r8_usr): undefined
569+ integer reg145 (r9_usr): undefined
570+ integer reg146 (r10_usr): undefined
571+ integer reg147 (r11_usr): undefined
572+ integer reg148 (r12_usr): undefined
573+ integer reg149 (r13_usr): undefined
574+ integer reg150 (r14_usr): undefined
575+ integer reg151 (r8_fiq): undefined
576+ integer reg152 (r9_fiq): undefined
577+ integer reg153 (r10_fiq): undefined
578+ integer reg154 (r11_fiq): undefined
579+ integer reg155 (r12_fiq): undefined
580+ integer reg156 (r13_fiq): undefined
581+ integer reg157 (r14_fiq): undefined
582+ integer reg158 (r13_irq): undefined
583+ integer reg159 (r14_irq): undefined
584+ integer reg160 (r13_abt): undefined
585+ integer reg161 (r14_abt): undefined
586+ integer reg162 (r13_und): undefined
587+ integer reg163 (r14_und): undefined
588+ integer reg164 (r13_svc): undefined
589+ integer reg165 (r14_svc): undefined
590+ MMX reg192 (wc0): undefined
591+ MMX reg193 (wc1): undefined
592+ MMX reg194 (wc2): undefined
593+ MMX reg195 (wc3): undefined
594+ MMX reg196 (wc4): undefined
595+ MMX reg197 (wc5): undefined
596+ MMX reg198 (wc6): undefined
597+ MMX reg199 (wc7): undefined
598 VFP reg256 (d0): undefined
599 VFP reg257 (d1): undefined
600 VFP reg258 (d2): undefined
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2026-04-22 05:46:48 +0000