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-rw-r--r--meta/recipes-devtools/elfutils/elfutils-0.158/arm_backend.diff603
1 files changed, 603 insertions, 0 deletions
diff --git a/meta/recipes-devtools/elfutils/elfutils-0.158/arm_backend.diff b/meta/recipes-devtools/elfutils/elfutils-0.158/arm_backend.diff
new file mode 100644
index 0000000000..fc3d6dc3f4
--- /dev/null
+++ b/meta/recipes-devtools/elfutils/elfutils-0.158/arm_backend.diff
@@ -0,0 +1,603 @@
1Index: elfutils-0.158/backends/arm_init.c
2===================================================================
3--- elfutils-0.158.orig/backends/arm_init.c 2014-04-21 11:13:24.378519252 +0000
4+++ elfutils-0.158/backends/arm_init.c 2014-04-21 11:13:24.374519343 +0000
5@@ -35,21 +35,32 @@
6 #define RELOC_PREFIX R_ARM_
7 #include "libebl_CPU.h"
8
9+#include "libebl_arm.h"
10+
11 /* This defines the common reloc hooks based on arm_reloc.def. */
12 #include "common-reloc.c"
13
14
15 const char *
16 arm_init (elf, machine, eh, ehlen)
17- Elf *elf __attribute__ ((unused));
18+ Elf *elf;
19 GElf_Half machine __attribute__ ((unused));
20 Ebl *eh;
21 size_t ehlen;
22 {
23+ int soft_float = 0;
24+
25 /* Check whether the Elf_BH object has a sufficent size. */
26 if (ehlen < sizeof (Ebl))
27 return NULL;
28
29+ if (elf) {
30+ GElf_Ehdr ehdr_mem;
31+ GElf_Ehdr *ehdr = gelf_getehdr (elf, &ehdr_mem);
32+ if (ehdr && (ehdr->e_flags & EF_ARM_SOFT_FLOAT))
33+ soft_float = 1;
34+ }
35+
36 /* We handle it. */
37 eh->name = "ARM";
38 arm_init_reloc (eh);
39@@ -61,7 +72,10 @@
40 HOOK (eh, core_note);
41 HOOK (eh, auxv_info);
42 HOOK (eh, check_object_attribute);
43- HOOK (eh, return_value_location);
44+ if (soft_float)
45+ eh->return_value_location = arm_return_value_location_soft;
46+ else
47+ eh->return_value_location = arm_return_value_location_hard;
48 HOOK (eh, abi_cfi);
49
50 return MODVERSION;
51Index: elfutils-0.158/backends/arm_regs.c
52===================================================================
53--- elfutils-0.158.orig/backends/arm_regs.c 2014-04-21 11:13:24.378519252 +0000
54+++ elfutils-0.158/backends/arm_regs.c 2014-04-21 11:13:24.374519343 +0000
55@@ -31,6 +31,7 @@
56 #endif
57
58 #include <string.h>
59+#include <stdio.h>
60 #include <dwarf.h>
61
62 #define BACKEND arm_
63@@ -76,6 +77,9 @@
64 break;
65
66 case 16 + 0 ... 16 + 7:
67+ /* AADWARF says that there are no registers in that range,
68+ * but gcc maps FPA registers here
69+ */
70 regno += 96 - 16;
71 /* Fall through. */
72 case 96 + 0 ... 96 + 7:
73@@ -87,11 +91,139 @@
74 namelen = 2;
75 break;
76
77+ case 64 + 0 ... 64 + 9:
78+ *setname = "VFP";
79+ *bits = 32;
80+ *type = DW_ATE_float;
81+ name[0] = 's';
82+ name[1] = regno - 64 + '0';
83+ namelen = 2;
84+ break;
85+
86+ case 64 + 10 ... 64 + 31:
87+ *setname = "VFP";
88+ *bits = 32;
89+ *type = DW_ATE_float;
90+ name[0] = 's';
91+ name[1] = (regno - 64) / 10 + '0';
92+ name[2] = (regno - 64) % 10 + '0';
93+ namelen = 3;
94+ break;
95+
96+ case 104 + 0 ... 104 + 7:
97+ /* XXX TODO:
98+ * This can be either intel wireless MMX general purpose/control
99+ * registers or xscale accumulator, which have different usage.
100+ * We only have the intel wireless MMX here now.
101+ * The name needs to be changed for the xscale accumulator too. */
102+ *setname = "MMX";
103+ *type = DW_ATE_unsigned;
104+ *bits = 32;
105+ memcpy(name, "wcgr", 4);
106+ name[4] = regno - 104 + '0';
107+ namelen = 5;
108+ break;
109+
110+ case 112 + 0 ... 112 + 9:
111+ *setname = "MMX";
112+ *type = DW_ATE_unsigned;
113+ *bits = 64;
114+ name[0] = 'w';
115+ name[1] = 'r';
116+ name[2] = regno - 112 + '0';
117+ namelen = 3;
118+ break;
119+
120+ case 112 + 10 ... 112 + 15:
121+ *setname = "MMX";
122+ *type = DW_ATE_unsigned;
123+ *bits = 64;
124+ name[0] = 'w';
125+ name[1] = 'r';
126+ name[2] = '1';
127+ name[3] = regno - 112 - 10 + '0';
128+ namelen = 4;
129+ break;
130+
131 case 128:
132+ *setname = "state";
133 *type = DW_ATE_unsigned;
134 return stpcpy (name, "spsr") + 1 - name;
135
136+ case 129:
137+ *setname = "state";
138+ *type = DW_ATE_unsigned;
139+ return stpcpy(name, "spsr_fiq") + 1 - name;
140+
141+ case 130:
142+ *setname = "state";
143+ *type = DW_ATE_unsigned;
144+ return stpcpy(name, "spsr_irq") + 1 - name;
145+
146+ case 131:
147+ *setname = "state";
148+ *type = DW_ATE_unsigned;
149+ return stpcpy(name, "spsr_abt") + 1 - name;
150+
151+ case 132:
152+ *setname = "state";
153+ *type = DW_ATE_unsigned;
154+ return stpcpy(name, "spsr_und") + 1 - name;
155+
156+ case 133:
157+ *setname = "state";
158+ *type = DW_ATE_unsigned;
159+ return stpcpy(name, "spsr_svc") + 1 - name;
160+
161+ case 144 ... 150:
162+ *setname = "integer";
163+ *type = DW_ATE_signed;
164+ *bits = 32;
165+ return sprintf(name, "r%d_usr", regno - 144 + 8) + 1;
166+
167+ case 151 ... 157:
168+ *setname = "integer";
169+ *type = DW_ATE_signed;
170+ *bits = 32;
171+ return sprintf(name, "r%d_fiq", regno - 151 + 8) + 1;
172+
173+ case 158 ... 159:
174+ *setname = "integer";
175+ *type = DW_ATE_signed;
176+ *bits = 32;
177+ return sprintf(name, "r%d_irq", regno - 158 + 13) + 1;
178+
179+ case 160 ... 161:
180+ *setname = "integer";
181+ *type = DW_ATE_signed;
182+ *bits = 32;
183+ return sprintf(name, "r%d_abt", regno - 160 + 13) + 1;
184+
185+ case 162 ... 163:
186+ *setname = "integer";
187+ *type = DW_ATE_signed;
188+ *bits = 32;
189+ return sprintf(name, "r%d_und", regno - 162 + 13) + 1;
190+
191+ case 164 ... 165:
192+ *setname = "integer";
193+ *type = DW_ATE_signed;
194+ *bits = 32;
195+ return sprintf(name, "r%d_svc", regno - 164 + 13) + 1;
196+
197+ case 192 ... 199:
198+ *setname = "MMX";
199+ *bits = 32;
200+ *type = DW_ATE_unsigned;
201+ name[0] = 'w';
202+ name[1] = 'c';
203+ name[2] = regno - 192 + '0';
204+ namelen = 3;
205+ break;
206+
207 case 256 + 0 ... 256 + 9:
208+ /* XXX TODO: Neon also uses those registers and can contain
209+ * both float and integers */
210 *setname = "VFP";
211 *type = DW_ATE_float;
212 *bits = 64;
213Index: elfutils-0.158/backends/arm_retval.c
214===================================================================
215--- elfutils-0.158.orig/backends/arm_retval.c 2014-04-21 11:13:24.378519252 +0000
216+++ elfutils-0.158/backends/arm_retval.c 2014-04-21 11:13:24.374519343 +0000
217@@ -48,6 +48,13 @@
218 #define nloc_intreg 1
219 #define nloc_intregs(n) (2 * (n))
220
221+/* f1 */ /* XXX TODO: f0 can also have number 96 if program was compiled with -mabi=aapcs */
222+static const Dwarf_Op loc_fpreg[] =
223+ {
224+ { .atom = DW_OP_reg16 },
225+ };
226+#define nloc_fpreg 1
227+
228 /* The return value is a structure and is actually stored in stack space
229 passed in a hidden argument by the caller. But, the compiler
230 helpfully returns the address of that space in r0. */
231@@ -58,8 +65,9 @@
232 #define nloc_aggregate 1
233
234
235-int
236-arm_return_value_location (Dwarf_Die *functypedie, const Dwarf_Op **locp)
237+static int
238+arm_return_value_location_ (Dwarf_Die *functypedie, const Dwarf_Op **locp,
239+ int soft_float)
240 {
241 /* Start with the function's type, and get the DW_AT_type attribute,
242 which is the type of the return value. */
243@@ -112,14 +120,31 @@
244 else
245 return -1;
246 }
247+ if (tag == DW_TAG_base_type)
248+ {
249+ Dwarf_Word encoding;
250+ if (dwarf_formudata (dwarf_attr_integrate (typedie, DW_AT_encoding,
251+ &attr_mem), &encoding) != 0)
252+ return -1;
253+
254+ if ((encoding == DW_ATE_float) && !soft_float)
255+ {
256+ *locp = loc_fpreg;
257+ if (size <= 8)
258+ return nloc_fpreg;
259+ goto aggregate;
260+ }
261+ }
262 if (size <= 16)
263 {
264 intreg:
265 *locp = loc_intreg;
266 return size <= 4 ? nloc_intreg : nloc_intregs ((size + 3) / 4);
267 }
268+ /* fall through. */
269
270 aggregate:
271+ /* XXX TODO sometimes aggregates are returned in r0 (-mabi=aapcs) */
272 *locp = loc_aggregate;
273 return nloc_aggregate;
274
275@@ -138,3 +163,18 @@
276 DWARF and might be valid. */
277 return -2;
278 }
279+
280+/* return location for -mabi=apcs-gnu -msoft-float */
281+int
282+arm_return_value_location_soft (Dwarf_Die *functypedie, const Dwarf_Op **locp)
283+{
284+ return arm_return_value_location_ (functypedie, locp, 1);
285+}
286+
287+/* return location for -mabi=apcs-gnu -mhard-float (current default) */
288+int
289+arm_return_value_location_hard (Dwarf_Die *functypedie, const Dwarf_Op **locp)
290+{
291+ return arm_return_value_location_ (functypedie, locp, 0);
292+}
293+
294Index: elfutils-0.158/libelf/elf.h
295===================================================================
296--- elfutils-0.158.orig/libelf/elf.h 2014-04-21 11:13:24.378519252 +0000
297+++ elfutils-0.158/libelf/elf.h 2014-04-21 11:13:24.374519343 +0000
298@@ -2318,6 +2318,9 @@
299 #define EF_ARM_EABI_VER4 0x04000000
300 #define EF_ARM_EABI_VER5 0x05000000
301
302+/* EI_OSABI values */
303+#define ELFOSABI_ARM_AEABI 64 /* Contains symbol versioning. */
304+
305 /* Additional symbol types for Thumb. */
306 #define STT_ARM_TFUNC STT_LOPROC /* A Thumb function. */
307 #define STT_ARM_16BIT STT_HIPROC /* A Thumb label. */
308@@ -2335,12 +2338,19 @@
309
310 /* Processor specific values for the Phdr p_type field. */
311 #define PT_ARM_EXIDX (PT_LOPROC + 1) /* ARM unwind segment. */
312+#define PT_ARM_UNWIND PT_ARM_EXIDX
313
314 /* Processor specific values for the Shdr sh_type field. */
315 #define SHT_ARM_EXIDX (SHT_LOPROC + 1) /* ARM unwind section. */
316 #define SHT_ARM_PREEMPTMAP (SHT_LOPROC + 2) /* Preemption details. */
317 #define SHT_ARM_ATTRIBUTES (SHT_LOPROC + 3) /* ARM attributes section. */
318
319+/* Processor specific values for the Dyn d_tag field. */
320+#define DT_ARM_RESERVED1 (DT_LOPROC + 0)
321+#define DT_ARM_SYMTABSZ (DT_LOPROC + 1)
322+#define DT_ARM_PREEMTMAB (DT_LOPROC + 2)
323+#define DT_ARM_RESERVED2 (DT_LOPROC + 3)
324+#define DT_ARM_NUM 4
325
326 /* AArch64 relocs. */
327
328@@ -2619,6 +2629,7 @@
329 TLS block (LDR, STR). */
330 #define R_ARM_TLS_IE12GP 111 /* 12 bit GOT entry relative
331 to GOT origin (LDR). */
332+/* 112 - 127 private range */
333 #define R_ARM_ME_TOO 128 /* Obsolete. */
334 #define R_ARM_THM_TLS_DESCSEQ 129
335 #define R_ARM_THM_TLS_DESCSEQ16 129
336Index: elfutils-0.158/backends/libebl_arm.h
337===================================================================
338--- /dev/null 1970-01-01 00:00:00.000000000 +0000
339+++ elfutils-0.158/backends/libebl_arm.h 2014-04-21 11:13:24.374519343 +0000
340@@ -0,0 +1,9 @@
341+#ifndef _LIBEBL_ARM_H
342+#define _LIBEBL_ARM_H 1
343+
344+#include <libdw.h>
345+
346+extern int arm_return_value_location_soft(Dwarf_Die *, const Dwarf_Op **locp);
347+extern int arm_return_value_location_hard(Dwarf_Die *, const Dwarf_Op **locp);
348+
349+#endif
350Index: elfutils-0.158/tests/run-allregs.sh
351===================================================================
352--- elfutils-0.158.orig/tests/run-allregs.sh 2014-04-21 11:13:24.378519252 +0000
353+++ elfutils-0.158/tests/run-allregs.sh 2014-04-21 11:13:24.378519252 +0000
354@@ -2671,7 +2671,28 @@
355 13: sp (sp), address 32 bits
356 14: lr (lr), address 32 bits
357 15: pc (pc), address 32 bits
358- 128: spsr (spsr), unsigned 32 bits
359+ 144: r8_usr (r8_usr), signed 32 bits
360+ 145: r9_usr (r9_usr), signed 32 bits
361+ 146: r10_usr (r10_usr), signed 32 bits
362+ 147: r11_usr (r11_usr), signed 32 bits
363+ 148: r12_usr (r12_usr), signed 32 bits
364+ 149: r13_usr (r13_usr), signed 32 bits
365+ 150: r14_usr (r14_usr), signed 32 bits
366+ 151: r8_fiq (r8_fiq), signed 32 bits
367+ 152: r9_fiq (r9_fiq), signed 32 bits
368+ 153: r10_fiq (r10_fiq), signed 32 bits
369+ 154: r11_fiq (r11_fiq), signed 32 bits
370+ 155: r12_fiq (r12_fiq), signed 32 bits
371+ 156: r13_fiq (r13_fiq), signed 32 bits
372+ 157: r14_fiq (r14_fiq), signed 32 bits
373+ 158: r13_irq (r13_irq), signed 32 bits
374+ 159: r14_irq (r14_irq), signed 32 bits
375+ 160: r13_abt (r13_abt), signed 32 bits
376+ 161: r14_abt (r14_abt), signed 32 bits
377+ 162: r13_und (r13_und), signed 32 bits
378+ 163: r14_und (r14_und), signed 32 bits
379+ 164: r13_svc (r13_svc), signed 32 bits
380+ 165: r14_svc (r14_svc), signed 32 bits
381 FPA registers:
382 16: f0 (f0), float 96 bits
383 17: f1 (f1), float 96 bits
384@@ -2689,7 +2710,72 @@
385 101: f5 (f5), float 96 bits
386 102: f6 (f6), float 96 bits
387 103: f7 (f7), float 96 bits
388+MMX registers:
389+ 104: wcgr0 (wcgr0), unsigned 32 bits
390+ 105: wcgr1 (wcgr1), unsigned 32 bits
391+ 106: wcgr2 (wcgr2), unsigned 32 bits
392+ 107: wcgr3 (wcgr3), unsigned 32 bits
393+ 108: wcgr4 (wcgr4), unsigned 32 bits
394+ 109: wcgr5 (wcgr5), unsigned 32 bits
395+ 110: wcgr6 (wcgr6), unsigned 32 bits
396+ 111: wcgr7 (wcgr7), unsigned 32 bits
397+ 112: wr0 (wr0), unsigned 64 bits
398+ 113: wr1 (wr1), unsigned 64 bits
399+ 114: wr2 (wr2), unsigned 64 bits
400+ 115: wr3 (wr3), unsigned 64 bits
401+ 116: wr4 (wr4), unsigned 64 bits
402+ 117: wr5 (wr5), unsigned 64 bits
403+ 118: wr6 (wr6), unsigned 64 bits
404+ 119: wr7 (wr7), unsigned 64 bits
405+ 120: wr8 (wr8), unsigned 64 bits
406+ 121: wr9 (wr9), unsigned 64 bits
407+ 122: wr10 (wr10), unsigned 64 bits
408+ 123: wr11 (wr11), unsigned 64 bits
409+ 124: wr12 (wr12), unsigned 64 bits
410+ 125: wr13 (wr13), unsigned 64 bits
411+ 126: wr14 (wr14), unsigned 64 bits
412+ 127: wr15 (wr15), unsigned 64 bits
413+ 192: wc0 (wc0), unsigned 32 bits
414+ 193: wc1 (wc1), unsigned 32 bits
415+ 194: wc2 (wc2), unsigned 32 bits
416+ 195: wc3 (wc3), unsigned 32 bits
417+ 196: wc4 (wc4), unsigned 32 bits
418+ 197: wc5 (wc5), unsigned 32 bits
419+ 198: wc6 (wc6), unsigned 32 bits
420+ 199: wc7 (wc7), unsigned 32 bits
421 VFP registers:
422+ 64: s0 (s0), float 32 bits
423+ 65: s1 (s1), float 32 bits
424+ 66: s2 (s2), float 32 bits
425+ 67: s3 (s3), float 32 bits
426+ 68: s4 (s4), float 32 bits
427+ 69: s5 (s5), float 32 bits
428+ 70: s6 (s6), float 32 bits
429+ 71: s7 (s7), float 32 bits
430+ 72: s8 (s8), float 32 bits
431+ 73: s9 (s9), float 32 bits
432+ 74: s10 (s10), float 32 bits
433+ 75: s11 (s11), float 32 bits
434+ 76: s12 (s12), float 32 bits
435+ 77: s13 (s13), float 32 bits
436+ 78: s14 (s14), float 32 bits
437+ 79: s15 (s15), float 32 bits
438+ 80: s16 (s16), float 32 bits
439+ 81: s17 (s17), float 32 bits
440+ 82: s18 (s18), float 32 bits
441+ 83: s19 (s19), float 32 bits
442+ 84: s20 (s20), float 32 bits
443+ 85: s21 (s21), float 32 bits
444+ 86: s22 (s22), float 32 bits
445+ 87: s23 (s23), float 32 bits
446+ 88: s24 (s24), float 32 bits
447+ 89: s25 (s25), float 32 bits
448+ 90: s26 (s26), float 32 bits
449+ 91: s27 (s27), float 32 bits
450+ 92: s28 (s28), float 32 bits
451+ 93: s29 (s29), float 32 bits
452+ 94: s30 (s30), float 32 bits
453+ 95: s31 (s31), float 32 bits
454 256: d0 (d0), float 64 bits
455 257: d1 (d1), float 64 bits
456 258: d2 (d2), float 64 bits
457@@ -2722,6 +2808,13 @@
458 285: d29 (d29), float 64 bits
459 286: d30 (d30), float 64 bits
460 287: d31 (d31), float 64 bits
461+state registers:
462+ 128: spsr (spsr), unsigned 32 bits
463+ 129: spsr_fiq (spsr_fiq), unsigned 32 bits
464+ 130: spsr_irq (spsr_irq), unsigned 32 bits
465+ 131: spsr_abt (spsr_abt), unsigned 32 bits
466+ 132: spsr_und (spsr_und), unsigned 32 bits
467+ 133: spsr_svc (spsr_svc), unsigned 32 bits
468 EOF
469
470 # See run-readelf-mixed-corenote.sh for instructions to regenerate
471Index: elfutils-0.158/tests/run-readelf-mixed-corenote.sh
472===================================================================
473--- elfutils-0.158.orig/tests/run-readelf-mixed-corenote.sh 2014-04-21 11:13:24.378519252 +0000
474+++ elfutils-0.158/tests/run-readelf-mixed-corenote.sh 2014-04-21 11:13:24.378519252 +0000
475@@ -30,12 +30,11 @@
476 pid: 11087, ppid: 11063, pgrp: 11087, sid: 11063
477 utime: 0.000000, stime: 0.010000, cutime: 0.000000, cstime: 0.000000
478 orig_r0: -1, fpvalid: 1
479- r0: 1 r1: -1091672508 r2: -1091672500
480- r3: 0 r4: 0 r5: 0
481- r6: 33728 r7: 0 r8: 0
482- r9: 0 r10: -1225703496 r11: -1091672844
483- r12: 0 sp: 0xbeee64f4 lr: 0xb6dc3f48
484- pc: 0x00008500 spsr: 0x60000010
485+ r0: 1 r1: -1091672508 r2: -1091672500 r3: 0
486+ r4: 0 r5: 0 r6: 33728 r7: 0
487+ r8: 0 r9: 0 r10: -1225703496 r11: -1091672844
488+ r12: 0 sp: 0xbeee64f4 lr: 0xb6dc3f48 pc: 0x00008500
489+ spsr: 0x60000010
490 CORE 124 PRPSINFO
491 state: 0, sname: R, zomb: 0, nice: 0, flag: 0x00400500
492 uid: 0, gid: 0, pid: 11087, ppid: 11063, pgrp: 11087, sid: 11063
493Index: elfutils-0.158/tests/run-addrcfi.sh
494===================================================================
495--- elfutils-0.158.orig/tests/run-addrcfi.sh 2014-04-21 11:13:24.378519252 +0000
496+++ elfutils-0.158/tests/run-addrcfi.sh 2014-04-21 11:13:24.378519252 +0000
497@@ -2530,6 +2530,38 @@
498 FPA reg21 (f5): undefined
499 FPA reg22 (f6): undefined
500 FPA reg23 (f7): undefined
501+ VFP reg64 (s0): undefined
502+ VFP reg65 (s1): undefined
503+ VFP reg66 (s2): undefined
504+ VFP reg67 (s3): undefined
505+ VFP reg68 (s4): undefined
506+ VFP reg69 (s5): undefined
507+ VFP reg70 (s6): undefined
508+ VFP reg71 (s7): undefined
509+ VFP reg72 (s8): undefined
510+ VFP reg73 (s9): undefined
511+ VFP reg74 (s10): undefined
512+ VFP reg75 (s11): undefined
513+ VFP reg76 (s12): undefined
514+ VFP reg77 (s13): undefined
515+ VFP reg78 (s14): undefined
516+ VFP reg79 (s15): undefined
517+ VFP reg80 (s16): undefined
518+ VFP reg81 (s17): undefined
519+ VFP reg82 (s18): undefined
520+ VFP reg83 (s19): undefined
521+ VFP reg84 (s20): undefined
522+ VFP reg85 (s21): undefined
523+ VFP reg86 (s22): undefined
524+ VFP reg87 (s23): undefined
525+ VFP reg88 (s24): undefined
526+ VFP reg89 (s25): undefined
527+ VFP reg90 (s26): undefined
528+ VFP reg91 (s27): undefined
529+ VFP reg92 (s28): undefined
530+ VFP reg93 (s29): undefined
531+ VFP reg94 (s30): undefined
532+ VFP reg95 (s31): undefined
533 FPA reg96 (f0): undefined
534 FPA reg97 (f1): undefined
535 FPA reg98 (f2): undefined
536@@ -2538,7 +2570,66 @@
537 FPA reg101 (f5): undefined
538 FPA reg102 (f6): undefined
539 FPA reg103 (f7): undefined
540- integer reg128 (spsr): undefined
541+ MMX reg104 (wcgr0): undefined
542+ MMX reg105 (wcgr1): undefined
543+ MMX reg106 (wcgr2): undefined
544+ MMX reg107 (wcgr3): undefined
545+ MMX reg108 (wcgr4): undefined
546+ MMX reg109 (wcgr5): undefined
547+ MMX reg110 (wcgr6): undefined
548+ MMX reg111 (wcgr7): undefined
549+ MMX reg112 (wr0): undefined
550+ MMX reg113 (wr1): undefined
551+ MMX reg114 (wr2): undefined
552+ MMX reg115 (wr3): undefined
553+ MMX reg116 (wr4): undefined
554+ MMX reg117 (wr5): undefined
555+ MMX reg118 (wr6): undefined
556+ MMX reg119 (wr7): undefined
557+ MMX reg120 (wr8): undefined
558+ MMX reg121 (wr9): undefined
559+ MMX reg122 (wr10): undefined
560+ MMX reg123 (wr11): undefined
561+ MMX reg124 (wr12): undefined
562+ MMX reg125 (wr13): undefined
563+ MMX reg126 (wr14): undefined
564+ MMX reg127 (wr15): undefined
565+ state reg128 (spsr): undefined
566+ state reg129 (spsr_fiq): undefined
567+ state reg130 (spsr_irq): undefined
568+ state reg131 (spsr_abt): undefined
569+ state reg132 (spsr_und): undefined
570+ state reg133 (spsr_svc): undefined
571+ integer reg144 (r8_usr): undefined
572+ integer reg145 (r9_usr): undefined
573+ integer reg146 (r10_usr): undefined
574+ integer reg147 (r11_usr): undefined
575+ integer reg148 (r12_usr): undefined
576+ integer reg149 (r13_usr): undefined
577+ integer reg150 (r14_usr): undefined
578+ integer reg151 (r8_fiq): undefined
579+ integer reg152 (r9_fiq): undefined
580+ integer reg153 (r10_fiq): undefined
581+ integer reg154 (r11_fiq): undefined
582+ integer reg155 (r12_fiq): undefined
583+ integer reg156 (r13_fiq): undefined
584+ integer reg157 (r14_fiq): undefined
585+ integer reg158 (r13_irq): undefined
586+ integer reg159 (r14_irq): undefined
587+ integer reg160 (r13_abt): undefined
588+ integer reg161 (r14_abt): undefined
589+ integer reg162 (r13_und): undefined
590+ integer reg163 (r14_und): undefined
591+ integer reg164 (r13_svc): undefined
592+ integer reg165 (r14_svc): undefined
593+ MMX reg192 (wc0): undefined
594+ MMX reg193 (wc1): undefined
595+ MMX reg194 (wc2): undefined
596+ MMX reg195 (wc3): undefined
597+ MMX reg196 (wc4): undefined
598+ MMX reg197 (wc5): undefined
599+ MMX reg198 (wc6): undefined
600+ MMX reg199 (wc7): undefined
601 VFP reg256 (d0): undefined
602 VFP reg257 (d1): undefined
603 VFP reg258 (d2): undefined
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2026-01-08 15:56:41 +0000