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-rw-r--r--meta/packages/uboot/u-boot-mkimage-openmoko-native/uboot-s3c2443.patch256
1 files changed, 0 insertions, 256 deletions
diff --git a/meta/packages/uboot/u-boot-mkimage-openmoko-native/uboot-s3c2443.patch b/meta/packages/uboot/u-boot-mkimage-openmoko-native/uboot-s3c2443.patch
deleted file mode 100644
index 62ae5592ab..0000000000
--- a/meta/packages/uboot/u-boot-mkimage-openmoko-native/uboot-s3c2443.patch
+++ /dev/null
@@ -1,256 +0,0 @@
1Index: u-boot/cpu/arm920t/start.S
2===================================================================
3--- u-boot.orig/cpu/arm920t/start.S
4+++ u-boot/cpu/arm920t/start.S
5@@ -35,6 +35,8 @@
6 #include <s3c2410.h>
7 #elif defined(CONFIG_S3C2440)
8 #include <s3c2440.h>
9+#elif defined(CONFIG_S3C2443)
10+#include <s3c2443.h>
11 #endif
12
13
14@@ -164,9 +166,15 @@
15 # define UPLLCON_val ((0x3c << 12) + (0x4 << 4) + 0x2)
16 # define CLKDIVN_val 7 /* FCLK:HCLK:PCLK = 1:3:6 */
17 # define CAMDIVN 0x4C000018
18+#elif defined(CONFIG_S3C2443)
19+# define INTSUBMSK_val 0x1fffffff
20+# define EPLLCON_val ((40 << 16) | (1 << 8) | (1)) /* 96 MHz */
21+# define MPLLCON_val ((81 << 16) | (2 << 8) | (0)) /* 1068 MHz */
22+# define CLKDIV0_val ((8 << 9) | (1 << 4) | (1 << 3) | (1 << 2)
23 #endif
24
25-#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
26+#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || \
27+ defined(CONFIG_S3C2440) || defined(CONFIG_S3C2443)
28 ldr r0, =pWTCON
29 mov r1, #0x0
30 str r1, [r0]
31@@ -177,7 +185,7 @@
32 mov r1, #0xffffffff
33 ldr r0, =INTMSK
34 str r1, [r0]
35-# if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
36+# if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) || defined(CONFIG_S3C2443)
37 ldr r1, =INTSUBMSK_val
38 ldr r0, =INTSUBMSK
39 str r1, [r0]
40@@ -196,6 +204,43 @@
41 mcr p15, 0, r1, c1, c0, 0
42
43
44+#if defined(CONFIG_S3C2443)
45+#define LOCKCON0 0x4c000000
46+#define LOCKCON1 0x4c000004
47+#define MPLLCON 0x4c000010
48+#define EPLLCON 0x4c000018
49+
50+ ldr r0, =CLKDIV0
51+ ldr r1, =CLKDIV0_val
52+ str r1, [r0]
53+
54+ /* set safe (way too long) locktime for both PLLs */
55+ ldr r0, =LOCKCON0
56+ mov r1, #0xffffff
57+ str r1, [r0]
58+ ldr r0, =LOCKCON1
59+ str r1, [r0]
60+
61+ /* configure MPLL */
62+ ldr r0, =MPLLCON
63+ ldr r1, =MPLLCON_val
64+ str r1, [r0]
65+
66+ /* select MPLL clock out for SYSCLK */
67+ ldr r0, =CLKSRC
68+ ldr r1, [r0]
69+ orr r1, r1, #0x10
70+ str r1, [r0]
71+
72+#if 0
73+ /* configure EPLL */
74+ ldr r0, =EPLLCON
75+ ldr r1, =EPLLCON_val
76+ str r1, [r0]
77+#endif
78+
79+
80+#else /* i.e. 2440, 2410 and 2440 */
81 #define LOCKTIME 0x4c000000
82 #define UPLLCON 0x4c000008
83
84@@ -223,6 +268,7 @@
85 ldr r0, =CLKDIVN
86 mov r1, #CLKDIVN_val
87 str r1, [r0]
88+#endif
89
90 #if 1
91 /* enable uart */
92@@ -249,7 +295,7 @@
93 str r1, [r0, #0x28]
94 #endif
95
96-#endif /* CONFIG_S3C2400 || CONFIG_S3C2410 || CONFIG_S3C2440 */
97+#endif /* CONFIG_S3C2400 || CONFIG_S3C2410 || CONFIG_S3C2440 || CONFIG_S3C2443 */
98
99 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
100 #ifndef CONFIG_LL_INIT_NAND_ONLY
101Index: u-boot/cpu/arm920t/s3c24x0/interrupts.c
102===================================================================
103--- u-boot.orig/cpu/arm920t/s3c24x0/interrupts.c
104+++ u-boot/cpu/arm920t/s3c24x0/interrupts.c
105@@ -31,7 +31,8 @@
106
107 #include <common.h>
108 #if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || \
109- defined(CONFIG_S3C2440) || defined (CONFIG_TRAB)
110+ defined(CONFIG_S3C2440) || defined(CONFIG_S3C2443) || \
111+ defined (CONFIG_TRAB)
112
113 #include <arm920t.h>
114 #if defined(CONFIG_S3C2400)
115@@ -40,6 +41,8 @@
116 #include <s3c2410.h>
117 #elif defined(CONFIG_S3C2440)
118 #include <s3c2440.h>
119+#elif defined(CONFIG_S3C2443)
120+#include <s3c2443.h>
121 #endif
122
123 int timer_load_val = 0;
124@@ -186,6 +189,7 @@
125 #elif defined(CONFIG_SBC2410X) || \
126 defined(CONFIG_SMDK2410) || \
127 defined(CONFIG_SMDK2440) || \
128+ defined(CONFIG_SMDK2443) || \
129 defined(CONFIG_VCMA9)
130 tbclk = CFG_HZ;
131 #else
132Index: u-boot/drivers/usbdcore_s3c2410.c
133===================================================================
134--- u-boot.orig/drivers/usbdcore_s3c2410.c
135+++ u-boot/drivers/usbdcore_s3c2410.c
136@@ -24,7 +24,8 @@
137
138 #include <config.h>
139
140-#if (defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)) && defined(CONFIG_USB_DEVICE)
141+#if (defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) || \
142+ defined(CONFIG_S3C2443)) && defined(CONFIG_USB_DEVICE)
143
144 #include <common.h>
145
146Index: u-boot/include/s3c2443.h
147===================================================================
148--- /dev/null
149+++ u-boot/include/s3c2443.h
150@@ -0,0 +1,106 @@
151+/*
152+ * (C) Copyright 2007 OpenMoko, Inc.
153+ * Author: Harald Welte <laforge@openmoko.org>
154+ *
155+ * See file CREDITS for list of people who contributed to this
156+ * project.
157+ *
158+ * This program is free software; you can redistribute it and/or
159+ * modify it under the terms of the GNU General Public License as
160+ * published by the Free Software Foundation; either version 2 of
161+ * the License, or (at your option) any later version.
162+ *
163+ * This program is distributed in the hope that it will be useful,
164+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
165+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
166+ * GNU General Public License for more details.
167+ *
168+ * You should have received a copy of the GNU General Public License
169+ * along with this program; if not, write to the Free Software
170+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
171+ * MA 02111-1307 USA
172+ */
173+
174+#ifndef __S3C2443_H
175+#define __S3C2443_H
176+
177+#include <s3c24x0.h>
178+
179+/* CLOCK & POWER MANAGEMENT (see S3C2443 manual chapter 2) */
180+typedef struct {
181+ S3C24X0_REG32 LOCKCON0;
182+ S3C24X0_REG32 LOCKCON1;
183+ S3C24X0_REG32 OSCSET;
184+ S3C24X0_REG32 res1;
185+ S3C24X0_REG32 MPLLCON;
186+ S3C24X0_REG32 res2;
187+ S3C24X0_REG32 EPLLCON;
188+ S3C24X0_REG32 res3;
189+ S3C24X0_REG32 CLKSRC;
190+ S3C24X0_REG32 CLKDIV0;
191+ S3C24X0_REG32 CLKDIV1;
192+ S3C24X0_REG32 res4;
193+ S3C24X0_REG32 HCLKCON;
194+ S3C24X0_REG32 PCLKCON;
195+ S3C24X0_REG32 SCLKCON;
196+ S3C24X0_REG32 res5;
197+ S3C24X0_REG32 PWRMODE;
198+ S3C24X0_REG32 SWRST;
199+ S3C24X0_REG32 res6[2];
200+ S3C24X0_REG32 BUSPRI0;
201+ S3C24X0_REG32 res7[3];
202+} /*__attribute__((__packed__))*/ S3C2443_CLOCK_POWER;
203+
204+/* NAND FLASH (see S3C2443 manual chapter 7) */
205+typedef struct {
206+ S3C24X0_REG32 NFCONF;
207+ S3C24X0_REG32 NFCONT;
208+ S3C24X0_REG32 NFCMD;
209+ S3C24X0_REG32 NFADDR;
210+ S3C24X0_REG32 NFDATA;
211+ S3C24X0_REG32 NFMECCD0;
212+ S3C24X0_REG32 NFMECCD1;
213+ S3C24X0_REG32 NFSECCD;
214+ S3C24X0_REG32 NFSBLK;
215+ S3C24X0_REG32 NFEBLK;
216+ S3C24X0_REG32 NFSTAT;
217+ S3C24X0_REG32 NFECCERR0;
218+ S3C24X0_REG32 NFECCERR1;
219+ S3C24X0_REG32 NFMECC0;
220+ S3C24X0_REG32 NFMECC1;
221+ S3C24X0_REG32 NFSECC;
222+ S3C24X0_REG32 NFMLCBITPT;
223+} /*__attribute__((__packed__))*/ S3C2443_NAND;
224+
225+/* STATIC MEMORY (see S3C2443 manual chapter 5) */
226+struct s3c2443_sm_bank {
227+ S3C24X0_REG32 SMBIDCYR;
228+ S3C24X0_REG32 SMBWSTRDR;
229+ S3C24X0_REG32 SMBWSTWRR;
230+ S3C24X0_REG32 SMBWSTOENR;
231+ S3C24X0_REG32 SMBWSTWENR;
232+ S3C24X0_REG32 SMBCR;
233+ S3C24X0_REG32 SMBSR;
234+ S3C24X0_REG32 SMBWSTBRDR;
235+};
236+
237+typedef struct {
238+ struct s3c2443_sm_bank bank[5]; /* 0x4f000000..0x4f0000bf */
239+ S3C24X0_REG32 res[0x40]; /* 0x4f0000c0..0x4f0000ff */
240+ S3C24X0_REG32 SMBONETYPER;
241+ S3C24X0_REG32 SMCSR;
242+ S3C24X0_REG32 SMCCR;
243+} /*__attribute__((__packed__))*/ S3C2443_SMEM;
244+
245+
246+/* MOBILE DRAM (see S3C2443 manual chapter 6) */
247+typedef struct {
248+ S3C24X0_REG32 BANKCFG;
249+ S3C24X0_REG32 BANKCON1;
250+ S3C24X0_REG32 BANKCON2;
251+ S3C24X0_REG32 BANKCON3;
252+ S3C24X0_REG32 REFRESH;
253+ S3C24X0_REG32 TIMEOUT;
254+} /*__attribute__((__packed__))*/ S3C2443_MDRAM
255+
256+#endif /* __S3C2443_H */
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2026-07-29 00:10:02 +0000