1 files changed, 113 insertions, 0 deletions
diff --git a/meta/packages/uboot/u-boot-mkimage-openmoko-native/uboot-neo1973-resume.patch b/meta/packages/uboot/u-boot-mkimage-openmoko-native/uboot-neo1973-resume.patch
new file mode 100644
index 0000000000..19d912620d
--- /dev/null
+++ b/meta/packages/uboot/u-boot-mkimage-openmoko-native/uboot-neo1973-resume.patch
@@ -0,0 +1,113 @@
+Resume support for low-level uboot code, Version 5
+Signed-off-by: Ben Dooks <ben-linux@fluff.org>
+Index: u-boot/cpu/arm920t/start.S
+===================================================================
+--- u-boot.orig/cpu/arm920t/start.S     2007-02-28 03:51:24.000000000 +0100
+++ u-boot/cpu/arm920t/start.S  2007-03-01 02:43:47.000000000 +0100
+@@ -158,18 +158,68 @@
+        str     r1, [r0]
+ # endif
+ 
+       /* default FCLK is 202 MHz ! */
+#define LOCKTIME       0x4c000000
+#define UPLLCON                0x4c000008
+//#define MPLLCFG              ((0x90 << 12) + (0x2 << 4) + 0x2)
+#define MPLLCFG                ((0x90 << 12) + (0x7 << 4) + 0x0)
+#define UPLLCFG                ((0x78 << 12) + (0x2 << 4) + 0x3)
+       ldr     r0, =LOCKTIME
+       mov     r1, #0xffffff
+       str     r1, [r0]
+
+       ldr     r0, =UPLLCON
+       ldr     r1, =UPLLCFG
+       str     r1, [r0]
+
+       /* Page 7-19, seven nops between UPLL and MPLL */
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop
+
+       ldr     r1, =MPLLCFG
+       str     r1, [r0, #-4]           /* MPLLCON */
+
+        /* FCLK:HCLK:PCLK = 1:2:4 */
+-       /* default FCLK is 120 MHz ! */
+        ldr     r0, =CLKDIVN
+        mov     r1, #3
+        str     r1, [r0]
+
+#if 1
+       /* enable uart */
+       ldr     r0, =0x4c00000c         /* clkcon */
+       ldr     r1, =0x7fff0            /* all clocks on */
+       str     r1, [r0]
+
+       /* gpio UART0 init */
+       ldr     r0, =0x56000070
+       mov     r1, #0xaa
+       str     r1, [r0]
+
+       /* init uart */
+       ldr     r0, =0x50000000
+       mov     r1, #0x03
+       str     r1, [r0]
+       ldr     r1, =0x245
+       str     r1, [r0, #0x04]
+       mov     r1, #0x01
+       str     r1, [r0, #0x08]
+       mov     r1, #0x00
+       str     r1, [r0, #0x0c]
+       mov     r1, #0x1a
+       str     r1, [r0, #0x28]
+#endif
+
+ #endif /* CONFIG_S3C2400 || CONFIG_S3C2410 */
+ 
+ #ifndef CONFIG_SKIP_LOWLEVEL_INIT
+ #ifndef CONFIG_LL_INIT_NAND_ONLY
+        bl      cpu_init_crit
+ #endif
+-#endif
+ 
+ #ifndef CONFIG_SKIP_RELOCATE_UBOOT
+        adr     r0, _start              /* r0 <- current position of code   */
+@@ -202,9 +252,33 @@
+ 
+ #ifdef CONFIG_S3C2410_NAND_BOOT
+ nand_load:
+       /* take sdram out of power down */
+       ldr     r0, =0x56000080         /* misccr */
+       ldr     r1, [ r0 ]
+       bic     r1, r1, #(S3C2410_MISCCR_nEN_SCLK0 | S3C2410_MISCCR_nEN_SCLK1 | S3C2410_MISCCR_nEN_SCLKE)
+       str     r1, [ r0 ]
+
+       /* ensure signals stabalise */
+       mov     r1, #128
+1:     subs    r1, r1, #1
+       bpl     1b
+
+ #if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && defined(CONFIG_LL_INIT_NAND_ONLY)
+        bl      cpu_init_crit
+ #endif
+#if defined(CONFIG_S3C2410)
+       /* ensure some refresh has happened */
+       ldr     r1, =0xfffff
+1:     subs    r1, r1, #1
+       bpl     1b
+
+       /* test for resume */
+       ldr     r1, =0x560000B4         /* gstatus2 */
+       ldr     r0, [ r1 ]
+       tst     r0, #0x02               /* is this resume from power down */
+       ldrne   pc, [r1, #4]            /* gstatus3 */
+#endif /* CONFIG_S3C2410 */
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
+ 
+        /* mov  r10, lr */
+

diff --git a/meta/packages/uboot/u-boot-mkimage-openmoko-native/uboot-neo1973-resume.patch b/meta/packages/uboot/u-boot-mkimage-openmoko-native/uboot-neo1973-resume.patch new file mode 100644 index 0000000000..19d912620d --- /dev/null +++ b/meta/packages/uboot/u-boot-mkimage-openmoko-native/uboot-neo1973-resume.patch
@@ -0,0 +1,113 @@
	1	Resume support for low-level uboot code, Version 5
	2
	3	Signed-off-by: Ben Dooks <ben-linux@fluff.org>
	4
	5	Index: u-boot/cpu/arm920t/start.S
	6	===================================================================
	7	--- u-boot.orig/cpu/arm920t/start.S 2007-02-28 03:51:24.000000000 +0100
	8	+++ u-boot/cpu/arm920t/start.S 2007-03-01 02:43:47.000000000 +0100
	9	@@ -158,18 +158,68 @@
	10	str r1, [r0]
	11	# endif
	12
	13	+ /* default FCLK is 202 MHz ! */
	14	+#define LOCKTIME 0x4c000000
	15	+#define UPLLCON 0x4c000008
	16	+//#define MPLLCFG ((0x90 << 12) + (0x2 << 4) + 0x2)
	17	+#define MPLLCFG ((0x90 << 12) + (0x7 << 4) + 0x0)
	18	+#define UPLLCFG ((0x78 << 12) + (0x2 << 4) + 0x3)
	19	+ ldr r0, =LOCKTIME
	20	+ mov r1, #0xffffff
	21	+ str r1, [r0]
	22	+
	23	+ ldr r0, =UPLLCON
	24	+ ldr r1, =UPLLCFG
	25	+ str r1, [r0]
	26	+
	27	+ /* Page 7-19, seven nops between UPLL and MPLL */
	28	+ nop
	29	+ nop
	30	+ nop
	31	+ nop
	32	+ nop
	33	+ nop
	34	+ nop
	35	+
	36	+ ldr r1, =MPLLCFG
	37	+ str r1, [r0, #-4] /* MPLLCON */
	38	+
	39	/* FCLK:HCLK:PCLK = 1:2:4 */
	40	- /* default FCLK is 120 MHz ! */
	41	ldr r0, =CLKDIVN
	42	mov r1, #3
	43	str r1, [r0]
	44	+
	45	+#if 1
	46	+ /* enable uart */
	47	+ ldr r0, =0x4c00000c /* clkcon */
	48	+ ldr r1, =0x7fff0 /* all clocks on */
	49	+ str r1, [r0]
	50	+
	51	+ /* gpio UART0 init */
	52	+ ldr r0, =0x56000070
	53	+ mov r1, #0xaa
	54	+ str r1, [r0]
	55	+
	56	+ /* init uart */
	57	+ ldr r0, =0x50000000
	58	+ mov r1, #0x03
	59	+ str r1, [r0]
	60	+ ldr r1, =0x245
	61	+ str r1, [r0, #0x04]
	62	+ mov r1, #0x01
	63	+ str r1, [r0, #0x08]
	64	+ mov r1, #0x00
	65	+ str r1, [r0, #0x0c]
	66	+ mov r1, #0x1a
	67	+ str r1, [r0, #0x28]
	68	+#endif
	69	+
	70	#endif /* CONFIG_S3C2400 \|\| CONFIG_S3C2410 */
	71
	72	#ifndef CONFIG_SKIP_LOWLEVEL_INIT
	73	#ifndef CONFIG_LL_INIT_NAND_ONLY
	74	bl cpu_init_crit
	75	#endif
	76	-#endif
	77
	78	#ifndef CONFIG_SKIP_RELOCATE_UBOOT
	79	adr r0, _start /* r0 <- current position of code */
	80	@@ -202,9 +252,33 @@
	81
	82	#ifdef CONFIG_S3C2410_NAND_BOOT
	83	nand_load:
	84	+ /* take sdram out of power down */
	85	+ ldr r0, =0x56000080 /* misccr */
	86	+ ldr r1, [ r0 ]
	87	+ bic r1, r1, #(S3C2410_MISCCR_nEN_SCLK0 \| S3C2410_MISCCR_nEN_SCLK1 \| S3C2410_MISCCR_nEN_SCLKE)
	88	+ str r1, [ r0 ]
	89	+
	90	+ /* ensure signals stabalise */
	91	+ mov r1, #128
	92	+1: subs r1, r1, #1
	93	+ bpl 1b
	94	+
	95	#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && defined(CONFIG_LL_INIT_NAND_ONLY)
	96	bl cpu_init_crit
	97	#endif
	98	+#if defined(CONFIG_S3C2410)
	99	+ /* ensure some refresh has happened */
	100	+ ldr r1, =0xfffff
	101	+1: subs r1, r1, #1
	102	+ bpl 1b
	103	+
	104	+ /* test for resume */
	105	+ ldr r1, =0x560000B4 /* gstatus2 */
	106	+ ldr r0, [ r1 ]
	107	+ tst r0, #0x02 /* is this resume from power down */
	108	+ ldrne pc, [r1, #4] /* gstatus3 */
	109	+#endif /* CONFIG_S3C2410 */
	110	+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
	111
	112	/* mov r10, lr */
	113