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-rw-r--r--meta/recipes-devtools/qemu/qemu/ppc.patch127
1 files changed, 102 insertions, 25 deletions
diff --git a/meta/recipes-devtools/qemu/qemu/ppc.patch b/meta/recipes-devtools/qemu/qemu/ppc.patch
index ade1daf61f..1fe6a3b413 100644
--- a/meta/recipes-devtools/qemu/qemu/ppc.patch
+++ b/meta/recipes-devtools/qemu/qemu/ppc.patch
@@ -1,70 +1,147 @@
1target/ppc: Fix fallback to MFSS for MFFSCRN, MFFSCRNI, MFFSCE and MFFSL 1From d92b63b7d15d4fd202c5802dfe444a96f5d8109c Mon Sep 17 00:00:00 2001
2From: Richard Purdie <richard.purdie@linuxfoundation.org>
3Date: Sat, 6 May 2023 07:42:35 +0100
4Cc: Víctor Colombo <victor.colombo@eldorado.org.br>
5Cc: Matheus Ferst <matheus.ferst@eldorado.org.br>
6Cc: Daniel Henrique Barboza <danielhb413@gmail.com>
7Cc: Richard Henderson <richard.henderson@linaro.org>
8Subject: [PATCH v2] target/ppc: Fix fallback to MFSS for MFFS* instructions on
9 pre 3.0 ISAs
2 10
3The following commits changed the code such that these instructions became invalid 11The following commits changed the code such that the fallback to MFSS for MFFSCRN,
4on pre 3.0 ISAs: 12MFFSCRNI, MFFSCE and MFFSL on pre 3.0 ISAs was removed and became an illegal instruction:
5 13
6 bf8adfd88b547680aa857c46098f3a1e94373160 - target/ppc: Move mffscrn[i] to decodetree 14 bf8adfd88b547680aa857c46098f3a1e94373160 - target/ppc: Move mffscrn[i] to decodetree
7 394c2e2fda70da722f20fb60412d6c0ca4bfaa03 - target/ppc: Move mffsce to decodetree 15 394c2e2fda70da722f20fb60412d6c0ca4bfaa03 - target/ppc: Move mffsce to decodetree
8 3e5bce70efe6bd1f684efbb21fd2a316cbf0657e - target/ppc: Move mffsl to decodetree 16 3e5bce70efe6bd1f684efbb21fd2a316cbf0657e - target/ppc: Move mffsl to decodetree
9 17
10The hardware will handle them as a MFFS instruction as the code did previously. 18The hardware will handle them as a MFFS instruction as the code did previously.
11Restore that behaviour. This means applications that were segfaulting under qemu 19This means applications that were segfaulting under qemu when encountering these
12when encountering these instructions now operate correctly. The instruction 20instructions which is used in glibc libm functions for example.
13is used in glibc libm functions for example.
14 21
15Upstream-Status: Submitted [https://lore.kernel.org/qemu-devel/20230504110150.3044402-1-richard.purdie@linuxfoundation.org/] 22The fallback for MFFSCDRN and MFFSCDRNI added in a later patch was also missing.
23
24This patch restores the fallback to MFSS for these instructions on pre 3.0s ISAs
25as the hardware decoder would, fixing the segfaulting libm code. It and also ensures
26the MFSS instruction is used for currently reserved bits to handle other potential
27ISA additions more correctly.
28
29Upstream-Status: Submitted [https://lore.kernel.org/qemu-devel/20230506065240.3177798-1-richard.purdie@linuxfoundation.org/]
16 30
17Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org> 31Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
32---
33 target/ppc/insn32.decode | 19 ++++++++++++-------
34 target/ppc/translate/fp-impl.c.inc | 30 ++++++++++++++++++++++++------
35 2 files changed, 36 insertions(+), 13 deletions(-)
18 36
19Index: qemu-8.0.0/target/ppc/translate/fp-impl.c.inc 37v2 - switch to use decodetree pattern groups per feedback
20=================================================================== 38
21--- qemu-8.0.0.orig/target/ppc/translate/fp-impl.c.inc 39diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
22+++ qemu-8.0.0/target/ppc/translate/fp-impl.c.inc 40index f8f589e9fd..3c4e2c2fc2 100644
23@@ -584,7 +584,10 @@ static bool trans_MFFSCE(DisasContext *c 41--- a/target/ppc/insn32.decode
42+++ b/target/ppc/insn32.decode
43@@ -390,13 +390,18 @@ SETNBCR 011111 ..... ..... ----- 0111100000 - @X_bi
44
45 ### Move To/From FPSCR
46
47-MFFS 111111 ..... 00000 ----- 1001000111 . @X_t_rc
48-MFFSCE 111111 ..... 00001 ----- 1001000111 - @X_t
49-MFFSCRN 111111 ..... 10110 ..... 1001000111 - @X_tb
50-MFFSCDRN 111111 ..... 10100 ..... 1001000111 - @X_tb
51-MFFSCRNI 111111 ..... 10111 ---.. 1001000111 - @X_imm2
52-MFFSCDRNI 111111 ..... 10101 --... 1001000111 - @X_imm3
53-MFFSL 111111 ..... 11000 ----- 1001000111 - @X_t
54+{
55+ # Before Power ISA v3.0, MFFS bits 11~15 were reserved and should be ignored
56+ [
57+ MFFSCE 111111 ..... 00001 ----- 1001000111 - @X_t
58+ MFFSCRN 111111 ..... 10110 ..... 1001000111 - @X_tb
59+ MFFSCDRN 111111 ..... 10100 ..... 1001000111 - @X_tb
60+ MFFSCRNI 111111 ..... 10111 ---.. 1001000111 - @X_imm2
61+ MFFSCDRNI 111111 ..... 10101 --... 1001000111 - @X_imm3
62+ MFFSL 111111 ..... 11000 ----- 1001000111 - @X_t
63+ ]
64+ MFFS 111111 ..... ----- ----- 1001000111 . @X_t_rc
65+}
66
67 ### Decimal Floating-Point Arithmetic Instructions
68
69diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-impl.c.inc
70index 57d8437851..10dfd91aa4 100644
71--- a/target/ppc/translate/fp-impl.c.inc
72+++ b/target/ppc/translate/fp-impl.c.inc
73@@ -584,7 +584,10 @@ static bool trans_MFFSCE(DisasContext *ctx, arg_X_t *a)
24 { 74 {
25 TCGv_i64 fpscr; 75 TCGv_i64 fpscr;
26 76
27- REQUIRE_INSNS_FLAGS2(ctx, ISA300); 77- REQUIRE_INSNS_FLAGS2(ctx, ISA300);
28+ if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) { 78+ if (!(ctx->insns_flags2 & PPC2_ISA300)) {
29+ return trans_MFFS(ctx, a); 79+ return false;
30+ } 80+ }
31+ 81+
32 REQUIRE_FPU(ctx); 82 REQUIRE_FPU(ctx);
33 83
34 gen_reset_fpstatus(); 84 gen_reset_fpstatus();
35@@ -597,7 +600,10 @@ static bool trans_MFFSCRN(DisasContext * 85@@ -597,7 +600,10 @@ static bool trans_MFFSCRN(DisasContext *ctx, arg_X_tb *a)
86 {
87 TCGv_i64 t1, fpscr;
88
89- REQUIRE_INSNS_FLAGS2(ctx, ISA300);
90+ if (!(ctx->insns_flags2 & PPC2_ISA300)) {
91+ return false;
92+ }
93+
94 REQUIRE_FPU(ctx);
95
96 t1 = tcg_temp_new_i64();
97@@ -614,7 +620,10 @@ static bool trans_MFFSCDRN(DisasContext *ctx, arg_X_tb *a)
36 { 98 {
37 TCGv_i64 t1, fpscr; 99 TCGv_i64 t1, fpscr;
38 100
39- REQUIRE_INSNS_FLAGS2(ctx, ISA300); 101- REQUIRE_INSNS_FLAGS2(ctx, ISA300);
40+ if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) { 102+ if (!(ctx->insns_flags2 & PPC2_ISA300)) {
41+ return trans_MFFS(ctx, a); 103+ return false;
42+ } 104+ }
43+ 105+
44 REQUIRE_FPU(ctx); 106 REQUIRE_FPU(ctx);
45 107
46 t1 = tcg_temp_new_i64(); 108 t1 = tcg_temp_new_i64();
47@@ -631,7 +637,10 @@ static bool trans_MFFSCRNI(DisasContext 109@@ -631,7 +640,10 @@ static bool trans_MFFSCRNI(DisasContext *ctx, arg_X_imm2 *a)
48 { 110 {
49 TCGv_i64 t1, fpscr; 111 TCGv_i64 t1, fpscr;
50 112
51- REQUIRE_INSNS_FLAGS2(ctx, ISA300); 113- REQUIRE_INSNS_FLAGS2(ctx, ISA300);
52+ if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) { 114+ if (!(ctx->insns_flags2 & PPC2_ISA300)) {
53+ return trans_MFFS(ctx, a); 115+ return false;
54+ } 116+ }
55+ 117+
56 REQUIRE_FPU(ctx); 118 REQUIRE_FPU(ctx);
57 119
58 t1 = tcg_temp_new_i64(); 120 t1 = tcg_temp_new_i64();
59@@ -661,7 +670,10 @@ static bool trans_MFFSCDRNI(DisasContext 121@@ -647,7 +659,10 @@ static bool trans_MFFSCDRNI(DisasContext *ctx, arg_X_imm3 *a)
122 {
123 TCGv_i64 t1, fpscr;
124
125- REQUIRE_INSNS_FLAGS2(ctx, ISA300);
126+ if (!(ctx->insns_flags2 & PPC2_ISA300)) {
127+ return false;
128+ }
129+
130 REQUIRE_FPU(ctx);
131
132 t1 = tcg_temp_new_i64();
133@@ -661,7 +676,10 @@ static bool trans_MFFSCDRNI(DisasContext *ctx, arg_X_imm3 *a)
60 134
61 static bool trans_MFFSL(DisasContext *ctx, arg_X_t *a) 135 static bool trans_MFFSL(DisasContext *ctx, arg_X_t *a)
62 { 136 {
63- REQUIRE_INSNS_FLAGS2(ctx, ISA300); 137- REQUIRE_INSNS_FLAGS2(ctx, ISA300);
64+ if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) { 138+ if (!(ctx->insns_flags2 & PPC2_ISA300)) {
65+ return trans_MFFS(ctx, a); 139+ return false;
66+ } 140+ }
67+ 141+
68 REQUIRE_FPU(ctx); 142 REQUIRE_FPU(ctx);
69 143
70 gen_reset_fpstatus(); 144 gen_reset_fpstatus();
145--
1462.39.2
147
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2026-02-13 07:17:41 +0000