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-rw-r--r--meta/recipes-devtools/gcc/gcc-11.1.inc3
-rw-r--r--meta/recipes-devtools/gcc/gcc/0038-arc-Update-64bit-move-split-patterns.patch290
-rw-r--r--meta/recipes-devtools/gcc/gcc/0039-arc-Fix-u-maddhisi-patterns.patch127
-rw-r--r--meta/recipes-devtools/gcc/gcc/0040-arc-Update-doloop_end-patterns.patch105
4 files changed, 525 insertions, 0 deletions
diff --git a/meta/recipes-devtools/gcc/gcc-11.1.inc b/meta/recipes-devtools/gcc/gcc-11.1.inc
index bf29879ded..69e4c8bacc 100644
--- a/meta/recipes-devtools/gcc/gcc-11.1.inc
+++ b/meta/recipes-devtools/gcc/gcc-11.1.inc
@@ -69,6 +69,9 @@ SRC_URI = "\
69 file://0036-mingw32-Enable-operation_not_supported.patch \ 69 file://0036-mingw32-Enable-operation_not_supported.patch \
70 file://0037-libatomic-Do-not-enforce-march-on-aarch64.patch \ 70 file://0037-libatomic-Do-not-enforce-march-on-aarch64.patch \
71 file://0001-Revert-libstdc-Install-libstdc-gdb.py-more-robustly-.patch \ 71 file://0001-Revert-libstdc-Install-libstdc-gdb.py-more-robustly-.patch \
72 file://0038-arc-Update-64bit-move-split-patterns.patch \
73 file://0039-arc-Fix-u-maddhisi-patterns.patch \
74 file://0040-arc-Update-doloop_end-patterns.patch \
72" 75"
73SRC_URI[sha256sum] = "4c4a6fb8a8396059241c2e674b85b351c26a5d678274007f076957afa1cc9ddf" 76SRC_URI[sha256sum] = "4c4a6fb8a8396059241c2e674b85b351c26a5d678274007f076957afa1cc9ddf"
74SRC_URI[backports.sha256sum] = "69274bebd6c069a13443d4af61070e854740a639ec4d66eedf3e80070363587b" 77SRC_URI[backports.sha256sum] = "69274bebd6c069a13443d4af61070e854740a639ec4d66eedf3e80070363587b"
diff --git a/meta/recipes-devtools/gcc/gcc/0038-arc-Update-64bit-move-split-patterns.patch b/meta/recipes-devtools/gcc/gcc/0038-arc-Update-64bit-move-split-patterns.patch
new file mode 100644
index 0000000000..37fe95d711
--- /dev/null
+++ b/meta/recipes-devtools/gcc/gcc/0038-arc-Update-64bit-move-split-patterns.patch
@@ -0,0 +1,290 @@
1From 0061fabeb9393c362601486105202cfe837a5a68 Mon Sep 17 00:00:00 2001
2From: Claudiu Zissulescu <claziss@synopsys.com>
3Date: Wed, 9 Jun 2021 12:12:57 +0300
4Subject: [PATCH] arc: Update 64bit move split patterns.
5
6ARCv2HS can use a limited number of instructions to implement 64bit
7moves. The VADD2 is used as a 64bit move, the LDD/STD are 64 bit loads
8and stores. All those instructions are not baseline, hence we need to
9provide alternatives when they are not available or cannot be generate
10due to instruction restriction.
11
12This patch is cleaning up those move patterns, and updates splits
13instruction lengths.
14
15This is a backport from mainline gcc.
16
17gcc/
182021-06-09 Claudiu Zissulescu <claziss@synopsys.com>
19
20 * config/arc/arc-protos.h (arc_split_move_p): New prototype.
21 * config/arc/arc.c (arc_split_move_p): New function.
22 (arc_split_move): Clean up.
23 * config/arc/arc.md (movdi_insn): Clean up, use arc_split_move_p.
24 (movdf_insn): Likewise.
25 * config/arc/simdext.md (mov<VWH>_insn): Likewise.
26
27Upstream-Status: Backport [https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=0061fabeb9393c362601486105202cfe837a5a68]
28
29Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
30(cherry picked from commit c0ba7a8af5366c37241f20e8be41e362f7260389)
31Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
32---
33 gcc/config/arc/arc-protos.h | 1 +
34 gcc/config/arc/arc.c | 44 ++++++++++++----------
35 gcc/config/arc/arc.md | 91 +++++++++------------------------------------
36 gcc/config/arc/simdext.md | 38 ++++---------------
37 4 files changed, 52 insertions(+), 122 deletions(-)
38
39diff --git a/gcc/config/arc/arc-protos.h b/gcc/config/arc/arc-protos.h
40index 1f56a0d82e4..62d7e45d29d 100644
41--- a/gcc/config/arc/arc-protos.h
42+++ b/gcc/config/arc/arc-protos.h
43@@ -50,6 +50,7 @@ extern void arc_split_ior (rtx *);
44 extern bool arc_check_mov_const (HOST_WIDE_INT );
45 extern bool arc_split_mov_const (rtx *);
46 extern bool arc_can_use_return_insn (void);
47+extern bool arc_split_move_p (rtx *);
48 #endif /* RTX_CODE */
49
50 extern bool arc_ccfsm_branch_deleted_p (void);
51diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
52index 3201c3fefd7..db541bc11f5 100644
53--- a/gcc/config/arc/arc.c
54+++ b/gcc/config/arc/arc.c
55@@ -10129,6 +10129,31 @@ arc_process_double_reg_moves (rtx *operands)
56 return true;
57 }
58
59+
60+/* Check if we need to split a 64bit move. We do not need to split it if we can
61+ use vadd2 or ldd/std instructions. */
62+
63+bool
64+arc_split_move_p (rtx *operands)
65+{
66+ machine_mode mode = GET_MODE (operands[0]);
67+
68+ if (TARGET_LL64
69+ && ((memory_operand (operands[0], mode)
70+ && (even_register_operand (operands[1], mode)
71+ || satisfies_constraint_Cm3 (operands[1])))
72+ || (memory_operand (operands[1], mode)
73+ && even_register_operand (operands[0], mode))))
74+ return false;
75+
76+ if (TARGET_PLUS_QMACW
77+ && even_register_operand (operands[0], mode)
78+ && even_register_operand (operands[1], mode))
79+ return false;
80+
81+ return true;
82+}
83+
84 /* operands 0..1 are the operands of a 64 bit move instruction.
85 split it into two moves with operands 2/3 and 4/5. */
86
87@@ -10146,25 +10171,6 @@ arc_split_move (rtx *operands)
88 return;
89 }
90
91- if (TARGET_LL64
92- && ((memory_operand (operands[0], mode)
93- && (even_register_operand (operands[1], mode)
94- || satisfies_constraint_Cm3 (operands[1])))
95- || (memory_operand (operands[1], mode)
96- && even_register_operand (operands[0], mode))))
97- {
98- emit_move_insn (operands[0], operands[1]);
99- return;
100- }
101-
102- if (TARGET_PLUS_QMACW
103- && even_register_operand (operands[0], mode)
104- && even_register_operand (operands[1], mode))
105- {
106- emit_move_insn (operands[0], operands[1]);
107- return;
108- }
109-
110 if (TARGET_PLUS_QMACW
111 && GET_CODE (operands[1]) == CONST_VECTOR)
112 {
113diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
114index 7a52551eef5..91a838a38e4 100644
115--- a/gcc/config/arc/arc.md
116+++ b/gcc/config/arc/arc.md
117@@ -1329,47 +1329,20 @@ core_3, archs4x, archs4xd, archs4xd_slow"
118 "register_operand (operands[0], DImode)
119 || register_operand (operands[1], DImode)
120 || (satisfies_constraint_Cm3 (operands[1])
121- && memory_operand (operands[0], DImode))"
122- "*
123-{
124- switch (which_alternative)
125- {
126- default:
127- return \"#\";
128-
129- case 0:
130- if (TARGET_PLUS_QMACW
131- && even_register_operand (operands[0], DImode)
132- && even_register_operand (operands[1], DImode))
133- return \"vadd2%?\\t%0,%1,0\";
134- return \"#\";
135-
136- case 2:
137- if (TARGET_LL64
138- && memory_operand (operands[1], DImode)
139- && even_register_operand (operands[0], DImode))
140- return \"ldd%U1%V1 %0,%1%&\";
141- return \"#\";
142-
143- case 3:
144- if (TARGET_LL64
145- && memory_operand (operands[0], DImode)
146- && (even_register_operand (operands[1], DImode)
147- || satisfies_constraint_Cm3 (operands[1])))
148- return \"std%U0%V0 %1,%0\";
149- return \"#\";
150- }
151-}"
152- "&& reload_completed"
153+ && memory_operand (operands[0], DImode))"
154+ "@
155+ vadd2\\t%0,%1,0
156+ #
157+ ldd%U1%V1\\t%0,%1
158+ std%U0%V0\\t%1,%0"
159+ "&& reload_completed && arc_split_move_p (operands)"
160 [(const_int 0)]
161 {
162 arc_split_move (operands);
163 DONE;
164 }
165 [(set_attr "type" "move,move,load,store")
166- ;; ??? The ld/st values could be 4 if it's [reg,bignum].
167- (set_attr "length" "8,16,*,*")])
168-
169+ (set_attr "length" "8,16,16,16")])
170
171 ;; Floating point move insns.
172
173@@ -1408,50 +1381,22 @@ core_3, archs4x, archs4xd, archs4xd_slow"
174 (define_insn_and_split "*movdf_insn"
175 [(set (match_operand:DF 0 "move_dest_operand" "=D,r,r,r,r,m")
176 (match_operand:DF 1 "move_double_src_operand" "r,D,r,E,m,r"))]
177- "register_operand (operands[0], DFmode)
178- || register_operand (operands[1], DFmode)"
179- "*
180-{
181- switch (which_alternative)
182- {
183- default:
184- return \"#\";
185-
186- case 2:
187- if (TARGET_PLUS_QMACW
188- && even_register_operand (operands[0], DFmode)
189- && even_register_operand (operands[1], DFmode))
190- return \"vadd2%?\\t%0,%1,0\";
191- return \"#\";
192-
193- case 4:
194- if (TARGET_LL64
195- && ((even_register_operand (operands[0], DFmode)
196- && memory_operand (operands[1], DFmode))
197- || (memory_operand (operands[0], DFmode)
198- && even_register_operand (operands[1], DFmode))))
199- return \"ldd%U1%V1 %0,%1%&\";
200- return \"#\";
201-
202- case 5:
203- if (TARGET_LL64
204- && ((even_register_operand (operands[0], DFmode)
205- && memory_operand (operands[1], DFmode))
206- || (memory_operand (operands[0], DFmode)
207- && even_register_operand (operands[1], DFmode))))
208- return \"std%U0%V0 %1,%0\";
209- return \"#\";
210- }
211-}"
212- "reload_completed"
213+ "(register_operand (operands[0], DFmode)
214+ || register_operand (operands[1], DFmode))"
215+ "@
216+ #
217+ #
218+ vadd2\\t%0,%1,0
219+ #
220+ ldd%U1%V1\\t%0,%1
221+ std%U0%V0\\t%1,%0"
222+ "&& reload_completed && arc_split_move_p (operands)"
223 [(const_int 0)]
224 {
225 arc_split_move (operands);
226 DONE;
227 }
228 [(set_attr "type" "move,move,move,move,load,store")
229- (set_attr "predicable" "no,no,no,yes,no,no")
230- ;; ??? The ld/st values could be 16 if it's [reg,bignum].
231 (set_attr "length" "4,16,8,16,16,16")])
232
233 (define_insn_and_split "*movdf_insn_nolrsr"
234diff --git a/gcc/config/arc/simdext.md b/gcc/config/arc/simdext.md
235index f0900757452..36f41a5c3d0 100644
236--- a/gcc/config/arc/simdext.md
237+++ b/gcc/config/arc/simdext.md
238@@ -1402,41 +1402,19 @@
239 (match_operand:VWH 1 "general_operand" "i,r,m,r"))]
240 "(register_operand (operands[0], <MODE>mode)
241 || register_operand (operands[1], <MODE>mode))"
242- "*
243-{
244- switch (which_alternative)
245- {
246- default:
247- return \"#\";
248-
249- case 1:
250- if (TARGET_PLUS_QMACW
251- && even_register_operand (operands[0], <MODE>mode)
252- && even_register_operand (operands[1], <MODE>mode))
253- return \"vadd2%?\\t%0,%1,0\";
254- return \"#\";
255-
256- case 2:
257- if (TARGET_LL64)
258- return \"ldd%U1%V1 %0,%1\";
259- return \"#\";
260-
261- case 3:
262- if (TARGET_LL64)
263- return \"std%U0%V0 %1,%0\";
264- return \"#\";
265- }
266-}"
267- "reload_completed"
268+ "@
269+ #
270+ vadd2\\t%0,%1,0
271+ ldd%U1%V1\\t%0,%1
272+ std%U0%V0\\t%1,%0"
273+ "&& reload_completed && arc_split_move_p (operands)"
274 [(const_int 0)]
275 {
276 arc_split_move (operands);
277 DONE;
278 }
279- [(set_attr "type" "move,multi,load,store")
280- (set_attr "predicable" "no,no,no,no")
281- (set_attr "iscompact" "false,false,false,false")
282- ])
283+ [(set_attr "type" "move,move,load,store")
284+ (set_attr "length" "16,8,16,16")])
285
286 (define_expand "movmisalign<mode>"
287 [(set (match_operand:VWH 0 "general_operand" "")
288--
2892.16.2
290
diff --git a/meta/recipes-devtools/gcc/gcc/0039-arc-Fix-u-maddhisi-patterns.patch b/meta/recipes-devtools/gcc/gcc/0039-arc-Fix-u-maddhisi-patterns.patch
new file mode 100644
index 0000000000..9c5a2b8b33
--- /dev/null
+++ b/meta/recipes-devtools/gcc/gcc/0039-arc-Fix-u-maddhisi-patterns.patch
@@ -0,0 +1,127 @@
1From 4186b7e93be73f8d68dc0fcc00a4cc8cc83e99a8 Mon Sep 17 00:00:00 2001
2From: Claudiu Zissulescu <claziss@synopsys.com>
3Date: Wed, 9 Jun 2021 12:12:57 +0300
4Subject: [PATCH] arc: Fix (u)maddhisi patterns
5
6Rework the (u)maddhisi4 patterns and use VMAC2H(U) instruction instead
7of the 64bit MAC(U) instruction.
8This fixes the next execute.exp failures:
9 arith-rand-ll.c -O2 execution test
10 arith-rand-ll.c -O3 execution test
11 pr78726.c -O2 execution test
12 pr78726.c -O3 execution test
13
14gcc/
152021-06-09 Claudiu Zissulescu <claziss@synopsys.com>
16
17 * config/arc/arc.md (maddhisi4): Use VMAC2H instruction.
18 (machi): New pattern.
19 (umaddhisi4): Use VMAC2HU instruction.
20 (umachi): New pattern.
21
22Upstream-Status: Backport [https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=4186b7e93be73f8d68dc0fcc00a4cc8cc83e99a8]
23
24Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
25(cherry picked from commit dd4778a59b4693777c732075021375e19eee6a76)
26Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
27---
28 gcc/config/arc/arc.md | 66 ++++++++++++++++++++++++++++++++-------------------
29 1 file changed, 41 insertions(+), 25 deletions(-)
30
31diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
32index 91a838a38e4..2a7e087ff72 100644
33--- a/gcc/config/arc/arc.md
34+++ b/gcc/config/arc/arc.md
35@@ -6053,48 +6053,64 @@ core_3, archs4x, archs4xd, archs4xd_slow"
36
37 ;; MAC and DMPY instructions
38
39-; Use MAC instruction to emulate 16bit mac.
40+; Use VMAC2H(U) instruction to emulate scalar 16bit mac.
41 (define_expand "maddhisi4"
42 [(match_operand:SI 0 "register_operand" "")
43 (match_operand:HI 1 "register_operand" "")
44 (match_operand:HI 2 "extend_operand" "")
45 (match_operand:SI 3 "register_operand" "")]
46- "TARGET_PLUS_DMPY"
47+ "TARGET_PLUS_MACD"
48 "{
49- rtx acc_reg = gen_rtx_REG (DImode, ACC_REG_FIRST);
50- rtx tmp1 = gen_reg_rtx (SImode);
51- rtx tmp2 = gen_reg_rtx (SImode);
52- rtx accl = gen_lowpart (SImode, acc_reg);
53-
54- emit_move_insn (accl, operands[3]);
55- emit_insn (gen_rtx_SET (tmp1, gen_rtx_SIGN_EXTEND (SImode, operands[1])));
56- emit_insn (gen_rtx_SET (tmp2, gen_rtx_SIGN_EXTEND (SImode, operands[2])));
57- emit_insn (gen_mac (tmp1, tmp2));
58- emit_move_insn (operands[0], accl);
59+ rtx acc_reg = gen_rtx_REG (SImode, ACC_REG_FIRST);
60+
61+ emit_move_insn (acc_reg, operands[3]);
62+ emit_insn (gen_machi (operands[1], operands[2]));
63+ emit_move_insn (operands[0], acc_reg);
64 DONE;
65 }")
66
67-; The same for the unsigned variant, but using MACU instruction.
68+(define_insn "machi"
69+ [(set (reg:SI ARCV2_ACC)
70+ (plus:SI
71+ (mult:SI (sign_extend:SI (match_operand:HI 0 "register_operand" "%r"))
72+ (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))
73+ (reg:SI ARCV2_ACC)))]
74+ "TARGET_PLUS_MACD"
75+ "vmac2h\\t0,%0,%1"
76+ [(set_attr "length" "4")
77+ (set_attr "type" "multi")
78+ (set_attr "predicable" "no")
79+ (set_attr "cond" "nocond")])
80+
81+; The same for the unsigned variant, but using VMAC2HU instruction.
82 (define_expand "umaddhisi4"
83 [(match_operand:SI 0 "register_operand" "")
84 (match_operand:HI 1 "register_operand" "")
85- (match_operand:HI 2 "extend_operand" "")
86+ (match_operand:HI 2 "register_operand" "")
87 (match_operand:SI 3 "register_operand" "")]
88- "TARGET_PLUS_DMPY"
89+ "TARGET_PLUS_MACD"
90 "{
91- rtx acc_reg = gen_rtx_REG (DImode, ACC_REG_FIRST);
92- rtx tmp1 = gen_reg_rtx (SImode);
93- rtx tmp2 = gen_reg_rtx (SImode);
94- rtx accl = gen_lowpart (SImode, acc_reg);
95-
96- emit_move_insn (accl, operands[3]);
97- emit_insn (gen_rtx_SET (tmp1, gen_rtx_ZERO_EXTEND (SImode, operands[1])));
98- emit_insn (gen_rtx_SET (tmp2, gen_rtx_ZERO_EXTEND (SImode, operands[2])));
99- emit_insn (gen_macu (tmp1, tmp2));
100- emit_move_insn (operands[0], accl);
101+ rtx acc_reg = gen_rtx_REG (SImode, ACC_REG_FIRST);
102+
103+ emit_move_insn (acc_reg, operands[3]);
104+ emit_insn (gen_umachi (operands[1], operands[2]));
105+ emit_move_insn (operands[0], acc_reg);
106 DONE;
107 }")
108
109+(define_insn "umachi"
110+ [(set (reg:SI ARCV2_ACC)
111+ (plus:SI
112+ (mult:SI (zero_extend:SI (match_operand:HI 0 "register_operand" "%r"))
113+ (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))
114+ (reg:SI ARCV2_ACC)))]
115+ "TARGET_PLUS_MACD"
116+ "vmac2hu\\t0,%0,%1"
117+ [(set_attr "length" "4")
118+ (set_attr "type" "multi")
119+ (set_attr "predicable" "no")
120+ (set_attr "cond" "nocond")])
121+
122 (define_expand "maddsidi4"
123 [(match_operand:DI 0 "register_operand" "")
124 (match_operand:SI 1 "register_operand" "")
125--
1262.16.2
127
diff --git a/meta/recipes-devtools/gcc/gcc/0040-arc-Update-doloop_end-patterns.patch b/meta/recipes-devtools/gcc/gcc/0040-arc-Update-doloop_end-patterns.patch
new file mode 100644
index 0000000000..5f0bf8df8f
--- /dev/null
+++ b/meta/recipes-devtools/gcc/gcc/0040-arc-Update-doloop_end-patterns.patch
@@ -0,0 +1,105 @@
1From 5a9b6a004f89fdd95b0470e1324dc4dee8c41d24 Mon Sep 17 00:00:00 2001
2From: Claudiu Zissulescu <claziss@synopsys.com>
3Date: Wed, 9 Jun 2021 12:12:57 +0300
4Subject: [PATCH] arc: Update doloop_end patterns
5
6ARC processor can use LP instruction to implement zero overlay loops.
7The current inplementation doesn't handle the unlikely situation when
8the loop iterator is located in memory. Refurbish the loop_end insn
9pattern into a define_insn_and_split pattern.
10
11gcc/
122021-07-09 Claudiu Zissulescu <claziss@synopsys.com>
13
14 * config/arc/arc.md (loop_end): Change it to
15 define_insn_and_split.
16
17Upstream-Status: Backport [https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=5a9b6a004f89fdd95b0470e1324dc4dee8c41d24]
18
19Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
20(cherry picked from commit 174e75a210753b68de0f2c398a13ace0f512e35b)
21Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
22---
23 gcc/config/arc/arc.md | 46 ++++++++++++++++++++--------------------------
24 1 file changed, 20 insertions(+), 26 deletions(-)
25
26diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
27index 2a7e087ff72..d704044c13f 100644
28--- a/gcc/config/arc/arc.md
29+++ b/gcc/config/arc/arc.md
30@@ -4986,7 +4986,7 @@ core_3, archs4x, archs4xd, archs4xd_slow"
31 (define_expand "doloop_end"
32 [(parallel [(set (pc)
33 (if_then_else
34- (ne (match_operand 0 "" "")
35+ (ne (match_operand 0 "nonimmediate_operand")
36 (const_int 1))
37 (label_ref (match_operand 1 "" ""))
38 (pc)))
39@@ -5012,44 +5012,38 @@ core_3, archs4x, archs4xd, archs4xd_slow"
40
41 ;; if by any chance the lp_count is not used, then use an 'r'
42 ;; register, instead of going to memory.
43-(define_insn "loop_end"
44- [(set (pc)
45- (if_then_else (ne (match_operand:SI 2 "nonimmediate_operand" "0,m")
46- (const_int 1))
47- (label_ref (match_operand 1 "" ""))
48- (pc)))
49- (set (match_operand:SI 0 "nonimmediate_operand" "=r,m")
50- (plus (match_dup 2) (const_int -1)))
51- (unspec [(const_int 0)] UNSPEC_ARC_LP)
52- (clobber (match_scratch:SI 3 "=X,&r"))]
53- ""
54- "; ZOL_END, begins @%l1"
55- [(set_attr "length" "0")
56- (set_attr "predicable" "no")
57- (set_attr "type" "loop_end")])
58-
59 ;; split pattern for the very slim chance when the loop register is
60 ;; memory.
61-(define_split
62+(define_insn_and_split "loop_end"
63 [(set (pc)
64- (if_then_else (ne (match_operand:SI 0 "memory_operand")
65+ (if_then_else (ne (match_operand:SI 0 "nonimmediate_operand" "+r,!m")
66 (const_int 1))
67- (label_ref (match_operand 1 ""))
68+ (label_ref (match_operand 1 "" ""))
69 (pc)))
70 (set (match_dup 0) (plus (match_dup 0) (const_int -1)))
71 (unspec [(const_int 0)] UNSPEC_ARC_LP)
72- (clobber (match_scratch:SI 2))]
73- "memory_operand (operands[0], SImode)"
74+ (clobber (match_scratch:SI 2 "=X,&r"))]
75+ ""
76+ "@
77+ ; ZOL_END, begins @%l1
78+ #"
79+ "reload_completed && memory_operand (operands[0], Pmode)"
80 [(set (match_dup 2) (match_dup 0))
81- (set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
82+ (parallel
83+ [(set (reg:CC_ZN CC_REG)
84+ (compare:CC_ZN (plus:SI (match_dup 2) (const_int -1))
85+ (const_int 0)))
86+ (set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))])
87 (set (match_dup 0) (match_dup 2))
88- (set (reg:CC CC_REG) (compare:CC (match_dup 2) (const_int 0)))
89 (set (pc)
90- (if_then_else (ne (reg:CC CC_REG)
91+ (if_then_else (ne (reg:CC_ZN CC_REG)
92 (const_int 0))
93 (label_ref (match_dup 1))
94 (pc)))]
95- "")
96+ ""
97+ [(set_attr "length" "0,24")
98+ (set_attr "predicable" "no")
99+ (set_attr "type" "loop_end")])
100
101 (define_insn "loop_fail"
102 [(set (reg:SI LP_COUNT)
103--
1042.16.2
105
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