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authorHongxu Jia <hongxu.jia@windriver.com>2018-07-02 13:57:09 +0800
committerRichard Purdie <richard.purdie@linuxfoundation.org>2018-07-04 00:02:16 +0100
commit60857bd2d4c4f78e452f131fa763a86ed56fc22e (patch)
tree2c70fbaa0a458cfc683cd1c39ef1786e3b6bc707 /meta/recipes-devtools/elfutils/files/debian/0001-arm_backend.patch
parentb07db23759b92d592a312e3472720212bb5a724e (diff)
downloadpoky-60857bd2d4c4f78e452f131fa763a86ed56fc22e.tar.gz
elfutils: 0.170 -> 0.172
- Update debian 0.170 patches and rebase them for 0.172; - Drop 0001-Use-fallthrough-attribute.patch which was accepted by upstream; - Drop 0001-Ensure-that-packed-structs-follow-the-gcc-memory-lay.patch which was backported from upstream; (From OE-Core rev: dbbe9c1d1f822cf13a4c16b79bccf6bf5c4b91e4) Signed-off-by: Hongxu Jia <hongxu.jia@windriver.com> Signed-off-by: Ross Burton <ross.burton@intel.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
Diffstat (limited to 'meta/recipes-devtools/elfutils/files/debian/0001-arm_backend.patch')
-rw-r--r--meta/recipes-devtools/elfutils/files/debian/0001-arm_backend.patch627
1 files changed, 627 insertions, 0 deletions
diff --git a/meta/recipes-devtools/elfutils/files/debian/0001-arm_backend.patch b/meta/recipes-devtools/elfutils/files/debian/0001-arm_backend.patch
new file mode 100644
index 0000000000..540ba95e0e
--- /dev/null
+++ b/meta/recipes-devtools/elfutils/files/debian/0001-arm_backend.patch
@@ -0,0 +1,627 @@
1From a95f370bc2690c150c46f215543de278469900eb Mon Sep 17 00:00:00 2001
2From: Hongxu Jia <hongxu.jia@windriver.com>
3Date: Fri, 29 Jun 2018 15:42:39 +0800
4Subject: [PATCH] arm_backend
5
6Upstream-Status: Backport from debian
7arm_backend.diff and rebase to 0.172
8
9http://ftp.de.debian.org/debian/pool/main/e/elfutils/elfutils_0.170-0.5.debian.tar.xz
10
11Signed-off-by: Hongxu Jia <hongxu.jia@windriver.com>
12---
13 backends/arm_init.c | 18 ++++-
14 backends/arm_regs.c | 132 ++++++++++++++++++++++++++++++++++++
15 backends/arm_retval.c | 43 +++++++++++-
16 backends/libebl_arm.h | 9 +++
17 libelf/elf.h | 11 +++
18 tests/run-addrcfi.sh | 93 ++++++++++++++++++++++++-
19 tests/run-allregs.sh | 95 +++++++++++++++++++++++++-
20 tests/run-readelf-mixed-corenote.sh | 11 ++-
21 8 files changed, 400 insertions(+), 12 deletions(-)
22 create mode 100644 backends/libebl_arm.h
23
24diff --git a/backends/arm_init.c b/backends/arm_init.c
25index f2b1b11..1b71f16 100644
26--- a/backends/arm_init.c
27+++ b/backends/arm_init.c
28@@ -35,20 +35,31 @@
29 #define RELOC_PREFIX R_ARM_
30 #include "libebl_CPU.h"
31
32+#include "libebl_arm.h"
33+
34 /* This defines the common reloc hooks based on arm_reloc.def. */
35 #include "common-reloc.c"
36
37
38 const char *
39-arm_init (Elf *elf __attribute__ ((unused)),
40+arm_init (Elf *elf,
41 GElf_Half machine __attribute__ ((unused)),
42 Ebl *eh,
43 size_t ehlen)
44 {
45+ int soft_float = 0;
46+
47 /* Check whether the Elf_BH object has a sufficent size. */
48 if (ehlen < sizeof (Ebl))
49 return NULL;
50
51+ if (elf) {
52+ GElf_Ehdr ehdr_mem;
53+ GElf_Ehdr *ehdr = gelf_getehdr (elf, &ehdr_mem);
54+ if (ehdr && (ehdr->e_flags & EF_ARM_SOFT_FLOAT))
55+ soft_float = 1;
56+ }
57+
58 /* We handle it. */
59 eh->name = "ARM";
60 arm_init_reloc (eh);
61@@ -60,7 +71,10 @@ arm_init (Elf *elf __attribute__ ((unused)),
62 HOOK (eh, core_note);
63 HOOK (eh, auxv_info);
64 HOOK (eh, check_object_attribute);
65- HOOK (eh, return_value_location);
66+ if (soft_float)
67+ eh->return_value_location = arm_return_value_location_soft;
68+ else
69+ eh->return_value_location = arm_return_value_location_hard;
70 HOOK (eh, abi_cfi);
71 HOOK (eh, check_reloc_target_type);
72 HOOK (eh, symbol_type_name);
73diff --git a/backends/arm_regs.c b/backends/arm_regs.c
74index a46a4c9..418c931 100644
75--- a/backends/arm_regs.c
76+++ b/backends/arm_regs.c
77@@ -31,6 +31,7 @@
78 #endif
79
80 #include <string.h>
81+#include <stdio.h>
82 #include <dwarf.h>
83
84 #define BACKEND arm_
85@@ -76,6 +77,9 @@ arm_register_info (Ebl *ebl __attribute__ ((unused)),
86 break;
87
88 case 16 + 0 ... 16 + 7:
89+ /* AADWARF says that there are no registers in that range,
90+ * but gcc maps FPA registers here
91+ */
92 regno += 96 - 16;
93 FALLTHROUGH;
94 case 96 + 0 ... 96 + 7:
95@@ -87,11 +91,139 @@ arm_register_info (Ebl *ebl __attribute__ ((unused)),
96 namelen = 2;
97 break;
98
99+ case 64 + 0 ... 64 + 9:
100+ *setname = "VFP";
101+ *bits = 32;
102+ *type = DW_ATE_float;
103+ name[0] = 's';
104+ name[1] = regno - 64 + '0';
105+ namelen = 2;
106+ break;
107+
108+ case 64 + 10 ... 64 + 31:
109+ *setname = "VFP";
110+ *bits = 32;
111+ *type = DW_ATE_float;
112+ name[0] = 's';
113+ name[1] = (regno - 64) / 10 + '0';
114+ name[2] = (regno - 64) % 10 + '0';
115+ namelen = 3;
116+ break;
117+
118+ case 104 + 0 ... 104 + 7:
119+ /* XXX TODO:
120+ * This can be either intel wireless MMX general purpose/control
121+ * registers or xscale accumulator, which have different usage.
122+ * We only have the intel wireless MMX here now.
123+ * The name needs to be changed for the xscale accumulator too. */
124+ *setname = "MMX";
125+ *type = DW_ATE_unsigned;
126+ *bits = 32;
127+ memcpy(name, "wcgr", 4);
128+ name[4] = regno - 104 + '0';
129+ namelen = 5;
130+ break;
131+
132+ case 112 + 0 ... 112 + 9:
133+ *setname = "MMX";
134+ *type = DW_ATE_unsigned;
135+ *bits = 64;
136+ name[0] = 'w';
137+ name[1] = 'r';
138+ name[2] = regno - 112 + '0';
139+ namelen = 3;
140+ break;
141+
142+ case 112 + 10 ... 112 + 15:
143+ *setname = "MMX";
144+ *type = DW_ATE_unsigned;
145+ *bits = 64;
146+ name[0] = 'w';
147+ name[1] = 'r';
148+ name[2] = '1';
149+ name[3] = regno - 112 - 10 + '0';
150+ namelen = 4;
151+ break;
152+
153 case 128:
154+ *setname = "state";
155 *type = DW_ATE_unsigned;
156 return stpcpy (name, "spsr") + 1 - name;
157
158+ case 129:
159+ *setname = "state";
160+ *type = DW_ATE_unsigned;
161+ return stpcpy(name, "spsr_fiq") + 1 - name;
162+
163+ case 130:
164+ *setname = "state";
165+ *type = DW_ATE_unsigned;
166+ return stpcpy(name, "spsr_irq") + 1 - name;
167+
168+ case 131:
169+ *setname = "state";
170+ *type = DW_ATE_unsigned;
171+ return stpcpy(name, "spsr_abt") + 1 - name;
172+
173+ case 132:
174+ *setname = "state";
175+ *type = DW_ATE_unsigned;
176+ return stpcpy(name, "spsr_und") + 1 - name;
177+
178+ case 133:
179+ *setname = "state";
180+ *type = DW_ATE_unsigned;
181+ return stpcpy(name, "spsr_svc") + 1 - name;
182+
183+ case 144 ... 150:
184+ *setname = "integer";
185+ *type = DW_ATE_signed;
186+ *bits = 32;
187+ return sprintf(name, "r%d_usr", regno - 144 + 8) + 1;
188+
189+ case 151 ... 157:
190+ *setname = "integer";
191+ *type = DW_ATE_signed;
192+ *bits = 32;
193+ return sprintf(name, "r%d_fiq", regno - 151 + 8) + 1;
194+
195+ case 158 ... 159:
196+ *setname = "integer";
197+ *type = DW_ATE_signed;
198+ *bits = 32;
199+ return sprintf(name, "r%d_irq", regno - 158 + 13) + 1;
200+
201+ case 160 ... 161:
202+ *setname = "integer";
203+ *type = DW_ATE_signed;
204+ *bits = 32;
205+ return sprintf(name, "r%d_abt", regno - 160 + 13) + 1;
206+
207+ case 162 ... 163:
208+ *setname = "integer";
209+ *type = DW_ATE_signed;
210+ *bits = 32;
211+ return sprintf(name, "r%d_und", regno - 162 + 13) + 1;
212+
213+ case 164 ... 165:
214+ *setname = "integer";
215+ *type = DW_ATE_signed;
216+ *bits = 32;
217+ return sprintf(name, "r%d_svc", regno - 164 + 13) + 1;
218+
219+ case 192 ... 199:
220+ *setname = "MMX";
221+ *bits = 32;
222+ *type = DW_ATE_unsigned;
223+ name[0] = 'w';
224+ name[1] = 'c';
225+ name[2] = regno - 192 + '0';
226+ namelen = 3;
227+ break;
228+
229 case 256 + 0 ... 256 + 9:
230+ /* XXX TODO: Neon also uses those registers and can contain
231+ * both float and integers */
232 *setname = "VFP";
233 *type = DW_ATE_float;
234 *bits = 64;
235diff --git a/backends/arm_retval.c b/backends/arm_retval.c
236index 1c28f01..313e4eb 100644
237--- a/backends/arm_retval.c
238+++ b/backends/arm_retval.c
239@@ -48,6 +48,13 @@ static const Dwarf_Op loc_intreg[] =
240 #define nloc_intreg 1
241 #define nloc_intregs(n) (2 * (n))
242
243+/* f1 */ /* XXX TODO: f0 can also have number 96 if program was compiled with -mabi=aapcs */
244+static const Dwarf_Op loc_fpreg[] =
245+ {
246+ { .atom = DW_OP_reg16 },
247+ };
248+#define nloc_fpreg 1
249+
250 /* The return value is a structure and is actually stored in stack space
251 passed in a hidden argument by the caller. But, the compiler
252 helpfully returns the address of that space in r0. */
253@@ -58,8 +65,9 @@ static const Dwarf_Op loc_aggregate[] =
254 #define nloc_aggregate 1
255
256
257-int
258-arm_return_value_location (Dwarf_Die *functypedie, const Dwarf_Op **locp)
259+static int
260+arm_return_value_location_ (Dwarf_Die *functypedie, const Dwarf_Op **locp,
261+ int soft_float)
262 {
263 /* Start with the function's type, and get the DW_AT_type attribute,
264 which is the type of the return value. */
265@@ -98,6 +106,21 @@ arm_return_value_location (Dwarf_Die *functypedie, const Dwarf_Op **locp)
266 else
267 return -1;
268 }
269+ if (tag == DW_TAG_base_type)
270+ {
271+ Dwarf_Word encoding;
272+ if (dwarf_formudata (dwarf_attr_integrate (typedie, DW_AT_encoding,
273+ &attr_mem), &encoding) != 0)
274+ return -1;
275+
276+ if ((encoding == DW_ATE_float) && !soft_float)
277+ {
278+ *locp = loc_fpreg;
279+ if (size <= 8)
280+ return nloc_fpreg;
281+ goto aggregate;
282+ }
283+ }
284 if (size <= 16)
285 {
286 intreg:
287@@ -106,6 +129,7 @@ arm_return_value_location (Dwarf_Die *functypedie, const Dwarf_Op **locp)
288 }
289
290 aggregate:
291+ /* XXX TODO sometimes aggregates are returned in r0 (-mabi=aapcs) */
292 *locp = loc_aggregate;
293 return nloc_aggregate;
294 }
295@@ -125,3 +149,18 @@ arm_return_value_location (Dwarf_Die *functypedie, const Dwarf_Op **locp)
296 DWARF and might be valid. */
297 return -2;
298 }
299+
300+/* return location for -mabi=apcs-gnu -msoft-float */
301+int
302+arm_return_value_location_soft (Dwarf_Die *functypedie, const Dwarf_Op **locp)
303+{
304+ return arm_return_value_location_ (functypedie, locp, 1);
305+}
306+
307+/* return location for -mabi=apcs-gnu -mhard-float (current default) */
308+int
309+arm_return_value_location_hard (Dwarf_Die *functypedie, const Dwarf_Op **locp)
310+{
311+ return arm_return_value_location_ (functypedie, locp, 0);
312+}
313+
314diff --git a/backends/libebl_arm.h b/backends/libebl_arm.h
315new file mode 100644
316index 0000000..c00770c
317--- /dev/null
318+++ b/backends/libebl_arm.h
319@@ -0,0 +1,9 @@
320+#ifndef _LIBEBL_ARM_H
321+#define _LIBEBL_ARM_H 1
322+
323+#include <libdw.h>
324+
325+extern int arm_return_value_location_soft(Dwarf_Die *, const Dwarf_Op **locp);
326+extern int arm_return_value_location_hard(Dwarf_Die *, const Dwarf_Op **locp);
327+
328+#endif
329diff --git a/libelf/elf.h b/libelf/elf.h
330index 6c9f61e..6d82fef 100644
331--- a/libelf/elf.h
332+++ b/libelf/elf.h
333@@ -2692,6 +2692,9 @@ enum
334 #define EF_ARM_EABI_VER4 0x04000000
335 #define EF_ARM_EABI_VER5 0x05000000
336
337+/* EI_OSABI values */
338+#define ELFOSABI_ARM_AEABI 64 /* Contains symbol versioning. */
339+
340 /* Additional symbol types for Thumb. */
341 #define STT_ARM_TFUNC STT_LOPROC /* A Thumb function. */
342 #define STT_ARM_16BIT STT_HIPROC /* A Thumb label. */
343@@ -2709,12 +2712,19 @@ enum
344
345 /* Processor specific values for the Phdr p_type field. */
346 #define PT_ARM_EXIDX (PT_LOPROC + 1) /* ARM unwind segment. */
347+#define PT_ARM_UNWIND PT_ARM_EXIDX
348
349 /* Processor specific values for the Shdr sh_type field. */
350 #define SHT_ARM_EXIDX (SHT_LOPROC + 1) /* ARM unwind section. */
351 #define SHT_ARM_PREEMPTMAP (SHT_LOPROC + 2) /* Preemption details. */
352 #define SHT_ARM_ATTRIBUTES (SHT_LOPROC + 3) /* ARM attributes section. */
353
354+/* Processor specific values for the Dyn d_tag field. */
355+#define DT_ARM_RESERVED1 (DT_LOPROC + 0)
356+#define DT_ARM_SYMTABSZ (DT_LOPROC + 1)
357+#define DT_ARM_PREEMTMAB (DT_LOPROC + 2)
358+#define DT_ARM_RESERVED2 (DT_LOPROC + 3)
359+#define DT_ARM_NUM 4
360
361 /* AArch64 relocs. */
362
363@@ -3007,6 +3017,7 @@ enum
364 TLS block (LDR, STR). */
365 #define R_ARM_TLS_IE12GP 111 /* 12 bit GOT entry relative
366 to GOT origin (LDR). */
367+/* 112 - 127 private range */
368 #define R_ARM_ME_TOO 128 /* Obsolete. */
369 #define R_ARM_THM_TLS_DESCSEQ 129
370 #define R_ARM_THM_TLS_DESCSEQ16 129
371diff --git a/tests/run-addrcfi.sh b/tests/run-addrcfi.sh
372index fd89d02..462d7c5 100755
373--- a/tests/run-addrcfi.sh
374+++ b/tests/run-addrcfi.sh
375@@ -3554,6 +3554,38 @@ dwarf_cfi_addrframe (.eh_frame): no matching address range
376 FPA reg21 (f5): undefined
377 FPA reg22 (f6): undefined
378 FPA reg23 (f7): undefined
379+ VFP reg64 (s0): undefined
380+ VFP reg65 (s1): undefined
381+ VFP reg66 (s2): undefined
382+ VFP reg67 (s3): undefined
383+ VFP reg68 (s4): undefined
384+ VFP reg69 (s5): undefined
385+ VFP reg70 (s6): undefined
386+ VFP reg71 (s7): undefined
387+ VFP reg72 (s8): undefined
388+ VFP reg73 (s9): undefined
389+ VFP reg74 (s10): undefined
390+ VFP reg75 (s11): undefined
391+ VFP reg76 (s12): undefined
392+ VFP reg77 (s13): undefined
393+ VFP reg78 (s14): undefined
394+ VFP reg79 (s15): undefined
395+ VFP reg80 (s16): undefined
396+ VFP reg81 (s17): undefined
397+ VFP reg82 (s18): undefined
398+ VFP reg83 (s19): undefined
399+ VFP reg84 (s20): undefined
400+ VFP reg85 (s21): undefined
401+ VFP reg86 (s22): undefined
402+ VFP reg87 (s23): undefined
403+ VFP reg88 (s24): undefined
404+ VFP reg89 (s25): undefined
405+ VFP reg90 (s26): undefined
406+ VFP reg91 (s27): undefined
407+ VFP reg92 (s28): undefined
408+ VFP reg93 (s29): undefined
409+ VFP reg94 (s30): undefined
410+ VFP reg95 (s31): undefined
411 FPA reg96 (f0): undefined
412 FPA reg97 (f1): undefined
413 FPA reg98 (f2): undefined
414@@ -3562,7 +3594,66 @@ dwarf_cfi_addrframe (.eh_frame): no matching address range
415 FPA reg101 (f5): undefined
416 FPA reg102 (f6): undefined
417 FPA reg103 (f7): undefined
418- integer reg128 (spsr): undefined
419+ MMX reg104 (wcgr0): undefined
420+ MMX reg105 (wcgr1): undefined
421+ MMX reg106 (wcgr2): undefined
422+ MMX reg107 (wcgr3): undefined
423+ MMX reg108 (wcgr4): undefined
424+ MMX reg109 (wcgr5): undefined
425+ MMX reg110 (wcgr6): undefined
426+ MMX reg111 (wcgr7): undefined
427+ MMX reg112 (wr0): undefined
428+ MMX reg113 (wr1): undefined
429+ MMX reg114 (wr2): undefined
430+ MMX reg115 (wr3): undefined
431+ MMX reg116 (wr4): undefined
432+ MMX reg117 (wr5): undefined
433+ MMX reg118 (wr6): undefined
434+ MMX reg119 (wr7): undefined
435+ MMX reg120 (wr8): undefined
436+ MMX reg121 (wr9): undefined
437+ MMX reg122 (wr10): undefined
438+ MMX reg123 (wr11): undefined
439+ MMX reg124 (wr12): undefined
440+ MMX reg125 (wr13): undefined
441+ MMX reg126 (wr14): undefined
442+ MMX reg127 (wr15): undefined
443+ state reg128 (spsr): undefined
444+ state reg129 (spsr_fiq): undefined
445+ state reg130 (spsr_irq): undefined
446+ state reg131 (spsr_abt): undefined
447+ state reg132 (spsr_und): undefined
448+ state reg133 (spsr_svc): undefined
449+ integer reg144 (r8_usr): undefined
450+ integer reg145 (r9_usr): undefined
451+ integer reg146 (r10_usr): undefined
452+ integer reg147 (r11_usr): undefined
453+ integer reg148 (r12_usr): undefined
454+ integer reg149 (r13_usr): undefined
455+ integer reg150 (r14_usr): undefined
456+ integer reg151 (r8_fiq): undefined
457+ integer reg152 (r9_fiq): undefined
458+ integer reg153 (r10_fiq): undefined
459+ integer reg154 (r11_fiq): undefined
460+ integer reg155 (r12_fiq): undefined
461+ integer reg156 (r13_fiq): undefined
462+ integer reg157 (r14_fiq): undefined
463+ integer reg158 (r13_irq): undefined
464+ integer reg159 (r14_irq): undefined
465+ integer reg160 (r13_abt): undefined
466+ integer reg161 (r14_abt): undefined
467+ integer reg162 (r13_und): undefined
468+ integer reg163 (r14_und): undefined
469+ integer reg164 (r13_svc): undefined
470+ integer reg165 (r14_svc): undefined
471+ MMX reg192 (wc0): undefined
472+ MMX reg193 (wc1): undefined
473+ MMX reg194 (wc2): undefined
474+ MMX reg195 (wc3): undefined
475+ MMX reg196 (wc4): undefined
476+ MMX reg197 (wc5): undefined
477+ MMX reg198 (wc6): undefined
478+ MMX reg199 (wc7): undefined
479 VFP reg256 (d0): undefined
480 VFP reg257 (d1): undefined
481 VFP reg258 (d2): undefined
482diff --git a/tests/run-allregs.sh b/tests/run-allregs.sh
483index 7ddd452..a31dba4 100755
484--- a/tests/run-allregs.sh
485+++ b/tests/run-allregs.sh
486@@ -2672,7 +2672,28 @@ integer registers:
487 13: sp (sp), address 32 bits
488 14: lr (lr), address 32 bits
489 15: pc (pc), address 32 bits
490- 128: spsr (spsr), unsigned 32 bits
491+ 144: r8_usr (r8_usr), signed 32 bits
492+ 145: r9_usr (r9_usr), signed 32 bits
493+ 146: r10_usr (r10_usr), signed 32 bits
494+ 147: r11_usr (r11_usr), signed 32 bits
495+ 148: r12_usr (r12_usr), signed 32 bits
496+ 149: r13_usr (r13_usr), signed 32 bits
497+ 150: r14_usr (r14_usr), signed 32 bits
498+ 151: r8_fiq (r8_fiq), signed 32 bits
499+ 152: r9_fiq (r9_fiq), signed 32 bits
500+ 153: r10_fiq (r10_fiq), signed 32 bits
501+ 154: r11_fiq (r11_fiq), signed 32 bits
502+ 155: r12_fiq (r12_fiq), signed 32 bits
503+ 156: r13_fiq (r13_fiq), signed 32 bits
504+ 157: r14_fiq (r14_fiq), signed 32 bits
505+ 158: r13_irq (r13_irq), signed 32 bits
506+ 159: r14_irq (r14_irq), signed 32 bits
507+ 160: r13_abt (r13_abt), signed 32 bits
508+ 161: r14_abt (r14_abt), signed 32 bits
509+ 162: r13_und (r13_und), signed 32 bits
510+ 163: r14_und (r14_und), signed 32 bits
511+ 164: r13_svc (r13_svc), signed 32 bits
512+ 165: r14_svc (r14_svc), signed 32 bits
513 FPA registers:
514 16: f0 (f0), float 96 bits
515 17: f1 (f1), float 96 bits
516@@ -2690,7 +2711,72 @@ FPA registers:
517 101: f5 (f5), float 96 bits
518 102: f6 (f6), float 96 bits
519 103: f7 (f7), float 96 bits
520+MMX registers:
521+ 104: wcgr0 (wcgr0), unsigned 32 bits
522+ 105: wcgr1 (wcgr1), unsigned 32 bits
523+ 106: wcgr2 (wcgr2), unsigned 32 bits
524+ 107: wcgr3 (wcgr3), unsigned 32 bits
525+ 108: wcgr4 (wcgr4), unsigned 32 bits
526+ 109: wcgr5 (wcgr5), unsigned 32 bits
527+ 110: wcgr6 (wcgr6), unsigned 32 bits
528+ 111: wcgr7 (wcgr7), unsigned 32 bits
529+ 112: wr0 (wr0), unsigned 64 bits
530+ 113: wr1 (wr1), unsigned 64 bits
531+ 114: wr2 (wr2), unsigned 64 bits
532+ 115: wr3 (wr3), unsigned 64 bits
533+ 116: wr4 (wr4), unsigned 64 bits
534+ 117: wr5 (wr5), unsigned 64 bits
535+ 118: wr6 (wr6), unsigned 64 bits
536+ 119: wr7 (wr7), unsigned 64 bits
537+ 120: wr8 (wr8), unsigned 64 bits
538+ 121: wr9 (wr9), unsigned 64 bits
539+ 122: wr10 (wr10), unsigned 64 bits
540+ 123: wr11 (wr11), unsigned 64 bits
541+ 124: wr12 (wr12), unsigned 64 bits
542+ 125: wr13 (wr13), unsigned 64 bits
543+ 126: wr14 (wr14), unsigned 64 bits
544+ 127: wr15 (wr15), unsigned 64 bits
545+ 192: wc0 (wc0), unsigned 32 bits
546+ 193: wc1 (wc1), unsigned 32 bits
547+ 194: wc2 (wc2), unsigned 32 bits
548+ 195: wc3 (wc3), unsigned 32 bits
549+ 196: wc4 (wc4), unsigned 32 bits
550+ 197: wc5 (wc5), unsigned 32 bits
551+ 198: wc6 (wc6), unsigned 32 bits
552+ 199: wc7 (wc7), unsigned 32 bits
553 VFP registers:
554+ 64: s0 (s0), float 32 bits
555+ 65: s1 (s1), float 32 bits
556+ 66: s2 (s2), float 32 bits
557+ 67: s3 (s3), float 32 bits
558+ 68: s4 (s4), float 32 bits
559+ 69: s5 (s5), float 32 bits
560+ 70: s6 (s6), float 32 bits
561+ 71: s7 (s7), float 32 bits
562+ 72: s8 (s8), float 32 bits
563+ 73: s9 (s9), float 32 bits
564+ 74: s10 (s10), float 32 bits
565+ 75: s11 (s11), float 32 bits
566+ 76: s12 (s12), float 32 bits
567+ 77: s13 (s13), float 32 bits
568+ 78: s14 (s14), float 32 bits
569+ 79: s15 (s15), float 32 bits
570+ 80: s16 (s16), float 32 bits
571+ 81: s17 (s17), float 32 bits
572+ 82: s18 (s18), float 32 bits
573+ 83: s19 (s19), float 32 bits
574+ 84: s20 (s20), float 32 bits
575+ 85: s21 (s21), float 32 bits
576+ 86: s22 (s22), float 32 bits
577+ 87: s23 (s23), float 32 bits
578+ 88: s24 (s24), float 32 bits
579+ 89: s25 (s25), float 32 bits
580+ 90: s26 (s26), float 32 bits
581+ 91: s27 (s27), float 32 bits
582+ 92: s28 (s28), float 32 bits
583+ 93: s29 (s29), float 32 bits
584+ 94: s30 (s30), float 32 bits
585+ 95: s31 (s31), float 32 bits
586 256: d0 (d0), float 64 bits
587 257: d1 (d1), float 64 bits
588 258: d2 (d2), float 64 bits
589@@ -2723,6 +2809,13 @@ VFP registers:
590 285: d29 (d29), float 64 bits
591 286: d30 (d30), float 64 bits
592 287: d31 (d31), float 64 bits
593+state registers:
594+ 128: spsr (spsr), unsigned 32 bits
595+ 129: spsr_fiq (spsr_fiq), unsigned 32 bits
596+ 130: spsr_irq (spsr_irq), unsigned 32 bits
597+ 131: spsr_abt (spsr_abt), unsigned 32 bits
598+ 132: spsr_und (spsr_und), unsigned 32 bits
599+ 133: spsr_svc (spsr_svc), unsigned 32 bits
600 EOF
601
602 # See run-readelf-mixed-corenote.sh for instructions to regenerate
603diff --git a/tests/run-readelf-mixed-corenote.sh b/tests/run-readelf-mixed-corenote.sh
604index 86171c4..018612f 100755
605--- a/tests/run-readelf-mixed-corenote.sh
606+++ b/tests/run-readelf-mixed-corenote.sh
607@@ -31,12 +31,11 @@ Note segment of 892 bytes at offset 0x274:
608 pid: 11087, ppid: 11063, pgrp: 11087, sid: 11063
609 utime: 0.000000, stime: 0.010000, cutime: 0.000000, cstime: 0.000000
610 orig_r0: -1, fpvalid: 1
611- r0: 1 r1: -1091672508 r2: -1091672500
612- r3: 0 r4: 0 r5: 0
613- r6: 33728 r7: 0 r8: 0
614- r9: 0 r10: -1225703496 r11: -1091672844
615- r12: 0 sp: 0xbeee64f4 lr: 0xb6dc3f48
616- pc: 0x00008500 spsr: 0x60000010
617+ r0: 1 r1: -1091672508 r2: -1091672500 r3: 0
618+ r4: 0 r5: 0 r6: 33728 r7: 0
619+ r8: 0 r9: 0 r10: -1225703496 r11: -1091672844
620+ r12: 0 sp: 0xbeee64f4 lr: 0xb6dc3f48 pc: 0x00008500
621+ spsr: 0x60000010
622 CORE 124 PRPSINFO
623 state: 0, sname: R, zomb: 0, nice: 0, flag: 0x00400500
624 uid: 0, gid: 0, pid: 11087, ppid: 11063, pgrp: 11087, sid: 11063
625--
6262.7.4
627
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2026-02-13 04:53:04 +0000