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| author | Alejandro Hernandez Samaniego <alejandro@enedino.org> | 2021-08-07 22:14:51 -0600 |
|---|---|---|
| committer | Richard Purdie <richard.purdie@linuxfoundation.org> | 2021-08-12 06:26:16 +0100 |
| commit | 650b720f1919987ed7593d117c81c1db1b2f7da0 (patch) | |
| tree | 28c88d1485ef98fde62910ce18c42a10c2546fb3 /meta/classes | |
| parent | 8ae0ee62cacb613f93f5b81ddf30083a97e39a43 (diff) | |
| download | poky-650b720f1919987ed7593d117c81c1db1b2f7da0.tar.gz | |
baremetal-helloworld: Enable RISC-V 32 port
$ runqemu nographic
runqemu - INFO - Running bitbake -e ...
KERNEL: [tmp/deploy/images/qemuriscv32/baremetal-helloworld-image-qemuriscv32.bin]
MACHINE: [qemuriscv32]
runqemu - INFO - Running tmp/work/x86_64-linux/qemu-helper-native/1.0-r1/recipe-sysroot-native/usr/bin/qemu-system-riscv32
Hello OpenEmbedded on RISC-V 32!
(From OE-Core rev: d4cca7471f2167b56347fa7b1364bb84a200b1f5)
Signed-off-by: Alejandro Enedino Hernandez Samaniego <alejandro@enedino.org>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
Diffstat (limited to 'meta/classes')
| -rw-r--r-- | meta/classes/baremetal-image.bbclass | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/meta/classes/baremetal-image.bbclass b/meta/classes/baremetal-image.bbclass index 9ec3f1460b..089c445522 100644 --- a/meta/classes/baremetal-image.bbclass +++ b/meta/classes/baremetal-image.bbclass | |||
| @@ -82,12 +82,15 @@ QB_OPT_APPEND:append = " -nographic" | |||
| 82 | # RISC-V tunes set the BIOS, unset, and instruct QEMU to | 82 | # RISC-V tunes set the BIOS, unset, and instruct QEMU to |
| 83 | # ignore the BIOS and boot from -kernel | 83 | # ignore the BIOS and boot from -kernel |
| 84 | QB_DEFAULT_BIOS:qemuriscv64 = "" | 84 | QB_DEFAULT_BIOS:qemuriscv64 = "" |
| 85 | QB_DEFAULT_BIOS:qemuriscv32 = "" | ||
| 85 | QB_OPT_APPEND:append:qemuriscv64 = " -bios none" | 86 | QB_OPT_APPEND:append:qemuriscv64 = " -bios none" |
| 87 | QB_OPT_APPEND:append:qemuriscv32 = " -bios none" | ||
| 86 | 88 | ||
| 87 | 89 | ||
| 88 | # Use the medium-any code model for the RISC-V 64 bit implementation, | 90 | # Use the medium-any code model for the RISC-V 64 bit implementation, |
| 89 | # since medlow can only access addresses below 0x80000000 and RAM | 91 | # since medlow can only access addresses below 0x80000000 and RAM |
| 90 | # starts at 0x80000000 on RISC-V 64 | 92 | # starts at 0x80000000 on RISC-V 64 |
| 93 | # Keep RISC-V 32 using -mcmodel=medlow (symbols lie between -2GB:2GB) | ||
| 91 | CFLAGS:append:qemuriscv64 = " -mcmodel=medany" | 94 | CFLAGS:append:qemuriscv64 = " -mcmodel=medany" |
| 92 | 95 | ||
| 93 | 96 | ||
