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authorKhem Raj <raj.khem@gmail.com>2025-08-18 18:01:26 -0700
committerRichard Purdie <richard.purdie@linuxfoundation.org>2025-08-28 10:47:08 +0100
commit07a6f2bbe385aa638ddbdede20740df619706ad7 (patch)
tree8d045b5341a8b115af575db6221d67580a6f0a75
parent24253d8818b706053d8916d4f249a9738fcaa061 (diff)
downloadpoky-07a6f2bbe385aa638ddbdede20740df619706ad7.tar.gz
spirv-headers: Add SPV_INTEL_function_variants
Needed for the clang 21 upgrade (From OE-Core rev: 79c1594bb0a8075a0d7b5c281f996e54c5351630) Signed-off-by: Khem Raj <raj.khem@gmail.com> Signed-off-by: Mathieu Dubois-Briand <mathieu.dubois-briand@bootlin.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
Diffstat
-rw-r--r--meta/recipes-graphics/spir/spirv-headers/0001-Add-SPV_INTEL_function_variants-532.patch642
-rw-r--r--meta/recipes-graphics/spir/spirv-headers_1.4.321.0.bb4
2 files changed, 645 insertions, 1 deletions
diff --git a/meta/recipes-graphics/spir/spirv-headers/0001-Add-SPV_INTEL_function_variants-532.patch b/meta/recipes-graphics/spir/spirv-headers/0001-Add-SPV_INTEL_function_variants-532.patch
new file mode 100644
index 0000000000..9a3ab15350
--- /dev/null
+++ b/meta/recipes-graphics/spir/spirv-headers/0001-Add-SPV_INTEL_function_variants-532.patch
@@ -0,0 +1,642 @@
1From 9e3836d7d6023843a72ecd3fbf3f09b1b6747a9e Mon Sep 17 00:00:00 2001
2From: =?UTF-8?q?Jakub=20=C5=BD=C3=A1dn=C3=ADk?= <jakub.zadnik@intel.com>
3Date: Tue, 24 Jun 2025 15:35:27 +0300
4Subject: [PATCH] Add SPV_INTEL_function_variants (#532)
5
6* Add tokens for SPV_INTEL_function_variants
7
8Add FunctionVariantXXX decorations
9
10Add SpecConditionalINTEL capability
11
12Change class of conditional copy to Composite
13
14Add new instructions; Update tokens
15
16Fix wrong op name
17
18Change spec const arch operand to integer
19
20Reassign tokens; Fix operand
21
22Remove old decorations
23
24* Generate headers
25
26* Add provisional entries and missing capability
27
28Co-authored-by: Victor Lomuller <victor@codeplay.com>
29
30---------
31
32Upstream-Status: Backport [https://github.com/KhronosGroup/SPIRV-Headers/commit/9e3836d7d6023843a72ecd3fbf3f09b1b6747a9e]
33Signed-off-by: Khem Raj <raj.khem@gmail.com>
34Co-authored-by: Victor Lomuller <victor@codeplay.com>
35---
36 include/spirv/unified1/spirv.bf | 10 ++
37 .../spirv/unified1/spirv.core.grammar.json | 120 ++++++++++++++++++
38 include/spirv/unified1/spirv.cs | 10 ++
39 include/spirv/unified1/spirv.h | 27 ++++
40 include/spirv/unified1/spirv.hpp | 27 ++++
41 include/spirv/unified1/spirv.hpp11 | 27 ++++
42 include/spirv/unified1/spirv.json | 10 ++
43 include/spirv/unified1/spirv.lua | 10 ++
44 include/spirv/unified1/spirv.py | 10 ++
45 include/spirv/unified1/spv.d | 10 ++
46 10 files changed, 261 insertions(+)
47
48diff --git a/include/spirv/unified1/spirv.bf b/include/spirv/unified1/spirv.bf
49index 1d5945a..630f2f4 100644
50--- a/include/spirv/unified1/spirv.bf
51+++ b/include/spirv/unified1/spirv.bf
52@@ -655,6 +655,7 @@ namespace Spv
53 HostAccessINTEL = 6188,
54 InitModeINTEL = 6190,
55 ImplementInRegisterMapINTEL = 6191,
56+ ConditionalINTEL = 6247,
57 CacheControlLoadINTEL = 6442,
58 CacheControlStoreINTEL = 6443,
59 Max = 0x7fffffff,
60@@ -1312,6 +1313,8 @@ namespace Spv
61 Subgroup2DBlockTransposeINTEL = 6230,
62 SubgroupMatrixMultiplyAccumulateINTEL = 6236,
63 TernaryBitwiseFunctionINTEL = 6241,
64+ SpecConditionalINTEL = 6245,
65+ FunctionVariantsINTEL = 6246,
66 GroupUniformArithmeticKHR = 6400,
67 TensorFloat32RoundingINTEL = 6425,
68 MaskedGatherScatterINTEL = 6427,
69@@ -2472,6 +2475,13 @@ namespace Spv
70 OpSubgroup2DBlockStoreINTEL = 6235,
71 OpSubgroupMatrixMultiplyAccumulateINTEL = 6237,
72 OpBitwiseFunctionINTEL = 6242,
73+ OpConditionalExtensionINTEL = 6248,
74+ OpConditionalEntryPointINTEL = 6249,
75+ OpConditionalCapabilityINTEL = 6250,
76+ OpSpecConstantTargetINTEL = 6251,
77+ OpSpecConstantArchitectureINTEL = 6252,
78+ OpSpecConstantCapabilitiesINTEL = 6253,
79+ OpConditionalCopyObjectINTEL = 6254,
80 OpGroupIMulKHR = 6401,
81 OpGroupFMulKHR = 6402,
82 OpGroupBitwiseAndKHR = 6403,
83diff --git a/include/spirv/unified1/spirv.core.grammar.json b/include/spirv/unified1/spirv.core.grammar.json
84index b197d9e..2470bfa 100644
85--- a/include/spirv/unified1/spirv.core.grammar.json
86+++ b/include/spirv/unified1/spirv.core.grammar.json
87@@ -10777,6 +10777,101 @@
88 "capabilities" : [ "TernaryBitwiseFunctionINTEL" ],
89 "version" : "None"
90 },
91+ {
92+ "opname" : "OpConditionalExtensionINTEL",
93+ "class" : "Extension",
94+ "opcode" : 6248,
95+ "operands" : [
96+ { "kind" : "IdRef", "name" : "Condition" },
97+ { "kind" : "LiteralString", "name" : "Name" }
98+ ],
99+ "capabilities" : [ "SpecConditionalINTEL" ],
100+ "provisional" : true,
101+ "version" : "None"
102+ },
103+ {
104+ "opname" : "OpConditionalEntryPointINTEL",
105+ "class" : "Mode-Setting",
106+ "opcode" : 6249,
107+ "operands" : [
108+ { "kind" : "IdRef", "name" : "Condition" },
109+ { "kind" : "ExecutionModel" },
110+ { "kind" : "IdRef", "name" : "Entry Point" },
111+ { "kind" : "LiteralString", "name" : "Name" },
112+ { "kind" : "IdRef", "quantifier" : "*", "name" : "Interface" }
113+ ],
114+ "capabilities" : [ "SpecConditionalINTEL" ],
115+ "provisional" : true,
116+ "version" : "None"
117+ },
118+ {
119+ "opname" : "OpConditionalCapabilityINTEL",
120+ "class" : "Mode-Setting",
121+ "opcode" : 6250,
122+ "operands" : [
123+ { "kind" : "IdRef", "name" : "Condition" },
124+ { "kind" : "Capability", "name" : "Capability" }
125+ ],
126+ "capabilities" : [ "SpecConditionalINTEL" ],
127+ "provisional" : true,
128+ "version" : "None"
129+ },
130+ {
131+ "opname" : "OpSpecConstantTargetINTEL",
132+ "class" : "Constant-Creation",
133+ "opcode" : 6251,
134+ "operands" : [
135+ { "kind" : "IdResultType" },
136+ { "kind" : "IdResult" },
137+ { "kind" : "LiteralInteger", "name" : "Target" },
138+ { "kind" : "LiteralInteger", "quantifier" : "*", "name" : "Features" }
139+ ],
140+ "capabilities" : [ "FunctionVariantsINTEL" ],
141+ "provisional" : true,
142+ "version": "None"
143+ },
144+ {
145+ "opname" : "OpSpecConstantArchitectureINTEL",
146+ "class" : "Constant-Creation",
147+ "opcode" : 6252,
148+ "operands" : [
149+ { "kind" : "IdResultType" },
150+ { "kind" : "IdResult" },
151+ { "kind" : "LiteralInteger", "name" : "Category" },
152+ { "kind" : "LiteralInteger", "name" : "Family" },
153+ { "kind" : "LiteralInteger", "name" : "Opcode" },
154+ { "kind" : "LiteralInteger", "name" : "Architecture" }
155+ ],
156+ "capabilities" : [ "FunctionVariantsINTEL" ],
157+ "provisional" : true,
158+ "version": "None"
159+ },
160+ {
161+ "opname" : "OpSpecConstantCapabilitiesINTEL",
162+ "class" : "Constant-Creation",
163+ "opcode" : 6253,
164+ "operands" : [
165+ { "kind" : "IdResultType" },
166+ { "kind" : "IdResult" },
167+ { "kind" : "Capability", "quantifier" : "*", "name" : "Capabilities" }
168+ ],
169+ "capabilities" : [ "FunctionVariantsINTEL" ],
170+ "provisional" : true,
171+ "version": "None"
172+ },
173+ {
174+ "opname" : "OpConditionalCopyObjectINTEL",
175+ "class" : "Composite",
176+ "opcode" : 6254,
177+ "operands" : [
178+ { "kind" : "IdResultType" },
179+ { "kind" : "IdResult" },
180+ { "kind" : "IdRef", "quantifier" : "*", "name" : "Condition 0, Operand 0, +\nCondition 1, Operand 1, +\n..." }
181+ ],
182+ "capabilities" : [ "SpecConditionalINTEL" ],
183+ "provisional" : true,
184+ "version" : "None"
185+ },
186 {
187 "opname" : "OpGroupIMulKHR",
188 "class" : "Group",
189@@ -14900,6 +14995,16 @@
190 "capabilities" : [ "GlobalVariableFPGADecorationsINTEL" ],
191 "version" : "None"
192 },
193+ {
194+ "enumerant" : "ConditionalINTEL",
195+ "value" : 6247,
196+ "parameters": [
197+ { "kind" : "IdRef", "name" : "Condition" }
198+ ],
199+ "capabilities" : [ "SpecConditionalINTEL" ],
200+ "provisional" : true,
201+ "version" : "None"
202+ },
203 {
204 "enumerant" : "CacheControlLoadINTEL",
205 "value" : 6442,
206@@ -17563,6 +17668,21 @@
207 "extensions" : [ "SPV_INTEL_ternary_bitwise_function"],
208 "version" : "None"
209 },
210+ {
211+ "enumerant" : "SpecConditionalINTEL",
212+ "value" : 6245,
213+ "extensions" : [ "SPV_INTEL_function_variants" ],
214+ "provisional" : true,
215+ "version": "None"
216+ },
217+ {
218+ "enumerant" : "FunctionVariantsINTEL",
219+ "value" : 6246,
220+ "capabilities" : [ "SpecConditionalINTEL" ],
221+ "extensions" : [ "SPV_INTEL_function_variants" ],
222+ "provisional" : true,
223+ "version": "None"
224+ },
225 {
226 "enumerant" : "GroupUniformArithmeticKHR",
227 "value" : 6400,
228diff --git a/include/spirv/unified1/spirv.cs b/include/spirv/unified1/spirv.cs
229index b11a8b2..57e7216 100644
230--- a/include/spirv/unified1/spirv.cs
231+++ b/include/spirv/unified1/spirv.cs
232@@ -654,6 +654,7 @@ namespace Spv
233 HostAccessINTEL = 6188,
234 InitModeINTEL = 6190,
235 ImplementInRegisterMapINTEL = 6191,
236+ ConditionalINTEL = 6247,
237 CacheControlLoadINTEL = 6442,
238 CacheControlStoreINTEL = 6443,
239 Max = 0x7fffffff,
240@@ -1311,6 +1312,8 @@ namespace Spv
241 Subgroup2DBlockTransposeINTEL = 6230,
242 SubgroupMatrixMultiplyAccumulateINTEL = 6236,
243 TernaryBitwiseFunctionINTEL = 6241,
244+ SpecConditionalINTEL = 6245,
245+ FunctionVariantsINTEL = 6246,
246 GroupUniformArithmeticKHR = 6400,
247 TensorFloat32RoundingINTEL = 6425,
248 MaskedGatherScatterINTEL = 6427,
249@@ -2471,6 +2474,13 @@ namespace Spv
250 OpSubgroup2DBlockStoreINTEL = 6235,
251 OpSubgroupMatrixMultiplyAccumulateINTEL = 6237,
252 OpBitwiseFunctionINTEL = 6242,
253+ OpConditionalExtensionINTEL = 6248,
254+ OpConditionalEntryPointINTEL = 6249,
255+ OpConditionalCapabilityINTEL = 6250,
256+ OpSpecConstantTargetINTEL = 6251,
257+ OpSpecConstantArchitectureINTEL = 6252,
258+ OpSpecConstantCapabilitiesINTEL = 6253,
259+ OpConditionalCopyObjectINTEL = 6254,
260 OpGroupIMulKHR = 6401,
261 OpGroupFMulKHR = 6402,
262 OpGroupBitwiseAndKHR = 6403,
263diff --git a/include/spirv/unified1/spirv.h b/include/spirv/unified1/spirv.h
264index 005d451..84972da 100644
265--- a/include/spirv/unified1/spirv.h
266+++ b/include/spirv/unified1/spirv.h
267@@ -642,6 +642,7 @@ typedef enum SpvDecoration_ {
268 SpvDecorationHostAccessINTEL = 6188,
269 SpvDecorationInitModeINTEL = 6190,
270 SpvDecorationImplementInRegisterMapINTEL = 6191,
271+ SpvDecorationConditionalINTEL = 6247,
272 SpvDecorationCacheControlLoadINTEL = 6442,
273 SpvDecorationCacheControlStoreINTEL = 6443,
274 SpvDecorationMax = 0x7fffffff,
275@@ -1282,6 +1283,8 @@ typedef enum SpvCapability_ {
276 SpvCapabilitySubgroup2DBlockTransposeINTEL = 6230,
277 SpvCapabilitySubgroupMatrixMultiplyAccumulateINTEL = 6236,
278 SpvCapabilityTernaryBitwiseFunctionINTEL = 6241,
279+ SpvCapabilitySpecConditionalINTEL = 6245,
280+ SpvCapabilityFunctionVariantsINTEL = 6246,
281 SpvCapabilityGroupUniformArithmeticKHR = 6400,
282 SpvCapabilityTensorFloat32RoundingINTEL = 6425,
283 SpvCapabilityMaskedGatherScatterINTEL = 6427,
284@@ -2406,6 +2409,13 @@ typedef enum SpvOp_ {
285 SpvOpSubgroup2DBlockStoreINTEL = 6235,
286 SpvOpSubgroupMatrixMultiplyAccumulateINTEL = 6237,
287 SpvOpBitwiseFunctionINTEL = 6242,
288+ SpvOpConditionalExtensionINTEL = 6248,
289+ SpvOpConditionalEntryPointINTEL = 6249,
290+ SpvOpConditionalCapabilityINTEL = 6250,
291+ SpvOpSpecConstantTargetINTEL = 6251,
292+ SpvOpSpecConstantArchitectureINTEL = 6252,
293+ SpvOpSpecConstantCapabilitiesINTEL = 6253,
294+ SpvOpConditionalCopyObjectINTEL = 6254,
295 SpvOpGroupIMulKHR = 6401,
296 SpvOpGroupFMulKHR = 6402,
297 SpvOpGroupBitwiseAndKHR = 6403,
298@@ -3225,6 +3235,13 @@ inline void SpvHasResultAndType(SpvOp opcode, bool *hasResult, bool *hasResultTy
299 case SpvOpSubgroup2DBlockStoreINTEL: *hasResult = false; *hasResultType = false; break;
300 case SpvOpSubgroupMatrixMultiplyAccumulateINTEL: *hasResult = true; *hasResultType = true; break;
301 case SpvOpBitwiseFunctionINTEL: *hasResult = true; *hasResultType = true; break;
302+ case SpvOpConditionalExtensionINTEL: *hasResult = false; *hasResultType = false; break;
303+ case SpvOpConditionalEntryPointINTEL: *hasResult = false; *hasResultType = false; break;
304+ case SpvOpConditionalCapabilityINTEL: *hasResult = false; *hasResultType = false; break;
305+ case SpvOpSpecConstantTargetINTEL: *hasResult = true; *hasResultType = true; break;
306+ case SpvOpSpecConstantArchitectureINTEL: *hasResult = true; *hasResultType = true; break;
307+ case SpvOpSpecConstantCapabilitiesINTEL: *hasResult = true; *hasResultType = true; break;
308+ case SpvOpConditionalCopyObjectINTEL: *hasResult = true; *hasResultType = true; break;
309 case SpvOpGroupIMulKHR: *hasResult = true; *hasResultType = true; break;
310 case SpvOpGroupFMulKHR: *hasResult = true; *hasResultType = true; break;
311 case SpvOpGroupBitwiseAndKHR: *hasResult = true; *hasResultType = true; break;
312@@ -3765,6 +3782,7 @@ inline const char* SpvDecorationToString(SpvDecoration value) {
313 case SpvDecorationHostAccessINTEL: return "HostAccessINTEL";
314 case SpvDecorationInitModeINTEL: return "InitModeINTEL";
315 case SpvDecorationImplementInRegisterMapINTEL: return "ImplementInRegisterMapINTEL";
316+ case SpvDecorationConditionalINTEL: return "ConditionalINTEL";
317 case SpvDecorationCacheControlLoadINTEL: return "CacheControlLoadINTEL";
318 case SpvDecorationCacheControlStoreINTEL: return "CacheControlStoreINTEL";
319 default: return "Unknown";
320@@ -4204,6 +4222,8 @@ inline const char* SpvCapabilityToString(SpvCapability value) {
321 case SpvCapabilitySubgroup2DBlockTransposeINTEL: return "Subgroup2DBlockTransposeINTEL";
322 case SpvCapabilitySubgroupMatrixMultiplyAccumulateINTEL: return "SubgroupMatrixMultiplyAccumulateINTEL";
323 case SpvCapabilityTernaryBitwiseFunctionINTEL: return "TernaryBitwiseFunctionINTEL";
324+ case SpvCapabilitySpecConditionalINTEL: return "SpecConditionalINTEL";
325+ case SpvCapabilityFunctionVariantsINTEL: return "FunctionVariantsINTEL";
326 case SpvCapabilityGroupUniformArithmeticKHR: return "GroupUniformArithmeticKHR";
327 case SpvCapabilityTensorFloat32RoundingINTEL: return "TensorFloat32RoundingINTEL";
328 case SpvCapabilityMaskedGatherScatterINTEL: return "MaskedGatherScatterINTEL";
329@@ -5198,6 +5218,13 @@ inline const char* SpvOpToString(SpvOp value) {
330 case SpvOpSubgroup2DBlockStoreINTEL: return "OpSubgroup2DBlockStoreINTEL";
331 case SpvOpSubgroupMatrixMultiplyAccumulateINTEL: return "OpSubgroupMatrixMultiplyAccumulateINTEL";
332 case SpvOpBitwiseFunctionINTEL: return "OpBitwiseFunctionINTEL";
333+ case SpvOpConditionalExtensionINTEL: return "OpConditionalExtensionINTEL";
334+ case SpvOpConditionalEntryPointINTEL: return "OpConditionalEntryPointINTEL";
335+ case SpvOpConditionalCapabilityINTEL: return "OpConditionalCapabilityINTEL";
336+ case SpvOpSpecConstantTargetINTEL: return "OpSpecConstantTargetINTEL";
337+ case SpvOpSpecConstantArchitectureINTEL: return "OpSpecConstantArchitectureINTEL";
338+ case SpvOpSpecConstantCapabilitiesINTEL: return "OpSpecConstantCapabilitiesINTEL";
339+ case SpvOpConditionalCopyObjectINTEL: return "OpConditionalCopyObjectINTEL";
340 case SpvOpGroupIMulKHR: return "OpGroupIMulKHR";
341 case SpvOpGroupFMulKHR: return "OpGroupFMulKHR";
342 case SpvOpGroupBitwiseAndKHR: return "OpGroupBitwiseAndKHR";
343diff --git a/include/spirv/unified1/spirv.hpp b/include/spirv/unified1/spirv.hpp
344index f7a7bf8..a3d760a 100644
345--- a/include/spirv/unified1/spirv.hpp
346+++ b/include/spirv/unified1/spirv.hpp
347@@ -638,6 +638,7 @@ enum Decoration {
348 DecorationHostAccessINTEL = 6188,
349 DecorationInitModeINTEL = 6190,
350 DecorationImplementInRegisterMapINTEL = 6191,
351+ DecorationConditionalINTEL = 6247,
352 DecorationCacheControlLoadINTEL = 6442,
353 DecorationCacheControlStoreINTEL = 6443,
354 DecorationMax = 0x7fffffff,
355@@ -1278,6 +1279,8 @@ enum Capability {
356 CapabilitySubgroup2DBlockTransposeINTEL = 6230,
357 CapabilitySubgroupMatrixMultiplyAccumulateINTEL = 6236,
358 CapabilityTernaryBitwiseFunctionINTEL = 6241,
359+ CapabilitySpecConditionalINTEL = 6245,
360+ CapabilityFunctionVariantsINTEL = 6246,
361 CapabilityGroupUniformArithmeticKHR = 6400,
362 CapabilityTensorFloat32RoundingINTEL = 6425,
363 CapabilityMaskedGatherScatterINTEL = 6427,
364@@ -2402,6 +2405,13 @@ enum Op {
365 OpSubgroup2DBlockStoreINTEL = 6235,
366 OpSubgroupMatrixMultiplyAccumulateINTEL = 6237,
367 OpBitwiseFunctionINTEL = 6242,
368+ OpConditionalExtensionINTEL = 6248,
369+ OpConditionalEntryPointINTEL = 6249,
370+ OpConditionalCapabilityINTEL = 6250,
371+ OpSpecConstantTargetINTEL = 6251,
372+ OpSpecConstantArchitectureINTEL = 6252,
373+ OpSpecConstantCapabilitiesINTEL = 6253,
374+ OpConditionalCopyObjectINTEL = 6254,
375 OpGroupIMulKHR = 6401,
376 OpGroupFMulKHR = 6402,
377 OpGroupBitwiseAndKHR = 6403,
378@@ -3221,6 +3231,13 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) {
379 case OpSubgroup2DBlockStoreINTEL: *hasResult = false; *hasResultType = false; break;
380 case OpSubgroupMatrixMultiplyAccumulateINTEL: *hasResult = true; *hasResultType = true; break;
381 case OpBitwiseFunctionINTEL: *hasResult = true; *hasResultType = true; break;
382+ case OpConditionalExtensionINTEL: *hasResult = false; *hasResultType = false; break;
383+ case OpConditionalEntryPointINTEL: *hasResult = false; *hasResultType = false; break;
384+ case OpConditionalCapabilityINTEL: *hasResult = false; *hasResultType = false; break;
385+ case OpSpecConstantTargetINTEL: *hasResult = true; *hasResultType = true; break;
386+ case OpSpecConstantArchitectureINTEL: *hasResult = true; *hasResultType = true; break;
387+ case OpSpecConstantCapabilitiesINTEL: *hasResult = true; *hasResultType = true; break;
388+ case OpConditionalCopyObjectINTEL: *hasResult = true; *hasResultType = true; break;
389 case OpGroupIMulKHR: *hasResult = true; *hasResultType = true; break;
390 case OpGroupFMulKHR: *hasResult = true; *hasResultType = true; break;
391 case OpGroupBitwiseAndKHR: *hasResult = true; *hasResultType = true; break;
392@@ -3761,6 +3778,7 @@ inline const char* DecorationToString(Decoration value) {
393 case DecorationHostAccessINTEL: return "HostAccessINTEL";
394 case DecorationInitModeINTEL: return "InitModeINTEL";
395 case DecorationImplementInRegisterMapINTEL: return "ImplementInRegisterMapINTEL";
396+ case DecorationConditionalINTEL: return "ConditionalINTEL";
397 case DecorationCacheControlLoadINTEL: return "CacheControlLoadINTEL";
398 case DecorationCacheControlStoreINTEL: return "CacheControlStoreINTEL";
399 default: return "Unknown";
400@@ -4200,6 +4218,8 @@ inline const char* CapabilityToString(Capability value) {
401 case CapabilitySubgroup2DBlockTransposeINTEL: return "Subgroup2DBlockTransposeINTEL";
402 case CapabilitySubgroupMatrixMultiplyAccumulateINTEL: return "SubgroupMatrixMultiplyAccumulateINTEL";
403 case CapabilityTernaryBitwiseFunctionINTEL: return "TernaryBitwiseFunctionINTEL";
404+ case CapabilitySpecConditionalINTEL: return "SpecConditionalINTEL";
405+ case CapabilityFunctionVariantsINTEL: return "FunctionVariantsINTEL";
406 case CapabilityGroupUniformArithmeticKHR: return "GroupUniformArithmeticKHR";
407 case CapabilityTensorFloat32RoundingINTEL: return "TensorFloat32RoundingINTEL";
408 case CapabilityMaskedGatherScatterINTEL: return "MaskedGatherScatterINTEL";
409@@ -5194,6 +5214,13 @@ inline const char* OpToString(Op value) {
410 case OpSubgroup2DBlockStoreINTEL: return "OpSubgroup2DBlockStoreINTEL";
411 case OpSubgroupMatrixMultiplyAccumulateINTEL: return "OpSubgroupMatrixMultiplyAccumulateINTEL";
412 case OpBitwiseFunctionINTEL: return "OpBitwiseFunctionINTEL";
413+ case OpConditionalExtensionINTEL: return "OpConditionalExtensionINTEL";
414+ case OpConditionalEntryPointINTEL: return "OpConditionalEntryPointINTEL";
415+ case OpConditionalCapabilityINTEL: return "OpConditionalCapabilityINTEL";
416+ case OpSpecConstantTargetINTEL: return "OpSpecConstantTargetINTEL";
417+ case OpSpecConstantArchitectureINTEL: return "OpSpecConstantArchitectureINTEL";
418+ case OpSpecConstantCapabilitiesINTEL: return "OpSpecConstantCapabilitiesINTEL";
419+ case OpConditionalCopyObjectINTEL: return "OpConditionalCopyObjectINTEL";
420 case OpGroupIMulKHR: return "OpGroupIMulKHR";
421 case OpGroupFMulKHR: return "OpGroupFMulKHR";
422 case OpGroupBitwiseAndKHR: return "OpGroupBitwiseAndKHR";
423diff --git a/include/spirv/unified1/spirv.hpp11 b/include/spirv/unified1/spirv.hpp11
424index b83ca46..e8479cb 100644
425--- a/include/spirv/unified1/spirv.hpp11
426+++ b/include/spirv/unified1/spirv.hpp11
427@@ -638,6 +638,7 @@ enum class Decoration : unsigned {
428 HostAccessINTEL = 6188,
429 InitModeINTEL = 6190,
430 ImplementInRegisterMapINTEL = 6191,
431+ ConditionalINTEL = 6247,
432 CacheControlLoadINTEL = 6442,
433 CacheControlStoreINTEL = 6443,
434 Max = 0x7fffffff,
435@@ -1278,6 +1279,8 @@ enum class Capability : unsigned {
436 Subgroup2DBlockTransposeINTEL = 6230,
437 SubgroupMatrixMultiplyAccumulateINTEL = 6236,
438 TernaryBitwiseFunctionINTEL = 6241,
439+ SpecConditionalINTEL = 6245,
440+ FunctionVariantsINTEL = 6246,
441 GroupUniformArithmeticKHR = 6400,
442 TensorFloat32RoundingINTEL = 6425,
443 MaskedGatherScatterINTEL = 6427,
444@@ -2402,6 +2405,13 @@ enum class Op : unsigned {
445 OpSubgroup2DBlockStoreINTEL = 6235,
446 OpSubgroupMatrixMultiplyAccumulateINTEL = 6237,
447 OpBitwiseFunctionINTEL = 6242,
448+ OpConditionalExtensionINTEL = 6248,
449+ OpConditionalEntryPointINTEL = 6249,
450+ OpConditionalCapabilityINTEL = 6250,
451+ OpSpecConstantTargetINTEL = 6251,
452+ OpSpecConstantArchitectureINTEL = 6252,
453+ OpSpecConstantCapabilitiesINTEL = 6253,
454+ OpConditionalCopyObjectINTEL = 6254,
455 OpGroupIMulKHR = 6401,
456 OpGroupFMulKHR = 6402,
457 OpGroupBitwiseAndKHR = 6403,
458@@ -3221,6 +3231,13 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) {
459 case Op::OpSubgroup2DBlockStoreINTEL: *hasResult = false; *hasResultType = false; break;
460 case Op::OpSubgroupMatrixMultiplyAccumulateINTEL: *hasResult = true; *hasResultType = true; break;
461 case Op::OpBitwiseFunctionINTEL: *hasResult = true; *hasResultType = true; break;
462+ case Op::OpConditionalExtensionINTEL: *hasResult = false; *hasResultType = false; break;
463+ case Op::OpConditionalEntryPointINTEL: *hasResult = false; *hasResultType = false; break;
464+ case Op::OpConditionalCapabilityINTEL: *hasResult = false; *hasResultType = false; break;
465+ case Op::OpSpecConstantTargetINTEL: *hasResult = true; *hasResultType = true; break;
466+ case Op::OpSpecConstantArchitectureINTEL: *hasResult = true; *hasResultType = true; break;
467+ case Op::OpSpecConstantCapabilitiesINTEL: *hasResult = true; *hasResultType = true; break;
468+ case Op::OpConditionalCopyObjectINTEL: *hasResult = true; *hasResultType = true; break;
469 case Op::OpGroupIMulKHR: *hasResult = true; *hasResultType = true; break;
470 case Op::OpGroupFMulKHR: *hasResult = true; *hasResultType = true; break;
471 case Op::OpGroupBitwiseAndKHR: *hasResult = true; *hasResultType = true; break;
472@@ -3761,6 +3778,7 @@ inline const char* DecorationToString(Decoration value) {
473 case Decoration::HostAccessINTEL: return "HostAccessINTEL";
474 case Decoration::InitModeINTEL: return "InitModeINTEL";
475 case Decoration::ImplementInRegisterMapINTEL: return "ImplementInRegisterMapINTEL";
476+ case Decoration::ConditionalINTEL: return "ConditionalINTEL";
477 case Decoration::CacheControlLoadINTEL: return "CacheControlLoadINTEL";
478 case Decoration::CacheControlStoreINTEL: return "CacheControlStoreINTEL";
479 default: return "Unknown";
480@@ -4200,6 +4218,8 @@ inline const char* CapabilityToString(Capability value) {
481 case Capability::Subgroup2DBlockTransposeINTEL: return "Subgroup2DBlockTransposeINTEL";
482 case Capability::SubgroupMatrixMultiplyAccumulateINTEL: return "SubgroupMatrixMultiplyAccumulateINTEL";
483 case Capability::TernaryBitwiseFunctionINTEL: return "TernaryBitwiseFunctionINTEL";
484+ case Capability::SpecConditionalINTEL: return "SpecConditionalINTEL";
485+ case Capability::FunctionVariantsINTEL: return "FunctionVariantsINTEL";
486 case Capability::GroupUniformArithmeticKHR: return "GroupUniformArithmeticKHR";
487 case Capability::TensorFloat32RoundingINTEL: return "TensorFloat32RoundingINTEL";
488 case Capability::MaskedGatherScatterINTEL: return "MaskedGatherScatterINTEL";
489@@ -5194,6 +5214,13 @@ inline const char* OpToString(Op value) {
490 case Op::OpSubgroup2DBlockStoreINTEL: return "OpSubgroup2DBlockStoreINTEL";
491 case Op::OpSubgroupMatrixMultiplyAccumulateINTEL: return "OpSubgroupMatrixMultiplyAccumulateINTEL";
492 case Op::OpBitwiseFunctionINTEL: return "OpBitwiseFunctionINTEL";
493+ case Op::OpConditionalExtensionINTEL: return "OpConditionalExtensionINTEL";
494+ case Op::OpConditionalEntryPointINTEL: return "OpConditionalEntryPointINTEL";
495+ case Op::OpConditionalCapabilityINTEL: return "OpConditionalCapabilityINTEL";
496+ case Op::OpSpecConstantTargetINTEL: return "OpSpecConstantTargetINTEL";
497+ case Op::OpSpecConstantArchitectureINTEL: return "OpSpecConstantArchitectureINTEL";
498+ case Op::OpSpecConstantCapabilitiesINTEL: return "OpSpecConstantCapabilitiesINTEL";
499+ case Op::OpConditionalCopyObjectINTEL: return "OpConditionalCopyObjectINTEL";
500 case Op::OpGroupIMulKHR: return "OpGroupIMulKHR";
501 case Op::OpGroupFMulKHR: return "OpGroupFMulKHR";
502 case Op::OpGroupBitwiseAndKHR: return "OpGroupBitwiseAndKHR";
503diff --git a/include/spirv/unified1/spirv.json b/include/spirv/unified1/spirv.json
504index 0668c98..e0c0230 100644
505--- a/include/spirv/unified1/spirv.json
506+++ b/include/spirv/unified1/spirv.json
507@@ -661,6 +661,7 @@
508 "HostAccessINTEL": 6188,
509 "InitModeINTEL": 6190,
510 "ImplementInRegisterMapINTEL": 6191,
511+ "ConditionalINTEL": 6247,
512 "CacheControlLoadINTEL": 6442,
513 "CacheControlStoreINTEL": 6443
514 }
515@@ -1254,6 +1255,8 @@
516 "Subgroup2DBlockTransposeINTEL": 6230,
517 "SubgroupMatrixMultiplyAccumulateINTEL": 6236,
518 "TernaryBitwiseFunctionINTEL": 6241,
519+ "SpecConditionalINTEL": 6245,
520+ "FunctionVariantsINTEL": 6246,
521 "GroupUniformArithmeticKHR": 6400,
522 "TensorFloat32RoundingINTEL": 6425,
523 "MaskedGatherScatterINTEL": 6427,
524@@ -2383,6 +2386,13 @@
525 "OpSubgroup2DBlockStoreINTEL": 6235,
526 "OpSubgroupMatrixMultiplyAccumulateINTEL": 6237,
527 "OpBitwiseFunctionINTEL": 6242,
528+ "OpConditionalExtensionINTEL": 6248,
529+ "OpConditionalEntryPointINTEL": 6249,
530+ "OpConditionalCapabilityINTEL": 6250,
531+ "OpSpecConstantTargetINTEL": 6251,
532+ "OpSpecConstantArchitectureINTEL": 6252,
533+ "OpSpecConstantCapabilitiesINTEL": 6253,
534+ "OpConditionalCopyObjectINTEL": 6254,
535 "OpGroupIMulKHR": 6401,
536 "OpGroupFMulKHR": 6402,
537 "OpGroupBitwiseAndKHR": 6403,
538diff --git a/include/spirv/unified1/spirv.lua b/include/spirv/unified1/spirv.lua
539index a612e5c..410060b 100644
540--- a/include/spirv/unified1/spirv.lua
541+++ b/include/spirv/unified1/spirv.lua
542@@ -629,6 +629,7 @@ spv = {
543 HostAccessINTEL = 6188,
544 InitModeINTEL = 6190,
545 ImplementInRegisterMapINTEL = 6191,
546+ ConditionalINTEL = 6247,
547 CacheControlLoadINTEL = 6442,
548 CacheControlStoreINTEL = 6443,
549 Max = 0x7fffffff,
550@@ -1269,6 +1270,8 @@ spv = {
551 Subgroup2DBlockTransposeINTEL = 6230,
552 SubgroupMatrixMultiplyAccumulateINTEL = 6236,
553 TernaryBitwiseFunctionINTEL = 6241,
554+ SpecConditionalINTEL = 6245,
555+ FunctionVariantsINTEL = 6246,
556 GroupUniformArithmeticKHR = 6400,
557 TensorFloat32RoundingINTEL = 6425,
558 MaskedGatherScatterINTEL = 6427,
559@@ -2393,6 +2396,13 @@ spv = {
560 OpSubgroup2DBlockStoreINTEL = 6235,
561 OpSubgroupMatrixMultiplyAccumulateINTEL = 6237,
562 OpBitwiseFunctionINTEL = 6242,
563+ OpConditionalExtensionINTEL = 6248,
564+ OpConditionalEntryPointINTEL = 6249,
565+ OpConditionalCapabilityINTEL = 6250,
566+ OpSpecConstantTargetINTEL = 6251,
567+ OpSpecConstantArchitectureINTEL = 6252,
568+ OpSpecConstantCapabilitiesINTEL = 6253,
569+ OpConditionalCopyObjectINTEL = 6254,
570 OpGroupIMulKHR = 6401,
571 OpGroupFMulKHR = 6402,
572 OpGroupBitwiseAndKHR = 6403,
573diff --git a/include/spirv/unified1/spirv.py b/include/spirv/unified1/spirv.py
574index 5adfded..0b77b4f 100644
575--- a/include/spirv/unified1/spirv.py
576+++ b/include/spirv/unified1/spirv.py
577@@ -611,6 +611,7 @@ spv = {
578 'HostAccessINTEL' : 6188,
579 'InitModeINTEL' : 6190,
580 'ImplementInRegisterMapINTEL' : 6191,
581+ 'ConditionalINTEL' : 6247,
582 'CacheControlLoadINTEL' : 6442,
583 'CacheControlStoreINTEL' : 6443,
584 },
585@@ -1240,6 +1241,8 @@ spv = {
586 'Subgroup2DBlockTransposeINTEL' : 6230,
587 'SubgroupMatrixMultiplyAccumulateINTEL' : 6236,
588 'TernaryBitwiseFunctionINTEL' : 6241,
589+ 'SpecConditionalINTEL' : 6245,
590+ 'FunctionVariantsINTEL' : 6246,
591 'GroupUniformArithmeticKHR' : 6400,
592 'TensorFloat32RoundingINTEL' : 6425,
593 'MaskedGatherScatterINTEL' : 6427,
594@@ -2336,6 +2339,13 @@ spv = {
595 'OpSubgroup2DBlockStoreINTEL' : 6235,
596 'OpSubgroupMatrixMultiplyAccumulateINTEL' : 6237,
597 'OpBitwiseFunctionINTEL' : 6242,
598+ 'OpConditionalExtensionINTEL' : 6248,
599+ 'OpConditionalEntryPointINTEL' : 6249,
600+ 'OpConditionalCapabilityINTEL' : 6250,
601+ 'OpSpecConstantTargetINTEL' : 6251,
602+ 'OpSpecConstantArchitectureINTEL' : 6252,
603+ 'OpSpecConstantCapabilitiesINTEL' : 6253,
604+ 'OpConditionalCopyObjectINTEL' : 6254,
605 'OpGroupIMulKHR' : 6401,
606 'OpGroupFMulKHR' : 6402,
607 'OpGroupBitwiseAndKHR' : 6403,
608diff --git a/include/spirv/unified1/spv.d b/include/spirv/unified1/spv.d
609index 3c5130a..a5763e6 100644
610--- a/include/spirv/unified1/spv.d
611+++ b/include/spirv/unified1/spv.d
612@@ -657,6 +657,7 @@ enum Decoration : uint
613 HostAccessINTEL = 6188,
614 InitModeINTEL = 6190,
615 ImplementInRegisterMapINTEL = 6191,
616+ ConditionalINTEL = 6247,
617 CacheControlLoadINTEL = 6442,
618 CacheControlStoreINTEL = 6443,
619 Max = 0x7fffffff,
620@@ -1314,6 +1315,8 @@ enum Capability : uint
621 Subgroup2DBlockTransposeINTEL = 6230,
622 SubgroupMatrixMultiplyAccumulateINTEL = 6236,
623 TernaryBitwiseFunctionINTEL = 6241,
624+ SpecConditionalINTEL = 6245,
625+ FunctionVariantsINTEL = 6246,
626 GroupUniformArithmeticKHR = 6400,
627 TensorFloat32RoundingINTEL = 6425,
628 MaskedGatherScatterINTEL = 6427,
629@@ -2474,6 +2477,13 @@ enum Op : uint
630 OpSubgroup2DBlockStoreINTEL = 6235,
631 OpSubgroupMatrixMultiplyAccumulateINTEL = 6237,
632 OpBitwiseFunctionINTEL = 6242,
633+ OpConditionalExtensionINTEL = 6248,
634+ OpConditionalEntryPointINTEL = 6249,
635+ OpConditionalCapabilityINTEL = 6250,
636+ OpSpecConstantTargetINTEL = 6251,
637+ OpSpecConstantArchitectureINTEL = 6252,
638+ OpSpecConstantCapabilitiesINTEL = 6253,
639+ OpConditionalCopyObjectINTEL = 6254,
640 OpGroupIMulKHR = 6401,
641 OpGroupFMulKHR = 6402,
642 OpGroupBitwiseAndKHR = 6403,
diff --git a/meta/recipes-graphics/spir/spirv-headers_1.4.321.0.bb b/meta/recipes-graphics/spir/spirv-headers_1.4.321.0.bb
index 5365d64a99..807e34abcc 100644
--- a/meta/recipes-graphics/spir/spirv-headers_1.4.321.0.bb
+++ b/meta/recipes-graphics/spir/spirv-headers_1.4.321.0.bb
@@ -5,7 +5,9 @@ LICENSE = "MIT & CC-BY-4.0"
5LIC_FILES_CHKSUM = "file://LICENSE;md5=a0dcaa512cc2dee95fe0fd791ee83a18" 5LIC_FILES_CHKSUM = "file://LICENSE;md5=a0dcaa512cc2dee95fe0fd791ee83a18"
6 6
7SRCREV = "2a611a970fdbc41ac2e3e328802aed9985352dca" 7SRCREV = "2a611a970fdbc41ac2e3e328802aed9985352dca"
8SRC_URI = "git://github.com/KhronosGroup/SPIRV-Headers;protocol=https;branch=main" 8SRC_URI = "git://github.com/KhronosGroup/SPIRV-Headers;protocol=https;branch=main \
9 file://0001-Add-SPV_INTEL_function_variants-532.patch \
10 "
9PE = "1" 11PE = "1"
10# These recipes need to be updated in lockstep with each other: 12# These recipes need to be updated in lockstep with each other:
11# glslang, vulkan-headers, vulkan-loader, vulkan-tools, spirv-headers, spirv-tools 13# glslang, vulkan-headers, vulkan-loader, vulkan-tools, spirv-headers, spirv-tools
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2026-01-08 15:21:54 +0000