1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
|
From 7de425548753461fd2768017d3be677ba2b2a583 Mon Sep 17 00:00:00 2001
From: Michael Eager <eager@eagercon.com>
Date: Wed, 21 Nov 2012 17:54:09 +0000
Subject: Add swap byte (swapb) and swap halfword (swaph) opcodes.
binutils/opcodes
* microblaze-opc.h (op_code_struct): Add swapb, swaph Increase MAX_OPCODES.
* microblaze-opcm.h (microblaze_instr): Likewise
binutils/gas/testsuite
* gas/microblaze/allinsn.s: Add swapb, swaph
* gas/microblaze/allinsn.d: Likewise
Upstream-Status: Backport
diff --git a/gas/testsuite/gas/microblaze/allinsn.d b/gas/testsuite/gas/microblaze/allinsn.d
index 4a03340..b454fdb 100644
--- a/gas/testsuite/gas/microblaze/allinsn.d
+++ b/gas/testsuite/gas/microblaze/allinsn.d
@@ -41,3 +41,9 @@ Disassembly of section .text:
30: b0000000 imm 0
34: 31600000 addik r11, r0, 0
38: 940bc802 mts rshr, r11
+
+0000003c <swapb>:
+ 3c: 900001e0 swapb r0, r0
+
+00000040 <swaph>:
+ 40: 900001e2 swaph r0, r0
diff --git a/gas/testsuite/gas/microblaze/allinsn.s b/gas/testsuite/gas/microblaze/allinsn.s
index 437444f..ffe91ca 100644
--- a/gas/testsuite/gas/microblaze/allinsn.s
+++ b/gas/testsuite/gas/microblaze/allinsn.s
@@ -46,4 +46,12 @@ regslr:
regshr:
la r11,r0,r0
mts rshr,r11
+ .text
+ .global swapb
+swapb:
+ swapb r0,r0
+ .text
+ .global swaph
+swaph:
+ swaph r0,r0
diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
index 0447fc5..404985b 100644
--- a/opcodes/microblaze-opc.h
+++ b/opcodes/microblaze-opc.h
@@ -101,7 +101,7 @@
#define DELAY_SLOT 1
#define NO_DELAY_SLOT 0
-#define MAX_OPCODES 287
+#define MAX_OPCODES 289
struct op_code_struct
{
@@ -402,6 +402,8 @@ struct op_code_struct
{"clz", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900000E0, OPCODE_MASK_H34, clz, special_inst },
{"mbar", INST_TYPE_IMM5, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8020004, OPCODE_MASK_HN, mbar, special_inst },
{"sleep", INST_TYPE_NONE, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBA020004, OPCODE_MASK_HN, invalid_inst, special_inst }, /* translates to mbar 16. */
+ {"swapb", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E0, OPCODE_MASK_H4, swapb, arithmetic_inst },
+ {"swaph", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E2, OPCODE_MASK_H4, swaph, arithmetic_inst },
{"", 0, 0, 0, 0, 0, 0, 0, 0},
};
diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
index a2a42d0..124cdec 100644
--- a/opcodes/microblaze-opcm.h
+++ b/opcodes/microblaze-opcm.h
@@ -27,7 +27,7 @@ enum microblaze_instr
{
add, rsub, addc, rsubc, addk, rsubk, addkc, rsubkc, clz, cmp, cmpu,
addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul,
- mulh, mulhu, mulhsu,
+ mulh, mulhu, mulhsu,swapb,swaph,
idiv, idivu, bsll, bsra, bsrl, get, put, nget, nput, cget, cput,
ncget, ncput, muli, bslli, bsrai, bsrli, mului, or, and, xor,
andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
--
1.7.5.4
|
