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Create a new meta-xilinx-core, move core functionality to the core, keeping
board specific files in the bsp layer.
zynqmp-generic changed from require <board> to include, so if meta-xilinx-bsp
is not available it will not fail.
Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
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Update dp-modules SRCREV to 2021.2 release.
Signed-off-by: Rajesh Gugulothu <gugulothu.rajesh@xilinx.com>
Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
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This is the result of automated script (0.9.0) conversion:
oe-core/scripts/contrib/convert-overrides.py .
converting the metadata to use ":" as the override character instead of "_".
Signed-off-by: Sai Hari Chandana Kalluri <chandana.kalluri@xilinx.com>
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Update dp-modules branch to xlnx_rel_2021.2 release branch.
Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@xilinx.com>
Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
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Update dp-modules branch and SRCREV to 2021.2 release.
Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@xilinx.com>
Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
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Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
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Update dp-modules branch to 2021.1 and commit id.
Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@xilinx.com>
Signed-off-by: Sai Hari Chandana Kalluri <chandana.kalluri@xilinx.com>
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Issue: CR-1098191
The kernel-module recipes set PACKAGE_ARCH = "${SOC_FAMILY_ARCH}" which is broken
because kernel modules depend on the kernel which is MACHINE specific. The
assignment claims that you could use a kernel module built for some other board
for any other zynqmp board, which is not true since their kernel versions and
configuration will differ.
Remove the assignment so that the kernel module becomes MACHINE_ARCH again.
This solves issues with kernel modules that refuse to install during the
do_rootfs stage, and various setscene tasks running over and again when
switching between MACHINEs.
Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
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Update dp modules branch from master to rel-v2020.2 and associated
release commit id.
Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@xilinx.com>
Signed-off-by: Sai Hari Chandana Kalluri <chandana.kalluri@xilinx.com>
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This recipe will pull in the Xilinx DP drivers and associated
components, for soft IP, to be built as an out-of-tree modules.
Following out-of-tree modules will be built
dp-rx (v4l2):
The DisplayPortPlay 1.4 Rx Subsystem is a feature-rich soft IP
incorporating all the necessary logic to properly interface with PHY
layers and provide DP decoding functionality. The subsystem is a
hierarchical IP that bundles a collection of DP RX-related IP
sub-cores and outputs them as a single IP. The subsystem outputs
multi-pixel video to AXI4-Stream Protocol interface.
dp-tx (drm):
The DisplayPortPlay 1.4 Tx subsystem is a feature-rich soft IP
incorporating all the necessary logic to properly interface with
xilinx PHY layers and provide DP encoding functionality. The subsystem
is a hierarchical IP that bundles a collection of DP TX-related IP
sub-cores and outputs them as a single IP. The subsystem takes incoming
video and transfers them to an DP stream. The stream is then forwarded
to the video PHY layer.
video-phy (phy):
Xilinx Video Phy implements the physical layer for enabling the
plug-and-play connectivity with dp MAC transmit and receive
subsystems. This driver is also used as the repository for common files
used by dp rx and tx drivers including hdcp1.4 and hdcp2.x software
stack.
Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@xilinx.com>
Signed-off-by: Sai Hari Chandana Kalluri <chandana.kalluri@xilinx.com>
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