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-rw-r--r--recipes-devtools/binutils/files/0009-b66f7d905a679685476fbfbc793541adb8829a6c.patch149
1 files changed, 149 insertions, 0 deletions
diff --git a/recipes-devtools/binutils/files/0009-b66f7d905a679685476fbfbc793541adb8829a6c.patch b/recipes-devtools/binutils/files/0009-b66f7d905a679685476fbfbc793541adb8829a6c.patch
new file mode 100644
index 00000000..28b5672d
--- /dev/null
+++ b/recipes-devtools/binutils/files/0009-b66f7d905a679685476fbfbc793541adb8829a6c.patch
@@ -0,0 +1,149 @@
1From b66f7d905a679685476fbfbc793541adb8829a6c Mon Sep 17 00:00:00 2001
2From: Michael Eager <eager@eagercon.com>
3Date: Wed, 21 Nov 2012 17:34:11 +0000
4Subject: Add stack high register and stack low register for MicroBlaze
5 hardware assisted stack protection, stores stack low / stack high
6 limits for detecting stack overflow / underflow
7
8binutils/opcodes
9 * microblaze-opcm.h: Add REG_SLR_MASK, REG_SHR_MASK, REG_SHR and REG_SLR
10 * microblaze-dis.c (get_field_special): Handle REG_SLR_MASK and REG_SHR_MASK
11binutils/gas
12 * config/tc-microblaze.c (parse_reg): Parse REG_SLR, REG_SHR
13binutils/gas
14 * gas/microblaze/allinsn.s: Test use of SHR, SLR
15 * gas/microblaze/allinsn.d: Likewise
16
17Upstream-Status: Backport
18
19diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
20index b71383b..5a427a0 100644
21--- a/gas/config/tc-microblaze.c
22+++ b/gas/config/tc-microblaze.c
23@@ -531,6 +531,17 @@ parse_reg (char * s, unsigned * reg)
24 }
25 return s;
26 }
27+ /* Stack protection registers. */
28+ else if (strncasecmp (s, "rshr", 4) == 0)
29+ {
30+ *reg = REG_SHR;
31+ return s + 4;
32+ }
33+ else if (strncasecmp (s, "rslr", 4) == 0)
34+ {
35+ *reg = REG_SLR;
36+ return s + 4;
37+ }
38 else
39 {
40 if (TOLOWER (s[0]) == 'r')
41@@ -760,6 +771,7 @@ check_spl_reg (unsigned * reg)
42 || (*reg == REG_PID) || (*reg == REG_ZPR)
43 || (*reg == REG_TLBX) || (*reg == REG_TLBLO)
44 || (*reg == REG_TLBHI) || (*reg == REG_TLBSX)
45+ || (*reg == REG_SHR) || (*reg == REG_SLR)
46 || (*reg >= REG_PVR+MIN_PVR_REGNUM && *reg <= REG_PVR+MAX_PVR_REGNUM))
47 return TRUE;
48
49@@ -1280,6 +1292,10 @@ md_assemble (char * str)
50 immed = opcode->immval_mask | REG_TLBLO_MASK;
51 else if (reg2 == REG_TLBHI)
52 immed = opcode->immval_mask | REG_TLBHI_MASK;
53+ else if (reg2 == REG_SHR)
54+ immed = opcode->immval_mask | REG_SHR_MASK;
55+ else if (reg2 == REG_SLR)
56+ immed = opcode->immval_mask | REG_SLR_MASK;
57 else if (reg2 >= (REG_PVR+MIN_PVR_REGNUM) && reg2 <= (REG_PVR+MAX_PVR_REGNUM))
58 immed = opcode->immval_mask | REG_PVR_MASK | reg2;
59 else
60@@ -1331,6 +1347,10 @@ md_assemble (char * str)
61 immed = opcode->immval_mask | REG_TLBHI_MASK;
62 else if (reg1 == REG_TLBSX)
63 immed = opcode->immval_mask | REG_TLBSX_MASK;
64+ else if (reg1 == REG_SHR)
65+ immed = opcode->immval_mask | REG_SHR_MASK;
66+ else if (reg1 == REG_SLR)
67+ immed = opcode->immval_mask | REG_SLR_MASK;
68 else
69 as_fatal (_("invalid value for special purpose register"));
70 inst |= (reg2 << RA_LOW) & RA_MASK;
71diff --git a/gas/testsuite/gas/microblaze/allinsn.d b/gas/testsuite/gas/microblaze/allinsn.d
72index ec14020..4a03340 100644
73--- a/gas/testsuite/gas/microblaze/allinsn.d
74+++ b/gas/testsuite/gas/microblaze/allinsn.d
75@@ -31,3 +31,13 @@ Disassembly of section .text:
76
77 00000020 <sleep>:
78 20: ba020004 sleep
79+
80+00000024 <regslr>:
81+ 24: b0000000 imm 0
82+ 28: 31600000 addik r11, r0, 0
83+ 2c: 940bc800 mts rslr, r11
84+
85+00000030 <regshr>:
86+ 30: b0000000 imm 0
87+ 34: 31600000 addik r11, r0, 0
88+ 38: 940bc802 mts rshr, r11
89diff --git a/gas/testsuite/gas/microblaze/allinsn.s b/gas/testsuite/gas/microblaze/allinsn.s
90index 582da17..437444f 100644
91--- a/gas/testsuite/gas/microblaze/allinsn.s
92+++ b/gas/testsuite/gas/microblaze/allinsn.s
93@@ -36,4 +36,14 @@ mbar:
94 .global sleep
95 sleep:
96 sleep
97+ .text
98+ .global regslr
99+regslr:
100+ la r11,r0,r0
101+ mts rslr,r11
102+ .text
103+ .global regshr
104+regshr:
105+ la r11,r0,r0
106+ mts rshr,r11
107
108diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c
109index e204e36..7e3a546 100644
110--- a/opcodes/microblaze-dis.c
111+++ b/opcodes/microblaze-dis.c
112@@ -139,6 +139,12 @@ get_field_special (long instr, struct op_code_struct * op)
113 case REG_TLBSX_MASK :
114 strcpy (spr, "tlbsx");
115 break;
116+ case REG_SHR_MASK :
117+ strcpy (spr, "shr");
118+ break;
119+ case REG_SLR_MASK :
120+ strcpy (spr, "slr");
121+ break;
122 default :
123 if (((((instr & IMM_MASK) >> IMM_LOW) ^ op->immval_mask) & 0xE000)
124 == REG_PVR_MASK)
125diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
126index 867263e..a2a42d0 100644
127--- a/opcodes/microblaze-opcm.h
128+++ b/opcodes/microblaze-opcm.h
129@@ -79,6 +79,8 @@ enum microblaze_instr_type
130 #define REG_BTR_MASK 0x800b
131 #define REG_EDR_MASK 0x800d
132 #define REG_PVR_MASK 0xa000
133+#define REG_SLR_MASK 0x8800
134+#define REG_SHR_MASK 0x8802
135
136 #define REG_PID_MASK 0x9000
137 #define REG_ZPR_MASK 0x9001
138@@ -100,6 +102,8 @@ enum microblaze_instr_type
139 #define REG_FSR 39 /* FPU Status reg. */
140 #define REG_BTR 43 /* Branch Target reg. */
141 #define REG_EDR 45 /* Exception reg. */
142+#define REG_SHR 50 /* Stack High reg. */
143+#define REG_SLR 51 /* Stack Low reg. */
144 #define REG_PVR 40960 /* Program Verification reg. */
145
146 #define REG_PID 36864 /* MMU: Process ID reg. */
147--
1481.7.5.4
149
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2026-04-23 00:54:45 +0000