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-rw-r--r--meta-microblaze/recipes-devtools/gcc/gcc-13/0029-re-arrangement-of-the-compare-branches.patch268
1 files changed, 268 insertions, 0 deletions
diff --git a/meta-microblaze/recipes-devtools/gcc/gcc-13/0029-re-arrangement-of-the-compare-branches.patch b/meta-microblaze/recipes-devtools/gcc/gcc-13/0029-re-arrangement-of-the-compare-branches.patch
new file mode 100644
index 00000000..448e850f
--- /dev/null
+++ b/meta-microblaze/recipes-devtools/gcc/gcc-13/0029-re-arrangement-of-the-compare-branches.patch
@@ -0,0 +1,268 @@
1From 870bfd716fcddeb72660f3176fb2a68aaa5ecc0e Mon Sep 17 00:00:00 2001
2From: Mahesh Bodapati <mbodapat@xilinx.com>
3Date: Tue, 13 Sep 2022 14:45:15 +0530
4Subject: [PATCH 29/54] re-arrangement of the compare branches
5
6---
7 gcc/config/microblaze/microblaze.cc | 28 ++----
8 gcc/config/microblaze/microblaze.md | 141 +++++++++++++---------------
9 2 files changed, 73 insertions(+), 96 deletions(-)
10
11diff --git a/gcc/config/microblaze/microblaze.cc b/gcc/config/microblaze/microblaze.cc
12index 46bbf8a21e7..de3c95a005e 100644
13--- a/gcc/config/microblaze/microblaze.cc
14+++ b/gcc/config/microblaze/microblaze.cc
15@@ -3707,11 +3707,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
16 {
17 comp_reg = cmp_op0;
18 condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx);
19- if (mode == Pmode)
20- emit_jump_insn (gen_condjump (condition, label1));
21- else
22- emit_jump_insn (gen_long_condjump (condition, label1));
23-
24+ emit_jump_insn (gen_condjump (condition, label1));
25 }
26
27 else if (code == EQ || code == NE)
28@@ -3722,10 +3718,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
29 else
30 emit_insn (gen_xordi3 (comp_reg, cmp_op0, cmp_op1));
31 condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx);
32- if (mode == SImode)
33- emit_jump_insn (gen_condjump (condition, label1));
34- else
35- emit_jump_insn (gen_long_condjump (condition, label1));
36+ emit_jump_insn (gen_condjump (condition, label1));
37 }
38 else
39 {
40@@ -3758,10 +3751,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
41 comp_reg = cmp_op0;
42 condition = gen_rtx_fmt_ee (signed_condition (code),
43 mode, comp_reg, const0_rtx);
44- if (mode == SImode)
45- emit_jump_insn (gen_condjump (condition, label1));
46- else
47- emit_jump_insn (gen_long_condjump (condition, label1));
48+ emit_jump_insn (gen_condjump (condition, label1));
49 }
50 else if (code == EQ)
51 {
52@@ -3776,10 +3766,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
53 cmp_op1));
54 }
55 condition = gen_rtx_EQ (mode, comp_reg, const0_rtx);
56- if (mode == SImode)
57- emit_jump_insn (gen_condjump (condition, label1));
58- else
59- emit_jump_insn (gen_long_condjump (condition, label1));
60+ emit_jump_insn (gen_condjump (condition, label1));
61
62 }
63 else if (code == NE)
64@@ -3795,10 +3782,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
65 cmp_op1));
66 }
67 condition = gen_rtx_NE (mode, comp_reg, const0_rtx);
68- if (mode == SImode)
69- emit_jump_insn (gen_condjump (condition, label1));
70- else
71- emit_jump_insn (gen_long_condjump (condition, label1));
72+ emit_jump_insn (gen_condjump (condition, label1));
73 }
74 else
75 {
76@@ -3840,7 +3824,7 @@ microblaze_expand_conditional_branch_df (rtx operands[])
77
78 emit_insn (gen_cstoredf4 (comp_reg, operands[0], cmp_op0, cmp_op1));
79 condition = gen_rtx_NE (Pmode, comp_reg, const0_rtx);
80- emit_jump_insn (gen_long_condjump (condition, operands[3]));
81+ emit_jump_insn (gen_condjump (condition, operands[3]));
82 }
83
84 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
85diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
86index 97da9aad6fd..31bf04e4abd 100644
87--- a/gcc/config/microblaze/microblaze.md
88+++ b/gcc/config/microblaze/microblaze.md
89@@ -2268,7 +2268,27 @@ else
90 (label_ref (match_operand 1))
91 (pc)))])
92
93-(define_insn "branch_zero64"
94+(define_insn "branch_zero_64"
95+ [(set (pc)
96+ (if_then_else (match_operator:SI 0 "ordered_comparison_operator"
97+ [(match_operand:SI 1 "register_operand" "d")
98+ (const_int 0)])
99+ (match_operand:SI 2 "pc_or_label_operand" "")
100+ (match_operand:SI 3 "pc_or_label_operand" "")))
101+ ]
102+ "TARGET_MB_64"
103+ {
104+ if (operands[3] == pc_rtx)
105+ return "bea%C0i%?\t%z1,%2";
106+ else
107+ return "bea%N0i%?\t%z1,%3";
108+ }
109+ [(set_attr "type" "branch")
110+ (set_attr "mode" "none")
111+ (set_attr "length" "4")]
112+)
113+
114+(define_insn "long_branch_zero"
115 [(set (pc)
116 (if_then_else (match_operator 0 "ordered_comparison_operator"
117 [(match_operand 1 "register_operand" "d")
118@@ -2279,9 +2299,9 @@ else
119 "TARGET_MB_64"
120 {
121 if (operands[3] == pc_rtx)
122- return "bea%C0i%?\t%z1,%2";
123+ return "beal%C0i%?\t%z1,%2";
124 else
125- return "bea%N0i%?\t%z1,%3";
126+ return "beal%N0i%?\t%z1,%3";
127 }
128 [(set_attr "type" "branch")
129 (set_attr "mode" "none")
130@@ -2310,9 +2330,9 @@ else
131
132 (define_insn "branch_compare64"
133 [(set (pc)
134- (if_then_else (match_operator 0 "cmp_op"
135- [(match_operand 1 "register_operand" "d")
136- (match_operand 2 "register_operand" "d")
137+ (if_then_else (match_operator:SI 0 "cmp_op"
138+ [(match_operand:SI 1 "register_operand" "d")
139+ (match_operand:SI 2 "register_operand" "d")
140 ])
141 (label_ref (match_operand 3))
142 (pc)))
143@@ -2349,6 +2369,47 @@ else
144 (set_attr "length" "12")]
145 )
146
147+(define_insn "long_branch_compare"
148+ [(set (pc)
149+ (if_then_else (match_operator 0 "cmp_op"
150+ [(match_operand 1 "register_operand" "d")
151+ (match_operand 2 "register_operand" "d")
152+ ])
153+ (label_ref (match_operand 3))
154+ (pc)))
155+ (clobber(reg:DI R_TMP))]
156+ "TARGET_MB_64"
157+ {
158+ operands[4] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
159+ enum rtx_code code = GET_CODE (operands[0]);
160+
161+ if (code == GT || code == LE)
162+ {
163+ output_asm_insn ("cmpl\tr18,%z1,%z2", operands);
164+ code = swap_condition (code);
165+ }
166+ else if (code == GTU || code == LEU)
167+ {
168+ output_asm_insn ("cmplu\tr18,%z1,%z2", operands);
169+ code = swap_condition (code);
170+ }
171+ else if (code == GE || code == LT)
172+ {
173+ output_asm_insn ("cmpl\tr18,%z2,%z1", operands);
174+ }
175+ else if (code == GEU || code == LTU)
176+ {
177+ output_asm_insn ("cmplu\tr18,%z2,%z1", operands);
178+ }
179+
180+ operands[0] = gen_rtx_fmt_ee (signed_condition (code), DImode, operands[4], const0_rtx);
181+ return "beal%C0i%?\tr18,%3";
182+ }
183+ [(set_attr "type" "branch")
184+ (set_attr "mode" "none")
185+ (set_attr "length" "12")]
186+)
187+
188 (define_insn "branch_compare"
189 [(set (pc)
190 (if_then_else (match_operator:SI 0 "cmp_op"
191@@ -2431,74 +2492,6 @@ else
192
193 })
194
195-;; Used to implement comparison instructions
196-(define_expand "long_condjump"
197- [(set (pc)
198- (if_then_else (match_operand 0)
199- (label_ref (match_operand 1))
200- (pc)))])
201-
202-(define_insn "long_branch_zero"
203- [(set (pc)
204- (if_then_else (match_operator:DI 0 "ordered_comparison_operator"
205- [(match_operand:DI 1 "register_operand" "d")
206- (const_int 0)])
207- (match_operand:DI 2 "pc_or_label_operand" "")
208- (match_operand:DI 3 "pc_or_label_operand" "")))
209- ]
210- "TARGET_MB_64"
211- {
212- if (operands[3] == pc_rtx)
213- return "beal%C0i%?\t%z1,%2";
214- else
215- return "beal%N0i%?\t%z1,%3";
216- }
217- [(set_attr "type" "branch")
218- (set_attr "mode" "none")
219- (set_attr "length" "4")]
220-)
221-
222-(define_insn "long_branch_compare"
223- [(set (pc)
224- (if_then_else (match_operator:DI 0 "cmp_op"
225- [(match_operand:DI 1 "register_operand" "d")
226- (match_operand:DI 2 "register_operand" "d")
227- ])
228- (label_ref (match_operand 3))
229- (pc)))
230- (clobber(reg:DI R_TMP))]
231- "TARGET_MB_64"
232- {
233- operands[4] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
234- enum rtx_code code = GET_CODE (operands[0]);
235-
236- if (code == GT || code == LE)
237- {
238- output_asm_insn ("cmpl\tr18,%z1,%z2", operands);
239- code = swap_condition (code);
240- }
241- else if (code == GTU || code == LEU)
242- {
243- output_asm_insn ("cmplu\tr18,%z1,%z2", operands);
244- code = swap_condition (code);
245- }
246- else if (code == GE || code == LT)
247- {
248- output_asm_insn ("cmpl\tr18,%z2,%z1", operands);
249- }
250- else if (code == GEU || code == LTU)
251- {
252- output_asm_insn ("cmplu\tr18,%z2,%z1", operands);
253- }
254-
255- operands[0] = gen_rtx_fmt_ee (signed_condition (code), DImode, operands[4], const0_rtx);
256- return "beal%C0i%?\tr18,%3";
257- }
258- [(set_attr "type" "branch")
259- (set_attr "mode" "none")
260- (set_attr "length" "12")]
261-)
262-
263 ;;----------------------------------------------------------------
264 ;; Unconditional branches
265 ;;----------------------------------------------------------------
266--
2672.34.1
268
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2026-04-24 08:31:28 +0000