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-rw-r--r--meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx/v2018.1/microblaze-kc705-Convert-microblaze-generic-to-k.patch1168
-rw-r--r--meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2018.1.bb2
2 files changed, 1170 insertions, 0 deletions
diff --git a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx/v2018.1/microblaze-kc705-Convert-microblaze-generic-to-k.patch b/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx/v2018.1/microblaze-kc705-Convert-microblaze-generic-to-k.patch
new file mode 100644
index 00000000..ce8771f8
--- /dev/null
+++ b/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx/v2018.1/microblaze-kc705-Convert-microblaze-generic-to-k.patch
@@ -0,0 +1,1168 @@
1From 539838b4fe4afecd9b6874c5ac397ab7f5b343d4 Mon Sep 17 00:00:00 2001
2From: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
3Date: Tue, 10 Apr 2018 18:34:45 -0700
4Subject: [PATCH] kc705-microblazeel: Convert microblaze-generic to
5 kc705-microblazeel
6
7This is an update to earlier kc705-trd patch done by Nathan Rossi.
8Starting from v2016.1, KC705 will no longer refer to deprecated KC705
9TRD application.
10
11Change the microblaze-generic board to match the kc705-microblazeel.
12This patch is not intended for upstream and serves as an intermediate
13solution until OF support in upstream u-boot allows for easy support for
14custom microblaze boards.
15
16Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
17Upstream-Status: Not-Upstreamable [meta-xilinx/kc705 specific]
18---
19 arch/microblaze/dts/microblaze-generic.dts | 590 ++++++++++++++++++++++++++++-
20 board/xilinx/microblaze-generic/config.mk | 30 +-
21 configs/microblaze-generic_defconfig | 57 ++-
22 include/configs/microblaze-generic.h | 396 ++++++++-----------
23 4 files changed, 782 insertions(+), 291 deletions(-)
24
25diff --git a/arch/microblaze/dts/microblaze-generic.dts b/arch/microblaze/dts/microblaze-generic.dts
26index 08a1396..f8e616b 100644
27--- a/arch/microblaze/dts/microblaze-generic.dts
28+++ b/arch/microblaze/dts/microblaze-generic.dts
29@@ -1,9 +1,587 @@
30 /dts-v1/;
31+
32 / {
33- #address-cells = <1>;
34- #size-cells = <1>;
35- aliases {
36- } ;
37+ #address-cells = <0x1>;
38+ #size-cells = <0x1>;
39+ compatible = "xlnx,microblaze";
40+ model = "Xilinx MicroBlaze";
41+ hard-reset-gpios = <0x1 0x0 0x1>;
42+
43+ cpus {
44+ #address-cells = <0x1>;
45+ #cpus = <0x1>;
46+ #size-cells = <0x0>;
47+
48+ cpu@0 {
49+ bus-handle = <0x2>;
50+ clock-frequency = <0xbebc200>;
51+ clocks = <0x3>;
52+ compatible = "xlnx,microblaze-10.0";
53+ d-cache-baseaddr = <0x80000000>;
54+ d-cache-highaddr = <0xbfffffff>;
55+ d-cache-line-size = <0x20>;
56+ d-cache-size = <0x4000>;
57+ device_type = "cpu";
58+ i-cache-baseaddr = <0x80000000>;
59+ i-cache-highaddr = <0xbfffffff>;
60+ i-cache-line-size = <0x10>;
61+ i-cache-size = <0x4000>;
62+ interrupt-handle = <0x4>;
63+ model = "microblaze,10.0";
64+ timebase-frequency = <0xbebc200>;
65+ xlnx,addr-size = <0x20>;
66+ xlnx,addr-tag-bits = <0x10>;
67+ xlnx,allow-dcache-wr = <0x1>;
68+ xlnx,allow-icache-wr = <0x1>;
69+ xlnx,area-optimized = <0x0>;
70+ xlnx,async-interrupt = <0x1>;
71+ xlnx,async-wakeup = <0x3>;
72+ xlnx,avoid-primitives = <0x0>;
73+ xlnx,base-vectors = <0x0>;
74+ xlnx,branch-target-cache-size = <0x0>;
75+ xlnx,cache-byte-size = <0x4000>;
76+ xlnx,d-axi = <0x1>;
77+ xlnx,d-lmb = <0x1>;
78+ xlnx,d-lmb-mon = <0x0>;
79+ xlnx,daddr-size = <0x20>;
80+ xlnx,data-size = <0x20>;
81+ xlnx,dc-axi-mon = <0x0>;
82+ xlnx,dcache-addr-tag = <0x10>;
83+ xlnx,dcache-always-used = <0x1>;
84+ xlnx,dcache-byte-size = <0x4000>;
85+ xlnx,dcache-data-width = <0x0>;
86+ xlnx,dcache-force-tag-lutram = <0x0>;
87+ xlnx,dcache-line-len = <0x8>;
88+ xlnx,dcache-use-writeback = <0x0>;
89+ xlnx,dcache-victims = <0x0>;
90+ xlnx,debug-counter-width = <0x20>;
91+ xlnx,debug-enabled = <0x1>;
92+ xlnx,debug-event-counters = <0x5>;
93+ xlnx,debug-external-trace = <0x0>;
94+ xlnx,debug-interface = <0x0>;
95+ xlnx,debug-latency-counters = <0x1>;
96+ xlnx,debug-profile-size = <0x0>;
97+ xlnx,debug-trace-async-reset = <0x0>;
98+ xlnx,debug-trace-size = <0x2000>;
99+ xlnx,div-zero-exception = <0x1>;
100+ xlnx,dp-axi-mon = <0x0>;
101+ xlnx,dynamic-bus-sizing = <0x0>;
102+ xlnx,ecc-use-ce-exception = <0x0>;
103+ xlnx,edge-is-positive = <0x1>;
104+ xlnx,enable-discrete-ports = <0x0>;
105+ xlnx,endianness = <0x1>;
106+ xlnx,fault-tolerant = <0x0>;
107+ xlnx,fpu-exception = <0x0>;
108+ xlnx,freq = <0xbebc200>;
109+ xlnx,fsl-exception = <0x0>;
110+ xlnx,fsl-links = <0x0>;
111+ xlnx,i-axi = <0x0>;
112+ xlnx,i-lmb = <0x1>;
113+ xlnx,i-lmb-mon = <0x0>;
114+ xlnx,iaddr-size = <0x20>;
115+ xlnx,ic-axi-mon = <0x0>;
116+ xlnx,icache-always-used = <0x1>;
117+ xlnx,icache-data-width = <0x0>;
118+ xlnx,icache-force-tag-lutram = <0x0>;
119+ xlnx,icache-line-len = <0x4>;
120+ xlnx,icache-streams = <0x1>;
121+ xlnx,icache-victims = <0x8>;
122+ xlnx,ill-opcode-exception = <0x1>;
123+ xlnx,imprecise-exceptions = <0x0>;
124+ xlnx,instr-size = <0x20>;
125+ xlnx,interconnect = <0x2>;
126+ xlnx,interrupt-is-edge = <0x0>;
127+ xlnx,interrupt-mon = <0x0>;
128+ xlnx,ip-axi-mon = <0x0>;
129+ xlnx,lockstep-master = <0x0>;
130+ xlnx,lockstep-select = <0x0>;
131+ xlnx,lockstep-slave = <0x0>;
132+ xlnx,mmu-dtlb-size = <0x4>;
133+ xlnx,mmu-itlb-size = <0x2>;
134+ xlnx,mmu-privileged-instr = <0x0>;
135+ xlnx,mmu-tlb-access = <0x3>;
136+ xlnx,mmu-zones = <0x2>;
137+ xlnx,num-sync-ff-clk = <0x2>;
138+ xlnx,num-sync-ff-clk-debug = <0x2>;
139+ xlnx,num-sync-ff-clk-irq = <0x1>;
140+ xlnx,num-sync-ff-dbg-clk = <0x1>;
141+ xlnx,num-sync-ff-dbg-trace-clk = <0x2>;
142+ xlnx,number-of-pc-brk = <0x1>;
143+ xlnx,number-of-rd-addr-brk = <0x0>;
144+ xlnx,number-of-wr-addr-brk = <0x0>;
145+ xlnx,opcode-0x0-illegal = <0x1>;
146+ xlnx,optimization = <0x0>;
147+ xlnx,pc-width = <0x20>;
148+ xlnx,piaddr-size = <0x20>;
149+ xlnx,pvr = <0x2>;
150+ xlnx,pvr-user1 = <0x0>;
151+ xlnx,pvr-user2 = <0x0>;
152+ xlnx,reset-msr = <0x0>;
153+ xlnx,reset-msr-bip = <0x0>;
154+ xlnx,reset-msr-dce = <0x0>;
155+ xlnx,reset-msr-ee = <0x0>;
156+ xlnx,reset-msr-eip = <0x0>;
157+ xlnx,reset-msr-ice = <0x0>;
158+ xlnx,reset-msr-ie = <0x0>;
159+ xlnx,sco = <0x0>;
160+ xlnx,trace = <0x0>;
161+ xlnx,unaligned-exceptions = <0x1>;
162+ xlnx,use-barrel = <0x1>;
163+ xlnx,use-branch-target-cache = <0x0>;
164+ xlnx,use-config-reset = <0x0>;
165+ xlnx,use-dcache = <0x1>;
166+ xlnx,use-div = <0x1>;
167+ xlnx,use-ext-brk = <0x0>;
168+ xlnx,use-ext-nm-brk = <0x0>;
169+ xlnx,use-extended-fsl-instr = <0x0>;
170+ xlnx,use-fpu = <0x0>;
171+ xlnx,use-hw-mul = <0x2>;
172+ xlnx,use-icache = <0x1>;
173+ xlnx,use-interrupt = <0x2>;
174+ xlnx,use-mmu = <0x3>;
175+ xlnx,use-msr-instr = <0x1>;
176+ xlnx,use-non-secure = <0x0>;
177+ xlnx,use-pcmp-instr = <0x1>;
178+ xlnx,use-reorder-instr = <0x1>;
179+ xlnx,use-stack-protection = <0x0>;
180+ };
181+ };
182+
183+ clocks {
184+ #address-cells = <0x1>;
185+ #size-cells = <0x0>;
186+
187+ clk_cpu@0 {
188+ #clock-cells = <0x0>;
189+ clock-frequency = <0xbebc200>;
190+ clock-output-names = "clk_cpu";
191+ compatible = "fixed-clock";
192+ reg = <0x0>;
193+ linux,phandle = <0x3>;
194+ phandle = <0x3>;
195+ };
196+
197+ clk_bus_0@1 {
198+ #clock-cells = <0x0>;
199+ clock-frequency = <0xbebc200>;
200+ clock-output-names = "clk_bus_0";
201+ compatible = "fixed-clock";
202+ reg = <0x1>;
203+ linux,phandle = <0x8>;
204+ phandle = <0x8>;
205+ };
206+ };
207+
208+ amba_pl {
209+ #address-cells = <0x1>;
210+ #size-cells = <0x1>;
211+ compatible = "simple-bus";
212+ ranges;
213+ linux,phandle = <0x2>;
214+ phandle = <0x2>;
215+
216+ ethernet@40c00000 {
217+ axistream-connected = <0x5>;
218+ axistream-control-connected = <0x5>;
219+ clock-frequency = <0x5f5e100>;
220+ compatible = "xlnx,axi-ethernet-1.00.a";
221+ device_type = "network";
222+ interrupt-names = "interrupt";
223+ interrupt-parent = <0x4>;
224+ interrupts = <0x4 0x2>;
225+ phy-mode = "gmii";
226+ reg = <0x40c00000 0x40000>;
227+ xlnx = <0x0>;
228+ xlnx,axiliteclkrate = <0x0>;
229+ xlnx,axisclkrate = <0x0>;
230+ xlnx,clockselection = <0x0>;
231+ xlnx,enableasyncsgmii = <0x0>;
232+ xlnx,gt-type = <0x0>;
233+ xlnx,gtinex = <0x0>;
234+ xlnx,gtlocation = <0x0>;
235+ xlnx,gtrefclksrc = <0x0>;
236+ xlnx,include-dre;
237+ xlnx,instantiatebitslice0 = <0x0>;
238+ xlnx,phy-type = <0x1>;
239+ xlnx,phyaddr = <0x1>;
240+ xlnx,rable = <0x0>;
241+ xlnx,rxcsum = <0x0>;
242+ xlnx,rxlane0-placement = <0x0>;
243+ xlnx,rxlane1-placement = <0x0>;
244+ xlnx,rxmem = <0x1000>;
245+ xlnx,rxnibblebitslice0used = <0x0>;
246+ xlnx,tx-in-upper-nibble = <0x1>;
247+ xlnx,txcsum = <0x0>;
248+ xlnx,txlane0-placement = <0x0>;
249+ xlnx,txlane1-placement = <0x0>;
250+ phy-handle = <0x6>;
251+ local-mac-address = [00 0a 35 00 22 01];
252+ linux,phandle = <0x7>;
253+ phandle = <0x7>;
254+
255+ mdio {
256+ #address-cells = <0x1>;
257+ #size-cells = <0x0>;
258+
259+ phy@7 {
260+ device_type = "ethernet-phy";
261+ reg = <0x7>;
262+ linux,phandle = <0x6>;
263+ phandle = <0x6>;
264+ };
265+ };
266+ };
267+
268+ dma@41e00000 {
269+ #dma-cells = <0x1>;
270+ axistream-connected = <0x7>;
271+ axistream-control-connected = <0x7>;
272+ clock-frequency = <0xbebc200>;
273+ clock-names = "s_axi_lite_aclk";
274+ clocks = <0x8>;
275+ compatible = "xlnx,eth-dma";
276+ interrupt-names = "mm2s_introut", "s2mm_introut";
277+ interrupt-parent = <0x4>;
278+ interrupts = <0x3 0x2 0x2 0x2>;
279+ reg = <0x41e00000 0x10000>;
280+ xlnx,include-dre;
281+ linux,phandle = <0x5>;
282+ phandle = <0x5>;
283+ };
284+
285+ timer@41c00000 {
286+ clock-frequency = <0xbebc200>;
287+ clocks = <0x8>;
288+ compatible = "xlnx,xps-timer-1.00.a";
289+ interrupt-names = "interrupt";
290+ interrupt-parent = <0x4>;
291+ interrupts = <0x5 0x2>;
292+ reg = <0x41c00000 0x10000>;
293+ xlnx,count-width = <0x20>;
294+ xlnx,gen0-assert = <0x1>;
295+ xlnx,gen1-assert = <0x1>;
296+ xlnx,one-timer-only = <0x0>;
297+ xlnx,trig0-assert = <0x1>;
298+ xlnx,trig1-assert = <0x1>;
299+ };
300+
301+ gpio@40010000 {
302+ #gpio-cells = <0x2>;
303+ clock-frequency = <0xbebc200>;
304+ clock-names = "s_axi_aclk";
305+ clocks = <0x8>;
306+ compatible = "xlnx,xps-gpio-1.00.a";
307+ gpio-controller;
308+ reg = <0x40010000 0x10000>;
309+ xlnx,all-inputs = <0x1>;
310+ xlnx,all-inputs-2 = <0x0>;
311+ xlnx,all-outputs = <0x0>;
312+ xlnx,all-outputs-2 = <0x0>;
313+ xlnx,dout-default = <0x0>;
314+ xlnx,dout-default-2 = <0x0>;
315+ xlnx,gpio-width = <0x1>;
316+ xlnx,gpio2-width = <0x20>;
317+ xlnx,interrupt-present = <0x0>;
318+ xlnx,is-dual = <0x0>;
319+ xlnx,tri-default = <0xffffffff>;
320+ xlnx,tri-default-2 = <0xffffffff>;
321+ };
322+
323+ gpio@40020000 {
324+ #gpio-cells = <0x2>;
325+ clock-frequency = <0xbebc200>;
326+ clock-names = "s_axi_aclk";
327+ clocks = <0x8>;
328+ compatible = "xlnx,xps-gpio-1.00.a";
329+ gpio-controller;
330+ reg = <0x40020000 0x10000>;
331+ xlnx,all-inputs = <0x1>;
332+ xlnx,all-inputs-2 = <0x0>;
333+ xlnx,all-outputs = <0x0>;
334+ xlnx,all-outputs-2 = <0x0>;
335+ xlnx,dout-default = <0x0>;
336+ xlnx,dout-default-2 = <0x0>;
337+ xlnx,gpio-width = <0x4>;
338+ xlnx,gpio2-width = <0x20>;
339+ xlnx,interrupt-present = <0x0>;
340+ xlnx,is-dual = <0x0>;
341+ xlnx,tri-default = <0xffffffff>;
342+ xlnx,tri-default-2 = <0xffffffff>;
343+ };
344+
345+ i2c@40800000 {
346+ #address-cells = <0x1>;
347+ #size-cells = <0x0>;
348+ clock-frequency = <0xbebc200>;
349+ clocks = <0x8>;
350+ compatible = "xlnx,xps-iic-2.00.a";
351+ interrupt-names = "iic2intc_irpt";
352+ interrupt-parent = <0x4>;
353+ interrupts = <0x1 0x2>;
354+ reg = <0x40800000 0x10000>;
355+
356+ i2cswitch@74 {
357+ compatible = "nxp,pca9548";
358+ #address-cells = <0x1>;
359+ #size-cells = <0x0>;
360+ reg = <0x74>;
361+
362+ i2c@0 {
363+ #address-cells = <0x1>;
364+ #size-cells = <0x0>;
365+ reg = <0x0>;
366+
367+ clock-generator@5d {
368+ #clock-cells = <0x0>;
369+ compatible = "silabs,si570";
370+ temperature-stability = <0x32>;
371+ reg = <0x5d>;
372+ factory-fout = <0x9502f90>;
373+ clock-frequency = <0x8d9ee20>;
374+ };
375+ };
376+
377+ i2c@3 {
378+ #address-cells = <0x1>;
379+ #size-cells = <0x0>;
380+ reg = <0x3>;
381+
382+ eeprom@54 {
383+ compatible = "at,24c08";
384+ reg = <0x54>;
385+ };
386+ };
387+ };
388+ };
389+
390+ gpio@40030000 {
391+ #gpio-cells = <0x2>;
392+ clock-frequency = <0xbebc200>;
393+ clock-names = "s_axi_aclk";
394+ clocks = <0x8>;
395+ compatible = "xlnx,xps-gpio-1.00.a";
396+ gpio-controller;
397+ reg = <0x40030000 0x10000>;
398+ xlnx,all-inputs = <0x0>;
399+ xlnx,all-inputs-2 = <0x0>;
400+ xlnx,all-outputs = <0x1>;
401+ xlnx,all-outputs-2 = <0x0>;
402+ xlnx,dout-default = <0x0>;
403+ xlnx,dout-default-2 = <0x0>;
404+ xlnx,gpio-width = <0x8>;
405+ xlnx,gpio2-width = <0x20>;
406+ xlnx,interrupt-present = <0x0>;
407+ xlnx,is-dual = <0x0>;
408+ xlnx,tri-default = <0xffffffff>;
409+ xlnx,tri-default-2 = <0xffffffff>;
410+ };
411+
412+ flash@60000000 {
413+ bank-width = <0x2>;
414+ compatible = "cfi-flash";
415+ reg = <0x60000000 0x8000000>;
416+ xlnx,axi-clk-period-ps = <0x1388>;
417+ xlnx,include-datawidth-matching-0 = <0x1>;
418+ xlnx,include-datawidth-matching-1 = <0x1>;
419+ xlnx,include-datawidth-matching-2 = <0x1>;
420+ xlnx,include-datawidth-matching-3 = <0x1>;
421+ xlnx,include-negedge-ioregs = <0x0>;
422+ xlnx,lflash-period-ps = <0x1388>;
423+ xlnx,linear-flash-sync-burst = <0x0>;
424+ xlnx,max-mem-width = <0x10>;
425+ xlnx,mem-a-lsb = <0x0>;
426+ xlnx,mem-a-msb = <0x1f>;
427+ xlnx,mem0-type = <0x2>;
428+ xlnx,mem0-width = <0x10>;
429+ xlnx,mem1-type = <0x0>;
430+ xlnx,mem1-width = <0x10>;
431+ xlnx,mem2-type = <0x0>;
432+ xlnx,mem2-width = <0x10>;
433+ xlnx,mem3-type = <0x0>;
434+ xlnx,mem3-width = <0x10>;
435+ xlnx,num-banks-mem = <0x1>;
436+ xlnx,page-size = <0x10>;
437+ xlnx,parity-type-mem-0 = <0x0>;
438+ xlnx,parity-type-mem-1 = <0x0>;
439+ xlnx,parity-type-mem-2 = <0x0>;
440+ xlnx,parity-type-mem-3 = <0x0>;
441+ xlnx,port-diff = <0x0>;
442+ xlnx,s-axi-en-reg = <0x0>;
443+ xlnx,s-axi-mem-addr-width = <0x20>;
444+ xlnx,s-axi-mem-data-width = <0x20>;
445+ xlnx,s-axi-mem-id-width = <0x1>;
446+ xlnx,s-axi-reg-addr-width = <0x5>;
447+ xlnx,s-axi-reg-data-width = <0x20>;
448+ xlnx,synch-pipedelay-0 = <0x1>;
449+ xlnx,synch-pipedelay-1 = <0x1>;
450+ xlnx,synch-pipedelay-2 = <0x1>;
451+ xlnx,synch-pipedelay-3 = <0x1>;
452+ xlnx,tavdv-ps-mem-0 = <0x1fbd0>;
453+ xlnx,tavdv-ps-mem-1 = <0x3a98>;
454+ xlnx,tavdv-ps-mem-2 = <0x3a98>;
455+ xlnx,tavdv-ps-mem-3 = <0x3a98>;
456+ xlnx,tcedv-ps-mem-0 = <0x1fbd0>;
457+ xlnx,tcedv-ps-mem-1 = <0x3a98>;
458+ xlnx,tcedv-ps-mem-2 = <0x3a98>;
459+ xlnx,tcedv-ps-mem-3 = <0x3a98>;
460+ xlnx,thzce-ps-mem-0 = <0x88b8>;
461+ xlnx,thzce-ps-mem-1 = <0x1b58>;
462+ xlnx,thzce-ps-mem-2 = <0x1b58>;
463+ xlnx,thzce-ps-mem-3 = <0x1b58>;
464+ xlnx,thzoe-ps-mem-0 = <0x1b58>;
465+ xlnx,thzoe-ps-mem-1 = <0x1b58>;
466+ xlnx,thzoe-ps-mem-2 = <0x1b58>;
467+ xlnx,thzoe-ps-mem-3 = <0x1b58>;
468+ xlnx,tlzwe-ps-mem-0 = <0xc350>;
469+ xlnx,tlzwe-ps-mem-1 = <0x0>;
470+ xlnx,tlzwe-ps-mem-2 = <0x0>;
471+ xlnx,tlzwe-ps-mem-3 = <0x0>;
472+ xlnx,tpacc-ps-flash-0 = <0x61a8>;
473+ xlnx,tpacc-ps-flash-1 = <0x61a8>;
474+ xlnx,tpacc-ps-flash-2 = <0x61a8>;
475+ xlnx,tpacc-ps-flash-3 = <0x61a8>;
476+ xlnx,twc-ps-mem-0 = <0x11170>;
477+ xlnx,twc-ps-mem-1 = <0x3a98>;
478+ xlnx,twc-ps-mem-2 = <0x3a98>;
479+ xlnx,twc-ps-mem-3 = <0x3a98>;
480+ xlnx,twp-ps-mem-0 = <0x13880>;
481+ xlnx,twp-ps-mem-1 = <0x2ee0>;
482+ xlnx,twp-ps-mem-2 = <0x2ee0>;
483+ xlnx,twp-ps-mem-3 = <0x2ee0>;
484+ xlnx,twph-ps-mem-0 = <0x13880>;
485+ xlnx,twph-ps-mem-1 = <0x2ee0>;
486+ xlnx,twph-ps-mem-2 = <0x2ee0>;
487+ xlnx,twph-ps-mem-3 = <0x2ee0>;
488+ xlnx,use-startup = <0x0>;
489+ xlnx,use-startup-int = <0x0>;
490+ xlnx,wr-rec-time-mem-0 = <0x186a0>;
491+ xlnx,wr-rec-time-mem-1 = <0x6978>;
492+ xlnx,wr-rec-time-mem-2 = <0x6978>;
493+ xlnx,wr-rec-time-mem-3 = <0x6978>;
494+ #address-cells = <0x1>;
495+ #size-cells = <0x1>;
496+
497+ partition@0x00000000 {
498+ label = "fpga";
499+ reg = <0x0 0xb00000>;
500+ };
501+
502+ partition@0x00b00000 {
503+ label = "boot";
504+ reg = <0xb00000 0x80000>;
505+ };
506+
507+ partition@0x00b80000 {
508+ label = "bootenv";
509+ reg = <0xb80000 0x20000>;
510+ };
511+
512+ partition@0x00ba0000 {
513+ label = "kernel";
514+ reg = <0xba0000 0xc00000>;
515+ };
516+
517+ partition@0x017a0000 {
518+ label = "spare";
519+ reg = <0x17a0000 0x0>;
520+ };
521+ };
522+
523+ interrupt-controller@41200000 {
524+ #interrupt-cells = <0x2>;
525+ compatible = "xlnx,xps-intc-1.00.a";
526+ interrupt-controller;
527+ reg = <0x41200000 0x10000>;
528+ xlnx,kind-of-intr = <0x0>;
529+ xlnx,num-intr-inputs = <0x6>;
530+ linux,phandle = <0x4>;
531+ phandle = <0x4>;
532+ };
533+
534+ gpio@40040000 {
535+ #gpio-cells = <0x2>;
536+ clock-frequency = <0xbebc200>;
537+ clock-names = "s_axi_aclk";
538+ clocks = <0x8>;
539+ compatible = "xlnx,xps-gpio-1.00.a";
540+ gpio-controller;
541+ reg = <0x40040000 0x10000>;
542+ xlnx,all-inputs = <0x1>;
543+ xlnx,all-inputs-2 = <0x0>;
544+ xlnx,all-outputs = <0x0>;
545+ xlnx,all-outputs-2 = <0x0>;
546+ xlnx,dout-default = <0x0>;
547+ xlnx,dout-default-2 = <0x0>;
548+ xlnx,gpio-width = <0x5>;
549+ xlnx,gpio2-width = <0x20>;
550+ xlnx,interrupt-present = <0x0>;
551+ xlnx,is-dual = <0x0>;
552+ xlnx,tri-default = <0xffffffff>;
553+ xlnx,tri-default-2 = <0xffffffff>;
554+ };
555+
556+ gpio@40000000 {
557+ #gpio-cells = <0x2>;
558+ clock-frequency = <0xbebc200>;
559+ clock-names = "s_axi_aclk";
560+ clocks = <0x8>;
561+ compatible = "xlnx,xps-gpio-1.00.a";
562+ gpio-controller;
563+ reg = <0x40000000 0x10000>;
564+ xlnx,all-inputs = <0x0>;
565+ xlnx,all-inputs-2 = <0x0>;
566+ xlnx,all-outputs = <0x1>;
567+ xlnx,all-outputs-2 = <0x0>;
568+ xlnx,dout-default = <0x0>;
569+ xlnx,dout-default-2 = <0x0>;
570+ xlnx,gpio-width = <0x1>;
571+ xlnx,gpio2-width = <0x20>;
572+ xlnx,interrupt-present = <0x0>;
573+ xlnx,is-dual = <0x0>;
574+ xlnx,tri-default = <0xffffffff>;
575+ xlnx,tri-default-2 = <0xffffffff>;
576+ linux,phandle = <0x1>;
577+ phandle = <0x1>;
578+ };
579+
580+ serial@44a00000 {
581+ clock-frequency = <0xbebc200>;
582+ clocks = <0x8>;
583+ compatible = "xlnx,xps-uart16550-2.00.a", "ns16550a";
584+ current-speed = <0x1c200>;
585+ device_type = "serial";
586+ interrupt-names = "ip2intc_irpt";
587+ interrupt-parent = <0x4>;
588+ interrupts = <0x0 0x2>;
589+ port-number = <0x0>;
590+ reg = <0x44a00000 0x10000>;
591+ reg-offset = <0x1000>;
592+ reg-shift = <0x2>;
593+ xlnx,external-xin-clk-hz = <0x17d7840>;
594+ xlnx,external-xin-clk-hz-d = <0x19>;
595+ xlnx,has-external-rclk = <0x0>;
596+ xlnx,has-external-xin = <0x0>;
597+ xlnx,is-a-16550 = <0x1>;
598+ xlnx,s-axi-aclk-freq-hz-d = "200.0";
599+ xlnx,use-modem-ports = <0x1>;
600+ xlnx,use-user-ports = <0x1>;
601+ };
602+ };
603+
604 chosen {
605- } ;
606-} ;
607+ bootargs = "console=ttyS0,115200 earlyprintk";
608+ stdout-path = "serial0:115200n8";
609+ };
610+
611+ aliases {
612+ ethernet0 = "/amba_pl/ethernet@40c00000";
613+ i2c0 = "/amba_pl/i2c@40800000";
614+ serial0 = "/amba_pl/serial@44a00000";
615+ };
616+
617+ memory {
618+ device_type = "memory";
619+ reg = <0x80000000 0x40000000>;
620+ };
621+};
622+
623diff --git a/board/xilinx/microblaze-generic/config.mk b/board/xilinx/microblaze-generic/config.mk
624index 1dee2d6..cb75fde 100644
625--- a/board/xilinx/microblaze-generic/config.mk
626+++ b/board/xilinx/microblaze-generic/config.mk
627@@ -1,20 +1,10 @@
628-#
629-# (C) Copyright 2007 - 2016 Michal Simek
630-#
631-# Michal SIMEK <monstr@monstr.eu>
632-#
633-# SPDX-License-Identifier: GPL-2.0+
634-#
635-
636-CPU_VER := $(shell echo $(CONFIG_XILINX_MICROBLAZE0_HW_VER))
637-
638-# USE_HW_MUL can be 0, 1, or 2, defining a hierarchy of HW Mul support.
639-CPUFLAGS-$(subst 1,,$(CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL)) += -mxl-multiply-high
640-CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL) += -mno-xl-soft-mul
641-CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_DIV) += -mno-xl-soft-div
642-CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_BARREL) += -mxl-barrel-shift
643-CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_PCMP_INSTR) += -mxl-pattern-compare
644-
645-CPUFLAGS-1 += $(call cc-option,-mcpu=v$(CPU_VER))
646-
647-PLATFORM_CPPFLAGS += $(CPUFLAGS-1) $(CPUFLAGS-2)
648+TEXT_BASE = 0x80400000
649+CONFIG_SYS_TEXT_BASE = 0x80400000
650+
651+PLATFORM_CPPFLAGS += -mxl-barrel-shift
652+PLATFORM_CPPFLAGS += -mno-xl-soft-div
653+PLATFORM_CPPFLAGS += -mxl-pattern-compare
654+PLATFORM_CPPFLAGS += -mxl-multiply-high
655+PLATFORM_CPPFLAGS += -mno-xl-soft-mul
656+PLATFORM_CPPFLAGS += -mcpu=v10.0
657+PLATFORM_CPPFLAGS += -fgnu89-inline
658diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig
659index 08d99f2..bac6939 100644
660--- a/configs/microblaze-generic_defconfig
661+++ b/configs/microblaze-generic_defconfig
662@@ -1,5 +1,4 @@
663 CONFIG_MICROBLAZE=y
664-CONFIG_SYS_TEXT_BASE=0x29000000
665 CONFIG_SPL_LIBCOMMON_SUPPORT=y
666 CONFIG_SPL_LIBGENERIC_SUPPORT=y
667 CONFIG_SPL_SERIAL_SUPPORT=y
668@@ -8,50 +7,50 @@ CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR=1
669 CONFIG_XILINX_MICROBLAZE0_USE_BARREL=1
670 CONFIG_XILINX_MICROBLAZE0_USE_DIV=1
671 CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL=1
672+CONFIG_SYS_TEXT_BASE=0x80400000
673 CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic"
674 CONFIG_FIT=y
675 CONFIG_FIT_VERBOSE=y
676-CONFIG_BOOTDELAY=-1
677-CONFIG_USE_BOOTARGS=y
678-CONFIG_BOOTARGS="root=romfs"
679+CONFIG_BOOTDELAY=4
680 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
681-CONFIG_SPL=y
682-CONFIG_SPL_BOARD_INIT=y
683-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
684 CONFIG_SPL_NOR_SUPPORT=y
685 CONFIG_SPL_OS_BOOT=y
686 CONFIG_SYS_OS_BASE=0x2c060000
687 CONFIG_HUSH_PARSER=y
688-CONFIG_SYS_PROMPT="U-Boot-mONStR> "
689-CONFIG_CMD_IMLS=y
690-CONFIG_CMD_SPL=y
691+CONFIG_SYS_PROMPT="U-Boot> "
692 CONFIG_CMD_ASKENV=y
693-CONFIG_CMD_GPIO=y
694 CONFIG_CMD_SAVES=y
695 # CONFIG_CMD_SETEXPR is not set
696-CONFIG_CMD_TFTPPUT=y
697+CONFIG_SYS_ENET=y
698+CONFIG_NET=y
699+CONFIG_NETDEVICES=y
700+CONFIG_CMD_NET=y
701 CONFIG_CMD_DHCP=y
702+CONFIG_CMD_NFS=y
703 CONFIG_CMD_MII=y
704 CONFIG_CMD_PING=y
705 CONFIG_CMD_JFFS2=y
706-CONFIG_SPL_OF_CONTROL=y
707 CONFIG_OF_EMBED=y
708-CONFIG_ENV_IS_IN_FLASH=y
709-CONFIG_NETCONSOLE=y
710-CONFIG_SPL_DM=y
711-CONFIG_MTD_NOR_FLASH=y
712-CONFIG_PHY_ATHEROS=y
713-CONFIG_PHY_BROADCOM=y
714-CONFIG_PHY_DAVICOM=y
715-CONFIG_PHY_LXT=y
716-CONFIG_PHY_MARVELL=y
717-CONFIG_PHY_MICREL=y
718-CONFIG_PHY_MICREL_KSZ90X1=y
719-CONFIG_PHY_NATSEMI=y
720-CONFIG_PHY_REALTEK=y
721-CONFIG_PHY_VITESSE=y
722 CONFIG_DM_ETH=y
723+CONFIG_SYS_MALLOC_F=y
724+CONFIG_SYS_GENERIC_BOARD=y
725 CONFIG_XILINX_AXIEMAC=y
726-CONFIG_XILINX_EMACLITE=y
727 CONFIG_SYS_NS16550=y
728-CONFIG_XILINX_UARTLITE=y
729+CONFIG_CMD_FLASH=y
730+CONFIG_MTD_NOR_FLASH=y
731+CONFIG_CMD_IMLS=y
732+CONFIG_CMD_GPIO=y
733+CONFIG_CMD_TFTPPUT=y
734+CONFIG_NETCONSOLE=y
735+CONFIG_XILINX_FSL_LINKS=0
736+CONFIG_PHY_GIGE=y
737+CONFIG_ENV_IS_IN_FLASH=y
738+CONFIG_PHY_MICREL=y
739+CONFIG_PHY_MICREL_KSZ90X1=y
740+CONFIG_SPL_DM_SERIAL=y
741+CONFIG_SPL_OF_LIBFDT=y
742+CONFIG_PHY_XILINX=y
743+# CONFIG_SPL is not set
744+# CONFIG_CMD_EEPROM is not set
745+# CONFIG_BOOTARGS is not set
746+# CONFIG_USE_BOOTARGS is not set
747diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h
748index 16481cb..1377c5e 100644
749--- a/include/configs/microblaze-generic.h
750+++ b/include/configs/microblaze-generic.h
751@@ -1,254 +1,178 @@
752-/*
753- * (C) Copyright 2007-2010 Michal Simek
754- *
755- * Michal SIMEK <monstr@monstr.eu>
756- *
757- * SPDX-License-Identifier: GPL-2.0+
758- */
759-
760 #ifndef __CONFIG_H
761 #define __CONFIG_H
762
763-#include "../board/xilinx/microblaze-generic/xparameters.h"
764-
765-/* MicroBlaze CPU */
766-#define MICROBLAZE_V5 1
767-
768-/* linear and spi flash memory */
769-#ifdef XILINX_FLASH_START
770-#define FLASH
771-#undef SPIFLASH
772-#undef RAMENV /* hold environment in flash */
773-#else
774-#ifdef XILINX_SPI_FLASH_BASEADDR
775-#undef FLASH
776-#define SPIFLASH
777-#undef RAMENV /* hold environment in flash */
778-#else
779-#undef FLASH
780-#undef SPIFLASH
781-#define RAMENV /* hold environment in RAM */
782-#endif
783-#endif
784-
785-/* uart */
786-/* The following table includes the supported baudrates */
787-# define CONFIG_SYS_BAUDRATE_TABLE \
788- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
789-
790-/* setting reset address */
791-/*#define CONFIG_SYS_RESET_ADDRESS CONFIG_SYS_TEXT_BASE*/
792-
793-/* gpio */
794-#ifdef XILINX_GPIO_BASEADDR
795-# define CONFIG_XILINX_GPIO
796-# define CONFIG_SYS_GPIO_0_ADDR XILINX_GPIO_BASEADDR
797-#endif
798-
799-/* watchdog */
800-#if defined(XILINX_WATCHDOG_BASEADDR) && defined(XILINX_WATCHDOG_IRQ)
801-# define CONFIG_WATCHDOG_BASEADDR XILINX_WATCHDOG_BASEADDR
802-# define CONFIG_WATCHDOG_IRQ XILINX_WATCHDOG_IRQ
803-# ifndef CONFIG_SPL_BUILD
804-# define CONFIG_HW_WATCHDOG
805-# define CONFIG_XILINX_TB_WATCHDOG
806-# endif
807-#endif
808-
809-#define CONFIG_SYS_MALLOC_LEN 0xC0000
810-
811-/* Stack location before relocation */
812-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_TEXT_BASE - \
813- CONFIG_SYS_MALLOC_F_LEN)
814-
815-/*
816- * CFI flash memory layout - Example
817- * CONFIG_SYS_FLASH_BASE = 0x2200_0000;
818- * CONFIG_SYS_FLASH_SIZE = 0x0080_0000; 8MB
819- *
820- * SECT_SIZE = 0x20000; 128kB is one sector
821- * CONFIG_ENV_SIZE = SECT_SIZE; 128kB environment store
822- *
823- * 0x2200_0000 CONFIG_SYS_FLASH_BASE
824- * FREE 256kB
825- * 0x2204_0000 CONFIG_ENV_ADDR
826- * ENV_AREA 128kB
827- * 0x2206_0000
828- * FREE
829- * 0x2280_0000 CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE
830- *
831- */
832-
833-#ifdef FLASH
834-# define CONFIG_SYS_FLASH_BASE XILINX_FLASH_START
835-# define CONFIG_SYS_FLASH_SIZE XILINX_FLASH_SIZE
836-# define CONFIG_SYS_FLASH_CFI 1
837-# define CONFIG_FLASH_CFI_DRIVER 1
838-/* ?empty sector */
839-# define CONFIG_SYS_FLASH_EMPTY_INFO 1
840-/* max number of memory banks */
841-# define CONFIG_SYS_MAX_FLASH_BANKS 1
842-/* max number of sectors on one chip */
843-# define CONFIG_SYS_MAX_FLASH_SECT 512
844-/* hardware flash protection */
845-# define CONFIG_SYS_FLASH_PROTECTION
846-/* use buffered writes (20x faster) */
847-# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
848-# ifdef RAMENV
849-# define CONFIG_ENV_SIZE 0x1000
850-# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
851-
852-# else /* FLASH && !RAMENV */
853-/* 128K(one sector) for env */
854-# define CONFIG_ENV_SECT_SIZE 0x20000
855-# define CONFIG_ENV_ADDR \
856- (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
857-# define CONFIG_ENV_SIZE 0x20000
858-# endif /* FLASH && !RAMBOOT */
859-#else /* !FLASH */
860-
861-#ifdef SPIFLASH
862-# define CONFIG_SYS_SPI_BASE XILINX_SPI_FLASH_BASEADDR
863-# define CONFIG_SPI 1
864-# define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
865-# define CONFIG_SF_DEFAULT_SPEED XILINX_SPI_FLASH_MAX_FREQ
866-# define CONFIG_SF_DEFAULT_CS XILINX_SPI_FLASH_CS
867-
868-# ifdef RAMENV
869-# define CONFIG_ENV_SIZE 0x1000
870-# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
871-
872-# else /* SPIFLASH && !RAMENV */
873-# define CONFIG_ENV_SPI_MODE SPI_MODE_3
874-# define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
875-# define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
876-/* 128K(two sectors) for env */
877-# define CONFIG_ENV_SECT_SIZE 0x10000
878-# define CONFIG_ENV_SIZE (2 * CONFIG_ENV_SECT_SIZE)
879-/* Warning: adjust the offset in respect of other flash content and size */
880-# define CONFIG_ENV_OFFSET (128 * CONFIG_ENV_SECT_SIZE) /* at 8MB */
881-# endif /* SPIFLASH && !RAMBOOT */
882-#else /* !SPIFLASH */
883-
884-/* ENV in RAM */
885-# define CONFIG_ENV_SIZE 0x1000
886-# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
887-#endif /* !SPIFLASH */
888-#endif /* !FLASH */
889-
890-#if defined(XILINX_USE_ICACHE)
891-# define CONFIG_ICACHE
892-#else
893-# undef CONFIG_ICACHE
894-#endif
895-
896-#if defined(XILINX_USE_DCACHE)
897-# define CONFIG_DCACHE
898-#else
899-# undef CONFIG_DCACHE
900-#endif
901-
902-#ifndef XILINX_DCACHE_BYTE_SIZE
903-#define XILINX_DCACHE_BYTE_SIZE 32768
904-#endif
905-
906-/*
907- * BOOTP options
908- */
909+#define CONFIG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400 }
910+
911+/* processor - microblaze_0 */
912+#define XILINX_USE_MSR_INSTR 1
913+#define XILINX_USE_ICACHE 1
914+#define XILINX_USE_DCACHE 1
915+#define XILINX_DCACHE_BYTE_SIZE 16384
916+#define XILINX_PVR 2
917+#define MICROBLAZE_V5
918+#define CONFIG_CMD_IRQ
919+#define CONFIG_DCACHE
920+#define CONFIG_ICACHE
921+
922+/* main_memory - ddr3_sdram */
923+
924+
925+/* uart - rs232_uart */
926+#define CONFIG_SYS_NS16550_COM1 ((XILINX_UART16550_BASEADDR & ~0xF) + 0x1000)
927+#define CONFIG_SYS_NS16550_REG_SIZE -4
928+#define CONSOLE_ARG "console=console=ttyS0,115200\0"
929+#define CONFIG_SYS_NS16550_SERIAL
930+#define CONFIG_CONS_INDEX 1
931+#define ESERIAL0 "eserial0=setenv stdout eserial0;setenv stdin eserial0\0"
932+#define SERIAL_MULTI "serial=setenv stdout serial;setenv stdin serial\0"
933+#define CONFIG_SYS_NS16550_CLK 200000000
934+#define CONFIG_BAUDRATE 115200
935+
936+/* ethernet - axi_ethernet */
937+#define CONFIG_PHY_XILINX
938+#define CONFIG_MII
939+#define CONFIG_PHY_MARVELL
940+#define CONFIG_PHY_NATSEMI
941+#define CONFIG_NET_MULTI
942+#define CONFIG_PHY_REALTEK
943+#define CONFIG_NETCONSOLE 1
944+#define CONFIG_SERVERIP 172.25.229.115
945+#define CONFIG_IPADDR
946+
947+/* nor_flash - linear_flash */
948+#define CONFIG_SYS_FLASH_BASE 0x60000000
949+#define CONFIG_FLASH_END 0x68000000
950+#define CONFIG_SYS_MAX_FLASH_SECT 2048
951+#define CONFIG_SYS_FLASH_PROTECTION
952+#define CONFIG_SYS_FLASH_EMPTY_INFO
953+#define CONFIG_SYS_FLASH_CFI
954+#define CONFIG_FLASH_CFI_DRIVER
955+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
956+#define CONFIG_SYS_MAX_FLASH_BANKS 1
957+
958+/* timer - axi_timer_0 */
959+
960+/* gpio - reset_gpio */
961+#define XILINX_GPIO_BASEADDR 0x40000000
962+#define CONFIG_SYS_GPIO_0_ADDR 0x40000000
963+#define CONFIG_XILINX_GPIO
964+
965+/* intc - microblaze_0_axi_intc */
966+
967+/* FPGA */
968+
969+/* Memory testing handling */
970+#define CONFIG_SYS_MEMTEST_START 0x80000000
971+#define CONFIG_SYS_MEMTEST_END (0x80000000 + 0x1000)
972+#define CONFIG_SYS_LOAD_ADDR 0x80000000 /* default load address */
973+
974+/* global pointer options */
975+#define CONFIG_SYS_GBL_DATA_OFFSET (0x40000000 - GENERATED_GBL_DATA_SIZE)
976+
977+/* Size of malloc() pool */
978+#define SIZE 0x100000
979+#define CONFIG_SYS_MALLOC_LEN SIZE
980+#define CONFIG_SYS_MONITOR_LEN SIZE
981+#define CONFIG_SYS_MONITOR_BASE (0x80000000 + CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_MONITOR_LEN - GENERATED_BD_INFO_SIZE)
982+#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
983+
984+/* stack */
985+#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_TEXT_BASE - CONFIG_SYS_MALLOC_F_LEN)
986+
987+/* No of_control support yet*/
988+
989+/* BOOTP options */
990+#define CONFIG_BOOTP_SERVERIP
991 #define CONFIG_BOOTP_BOOTFILESIZE
992 #define CONFIG_BOOTP_BOOTPATH
993 #define CONFIG_BOOTP_GATEWAY
994 #define CONFIG_BOOTP_HOSTNAME
995+#define CONFIG_BOOTP_MAY_FAIL
996+#define CONFIG_BOOTP_DNS
997+#define CONFIG_BOOTP_SUBNETMASK
998+#define CONFIG_BOOTP_PXE
999
1000-#if defined(CONFIG_CMD_JFFS2)
1001-# define CONFIG_MTD_PARTITIONS
1002-#endif
1003-
1004-#if defined(CONFIG_CMD_UBI)
1005-# define CONFIG_MTD_PARTITIONS
1006-#endif
1007-
1008-#if defined(CONFIG_MTD_PARTITIONS)
1009-/* MTD partitions */
1010-#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
1011-#define CONFIG_FLASH_CFI_MTD
1012-
1013-/* default mtd partition table */
1014-#endif
1015-
1016-/* size of console buffer */
1017-#define CONFIG_SYS_CBSIZE 512
1018-/* max number of command args */
1019-#define CONFIG_SYS_MAXARGS 15
1020-#define CONFIG_SYS_LONGHELP
1021-/* default load address */
1022-#define CONFIG_SYS_LOAD_ADDR 0
1023-
1024-#define CONFIG_HOSTNAME XILINX_BOARD_NAME
1025-#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm"
1026-
1027-/* architecture dependent code */
1028-#define CONFIG_SYS_USR_EXCEP /* user exception */
1029-
1030-#define CONFIG_PREBOOT "echo U-BOOT for ${hostname};setenv preboot;echo"
1031-
1032-#ifndef CONFIG_EXTRA_ENV_SETTINGS
1033-#define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" \
1034- "nor0=flash-0\0"\
1035- "mtdparts=mtdparts=flash-0:"\
1036- "256k(u-boot),256k(env),3m(kernel),"\
1037- "1m(romfs),1m(cramfs),-(jffs2)\0"\
1038- "nc=setenv stdout nc;"\
1039- "setenv stdin nc\0" \
1040- "serial=setenv stdout serial;"\
1041- "setenv stdin serial\0"
1042-#endif
1043-
1044+/*Command line configuration.*/
1045 #define CONFIG_CMDLINE_EDITING
1046+#define CONFIG_AUTO_COMPLETE
1047
1048-/* Enable flat device tree support */
1049-#define CONFIG_LMB 1
1050-
1051-#if defined(CONFIG_XILINX_AXIEMAC)
1052-# define CONFIG_MII 1
1053-# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1
1054-#else
1055-# undef CONFIG_MII
1056-#endif
1057-
1058-/* SPL part */
1059-#define CONFIG_SPL_FRAMEWORK
1060+/* Miscellaneous configurable options */
1061+#define CONFIG_SYS_CBSIZE 2048/* Console I/O Buffer Size */
1062+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
1063+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
1064
1065-#ifdef CONFIG_SYS_FLASH_BASE
1066-# define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_FLASH_BASE
1067-#endif
1068-
1069-/* for booting directly linux */
1070
1071-#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + \
1072- 0x40000)
1073-#define CONFIG_SYS_FDT_SIZE (16<<10)
1074-#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_TEXT_BASE + \
1075- 0x1000000)
1076+/* Use the HUSH parser */
1077+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
1078
1079-/* SP location before relocation, must use scratch RAM */
1080-/* BRAM start */
1081-#define CONFIG_SYS_INIT_RAM_ADDR 0x0
1082-/* BRAM size - will be generated */
1083-#define CONFIG_SYS_INIT_RAM_SIZE 0x100000
1084+#define CONFIG_ENV_VARS_UBOOT_CONFIG
1085+#define CONFIG_ENV_OVERWRITE /* Allow to overwrite the u-boot environment variables */
1086
1087-# define CONFIG_SPL_STACK_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
1088- CONFIG_SYS_INIT_RAM_SIZE - \
1089- CONFIG_SYS_MALLOC_F_LEN)
1090+#define CONFIG_LMB
1091
1092-/* Just for sure that there is a space for stack */
1093-#define CONFIG_SPL_STACK_SIZE 0x100
1094+/* FDT support */
1095+#define CONFIG_DISPLAY_BOARDINFO_LATE
1096
1097-#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
1098
1099-#define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_INIT_RAM_SIZE - \
1100- CONFIG_SYS_INIT_RAM_ADDR - \
1101- CONFIG_SYS_MALLOC_F_LEN - \
1102- CONFIG_SPL_STACK_SIZE)
1103+/* architecture dependent code */
1104+#define CONFIG_SYS_USR_EXCEP /* user exception */
1105+#define CONFIG_SYS_HZ 1000
1106+
1107+/* Boot Argument Buffer Size */
1108+#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
1109+#define CONFIG_SYS_LONGHELP
1110+/* Initial memory map for Linux */
1111+#define CONFIG_SYS_BOOTMAPSZ 0x8000000
1112+
1113+/* Environment settings*/
1114+#define CONFIG_ENV_ADDR 0x60b80000
1115+#define CONFIG_ENV_SIZE 0x20000
1116+#define CONFIG_ENV_SECT_SIZE 0x20000
1117+/* PREBOOT */
1118+#define CONFIG_PREBOOT "echo U-BOOT for ${hostname};setenv preboot; echo; dhcp"
1119+
1120+/* Extra U-Boot Env settings */
1121+#define CONFIG_EXTRA_ENV_SETTINGS \
1122+ SERIAL_MULTI \
1123+ CONSOLE_ARG \
1124+ ESERIAL0 \
1125+ "nc=setenv stdout nc;setenv stdin nc;\0" \
1126+ "ethaddr=00:0a:35:00:22:01\0" \
1127+ "autoload=no\0" \
1128+ "sdbootdev=0\0" \
1129+ "clobstart=0x81000000\0" \
1130+ "netstart=0x81000000\0" \
1131+ "dtbnetstart=0x82800000\0" \
1132+ "loadaddr=0x81000000\0" \
1133+ "bootsize=0x80000\0" \
1134+ "bootstart=0x60b00000\0" \
1135+ "boot_img=u-boot-s.bin\0" \
1136+ "load_boot=tftpboot ${clobstart} ${boot_img}\0" \
1137+ "update_boot=setenv img boot; setenv psize ${bootsize}; setenv installcmd \"install_boot\"; run load_boot test_img; setenv img; setenv psize; setenv installcmd\0" \
1138+ "install_boot=protect off ${bootstart} +${bootsize} && erase ${bootstart} +${bootsize} && " "cp.b ${clobstart} ${bootstart} ${filesize}\0" \
1139+ "bootenvsize=0x20000\0" \
1140+ "bootenvstart=0x60b80000\0" \
1141+ "eraseenv=protect off ${bootenvstart} +${bootenvsize} && erase ${bootenvstart} +${bootenvsize}\0" \
1142+ "kernelsize=0xc00000\0" \
1143+ "kernelstart=0x60ba0000\0" \
1144+ "kernel_img=image.ub\0" \
1145+ "load_kernel=tftpboot ${clobstart} ${kernel_img}\0" \
1146+ "update_kernel=setenv img kernel; setenv psize ${kernelsize}; setenv installcmd \"install_kernel\"; run load_kernel test_crc; setenv img; setenv psize; setenv installcmd\0" \
1147+ "install_kernel=protect off ${kernelstart} +${kernelsize} && erase ${kernelstart} +${kernelsize} && " "cp.b ${clobstart} ${kernelstart} ${filesize}\0" \
1148+ "cp_kernel2ram=cp.b ${kernelstart} ${netstart} ${kernelsize}\0" \
1149+ "fpgasize=0xb00000\0" \
1150+ "fpgastart=0x60000000\0" \
1151+ "fpga_img=system.bit.bin\0" \
1152+ "load_fpga=tftpboot ${clobstart} ${fpga_img}\0" \
1153+ "update_fpga=setenv img fpga; setenv psize ${fpgasize}; setenv installcmd \"install_fpga\"; run load_fpga test_img; setenv img; setenv psize; setenv installcmd\0" \
1154+ "install_fpga=protect off ${fpgastart} +${fpgasize} && erase ${fpgastart} +${fpgasize} && " "cp.b ${clobstart} ${fpgastart} ${filesize}\0" \
1155+ "fault=echo ${img} image size is greater than allocated place - partition ${img} is NOT UPDATED\0" \
1156+ "test_crc=if imi ${clobstart}; then run test_img; else echo ${img} Bad CRC - ${img} is NOT UPDATED; fi\0" \
1157+ "test_img=setenv var \"if test ${filesize} -gt ${psize}\\; then run fault\\; else run ${installcmd}\\; fi\"; run var; setenv var\0" \
1158+ "netboot=tftpboot ${netstart} ${kernel_img} && bootm\0" \
1159+ "default_bootcmd=run cp_kernel2ram && bootm ${netstart}\0" \
1160+""
1161+/* BOOTCOMMAND */
1162+#define CONFIG_BOOTCOMMAND "run default_bootcmd"
1163
1164-#endif /* __CONFIG_H */
1165+#endif
1166--
11672.7.4
1168
diff --git a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2018.1.bb b/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2018.1.bb
index 6388cf33..e503f825 100644
--- a/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2018.1.bb
+++ b/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-xlnx_2018.1.bb
@@ -8,6 +8,8 @@ SRCREV ?= "949e5cb9a736bac32ea8886e3953da55bdd30754"
8include u-boot-xlnx.inc 8include u-boot-xlnx.inc
9include u-boot-spl-zynq-init.inc 9include u-boot-spl-zynq-init.inc
10 10
11SRC_URI_append_kc705-microblazeel = " file://microblaze-kc705-Convert-microblaze-generic-to-k.patch"
12
11LICENSE = "GPLv2+" 13LICENSE = "GPLv2+"
12LIC_FILES_CHKSUM = "file://README;beginline=1;endline=6;md5=157ab8408beab40cd8ce1dc69f702a6c" 14LIC_FILES_CHKSUM = "file://README;beginline=1;endline=6;md5=157ab8408beab40cd8ce1dc69f702a6c"
13 15
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2026-08-18 21:56:41 +0000