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| author | Sivaprasad Addepalli <sivaprasad.addepalli@xilinx.com> | 2024-04-10 06:17:56 +0530 |
|---|---|---|
| committer | Siva Addepalli <sivaprasad.addepalli@xilinx.com> | 2024-04-10 08:07:10 +0530 |
| commit | 4ea7a9cf93c7345c316babfbbbedb5740bddea88 (patch) | |
| tree | ab18cbef3b7e93da606dd295b8155bca35720a9a /meta-xilinx-standalone | |
| parent | c01790e541f5fa37c8053bafff08a1805358753b (diff) | |
| download | meta-xilinx-4ea7a9cf93c7345c316babfbbbedb5740bddea88.tar.gz | |
linux-xlnx : Updated SRCREV for 2024.1_9495
net: axienet: Correct tx_buff size when DRE is not enabled
clk: clocking-wizard: calculate dividers fractional parts
v4l: xilinx: dprxss: Fix xhdcp1x_rx_init() function declaration
v4l: xilinx: dprxss: Fix gcc warning
staging: xilinx_hdcp: Fix gcc warning
mtd: spi-nor: Use same bit mask macro in spi & spi-nor core
Revert "drivers: clk: zynqmp: add hack to use old algorithm for divider round rate"
fpga: Fix the reset handling
remoteproc: zynqmp_r5: Clean up support for Versal NET CTCM
mtd: spi-nor: Add support for BP3 at SR bit 5
mtd: spi-nor: Use params->size for flash size info
mtd: spi-nor: Avoid writing EAR register for flashes less than 16MB
mtd: spi-nor: Use nor->info->id[0] for manufacturer id
Diffstat (limited to 'meta-xilinx-standalone')
0 files changed, 0 insertions, 0 deletions