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| author | Sivaprasad Addepalli <sivaprasad.addepalli@xilinx.com> | 2024-08-28 14:38:34 +0530 |
|---|---|---|
| committer | Siva Addepalli <sivaprasad.addepalli@xilinx.com> | 2024-08-28 16:37:10 +0530 |
| commit | 27cea51ef44cf1d0d0400e86c71c75a73a4270ec (patch) | |
| tree | 55a1227fcb0360ea39270cd4747b149112aea8d7 /meta-xilinx-standalone | |
| parent | 5b652c57a5bc97feb0544989f22e8f03835cd67b (diff) | |
| download | meta-xilinx-27cea51ef44cf1d0d0400e86c71c75a73a4270ec.tar.gz | |
embeddedsw : Updated SRCREV for 2024.2_8999
i3cpsx: Use macros instead of hard code values
i3cpsx: Update the driver version
sw_services: xilloader: Check configuration limiter during secure boot
sw_services: xilnvm: Provisioning Configuration Limiter parameters
dp14txss: Updated the GT quad address macro in the pt and txo application due to change of the macro in gt quad.
xilsecure: Add RsaPrivateDecrypt for Versal_AiePg2
xilpm: versal_net: Add API for LLC flush in CMN block
scripts: Add support for ASU processor
bsp: Move the platform specific macro definitions from toolchain and scripts to bspconfig
sw_services:xilloader: Fixed build issue
sw_services:xilpuf: Add xilpuf library support for spartan ultrascale plus
sw_services:xilsecure: Add xilsecure library support for spartan ultrascale plus
sw_services:xilnvm: Add xilnvm library support for spartan ultrascale plus
xilpm: versal_common: server: Add new APIs for subsystem specific address management
xilpm: versal_common: server: Handle memory region nodes for default subsystem
xilpm: versal_common: server: Add API for new memory region nodes
sw_services:xilsecure:Add Key Transfer to ASU via IPI
sw_services: xilloader: Add support for loading CDO after secure boot
Diffstat (limited to 'meta-xilinx-standalone')
| -rw-r--r-- | meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index c49be402..ba3d6206 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | |||
| @@ -19,7 +19,7 @@ ESW_REV[2022.2] = "5330a64c8efd14f0eef09befdbb8d3d738c33ec2" | |||
| 19 | ESW_REV[2023.1] = "af784f742dad0ca6e69e05baf8de51152c396b9a" | 19 | ESW_REV[2023.1] = "af784f742dad0ca6e69e05baf8de51152c396b9a" |
| 20 | ESW_REV[2023.2] = "e847e1935dca630615e5f7dc694365a44b89699c" | 20 | ESW_REV[2023.2] = "e847e1935dca630615e5f7dc694365a44b89699c" |
| 21 | ESW_REV[2024.1] = "b173d246826f662b9a98215d8f39e93d39d699b4" | 21 | ESW_REV[2024.1] = "b173d246826f662b9a98215d8f39e93d39d699b4" |
| 22 | ESW_REV[2024.2] = "77f04421ff7b3b56cf548cef465d7a69c9a7f7c3" | 22 | ESW_REV[2024.2] = "81e45556701e782ee721189a109dacf56766e31e" |
| 23 | SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or 'INVALID'}" | 23 | SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or 'INVALID'}" |
| 24 | 24 | ||
| 25 | EMBEDDEDSW_BRANCHARG ?= "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH') != '']}" | 25 | EMBEDDEDSW_BRANCHARG ?= "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH') != '']}" |