diff options
| author | Sivaprasad Addepalli <sivaprasad.addepalli@xilinx.com> | 2024-09-30 11:14:37 +0530 |
|---|---|---|
| committer | Siva Addepalli <sivaprasad.addepalli@xilinx.com> | 2024-10-01 11:27:10 +0530 |
| commit | ffc8f2c9c676161379a26bd99e3101b995959344 (patch) | |
| tree | 35dbbde2fe0b8e7ac3640c0170b59efd9a7131d7 /meta-xilinx-standalone/classes | |
| parent | 49a3c0b5a8323e8d3d15671834fa3d867ef4f553 (diff) | |
| download | meta-xilinx-ffc8f2c9c676161379a26bd99e3101b995959344.tar.gz | |
embeddedsw : Updated SRCREV for 2024.2_4867
v_hdmiphy1: Added min max for DPLL
scripts: pyesw: validate_hw: Add special handling for dhrystone
xilpm: versal_aiepg2: Fix plm build error
sw_services: xilsecure: Add Redundancy check for XPlmi_MemCpy64
xdmapcie:Modify the format specifier for BAR allocation debug prints
pciepsu:Modify format specifier for BAR allocation debug prints
bsp: standalone: Add support for AXI NOC2 DDR region in MPU initialization
sw_services:xilasu:Added timeout
xilpm: versal_common: server: Fix compilation warning
versalnet: xilnvm doxygen updates to RTF
versal: xilnvm doxygen updates for RTF
xilnvm: fixed doxygen grouping
peripheral_tests: Fixed source code-format issue.
peripheral_tests: Fix compilation warnings
sw_services:xilnvm: Fix for debug prints in efuse client example
spdif: Fix the interrupt id mapping
xilpm: versal: support skipping ADC/DAC housecleaning
sw_services: xilplmi: Fix compilation errors
ThirdParty: openamp: libmetal version dependency
sw_services: xilpuf: Corrected comments in function header
lib: sw_apps: openamp: sdt: versal: Add RPU1 to A72 channel
Diffstat (limited to 'meta-xilinx-standalone/classes')
| -rw-r--r-- | meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index d893a559..471379db 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | |||
| @@ -19,7 +19,7 @@ ESW_REV[2022.2] = "5330a64c8efd14f0eef09befdbb8d3d738c33ec2" | |||
| 19 | ESW_REV[2023.1] = "af784f742dad0ca6e69e05baf8de51152c396b9a" | 19 | ESW_REV[2023.1] = "af784f742dad0ca6e69e05baf8de51152c396b9a" |
| 20 | ESW_REV[2023.2] = "e847e1935dca630615e5f7dc694365a44b89699c" | 20 | ESW_REV[2023.2] = "e847e1935dca630615e5f7dc694365a44b89699c" |
| 21 | ESW_REV[2024.1] = "b173d246826f662b9a98215d8f39e93d39d699b4" | 21 | ESW_REV[2024.1] = "b173d246826f662b9a98215d8f39e93d39d699b4" |
| 22 | ESW_REV[2024.2] = "06b156a1f3e09cc33ca333180a772bbfa4f614c2" | 22 | ESW_REV[2024.2] = "449d38b0c5e4bf00ea763525b4c11c35f528c2f4" |
| 23 | SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or 'INVALID'}" | 23 | SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or 'INVALID'}" |
| 24 | 24 | ||
| 25 | EMBEDDEDSW_BRANCHARG ?= "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH') != '']}" | 25 | EMBEDDEDSW_BRANCHARG ?= "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH') != '']}" |