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| author | Sivaprasad Addepalli <sivaprasad.addepalli@xilinx.com> | 2023-12-01 18:30:57 +0530 |
|---|---|---|
| committer | Siva Addepalli <sivaprasad.addepalli@xilinx.com> | 2023-12-01 20:07:11 +0530 |
| commit | e749ada4fa0aba143eab8654b8f95804ffb7ba27 (patch) | |
| tree | 4322c6d0dbaa7f80b5f6a24bca094599989101eb /meta-xilinx-standalone/classes | |
| parent | 05f5cba600c16cc6d78a00916e79d334c6c5cea1 (diff) | |
| download | meta-xilinx-e749ada4fa0aba143eab8654b8f95804ffb7ba27.tar.gz | |
embeddedsw : Updated SRCREV for 2024.1_6567
lib: ARMv8: add Xil_MemMap()
Xilsem:Enable XILSEM_ENABLE_SSIT macro using tcl
lib: bsp: standalone: src: Fix race condition in yocto flow
dp21rxss: Add support for system device-tree flow.
dp21rxss: Add support for system device-tree flow
dp21txss: Add support for system device-tree flow
dp21txss: Add support for system device-tree flow
dp21: Add support for system device-tree flow
dp21: Add support for system device-tree flow
lwip: Remove PMC/PSM/PMU entries from the processor lists of all LwIP components
lib: Add Versal Net specific processors wherever missing
scripts: pyesw: build_app: Update link libraries for freertos
xilpm: versal_net: server: VID support
xilpm: versal_common: server: Allow any I2C controller to control power rails
xilpm: versal_common: server: Issue all I2C commands for a power level change
xilplmi: implemented user modules
drivers: Fixed source code-format issue.
drivers: Fix compilation errors reported with -std=c2x compiler flag
lib: bsp: standalone: Enhance the ability to generate XPAR_CPU_ID definitions based on the reg property in the SDT flow
freertos: Move the selection of config parameters for stdin and stdout into a separate header
xilpm:versal_net: subsystem ipimask restore
Diffstat (limited to 'meta-xilinx-standalone/classes')
| -rw-r--r-- | meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass index 4b69946f..c0e7dbe7 100644 --- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass +++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass | |||
| @@ -12,7 +12,7 @@ BRANCH ??= "${@d.getVarFlag('ESW_BRANCH', d.getVar('ESW_VER')) or '${ESW_VER}'}" | |||
| 12 | ESW_REV[git] = "${AUTOREV}" | 12 | ESW_REV[git] = "${AUTOREV}" |
| 13 | ESW_REV[2023.1] = "af784f742dad0ca6e69e05baf8de51152c396b9a" | 13 | ESW_REV[2023.1] = "af784f742dad0ca6e69e05baf8de51152c396b9a" |
| 14 | ESW_REV[2023.2] = "c9a0ee31b2a14cbcfcb56ca369037319b4ad4847" | 14 | ESW_REV[2023.2] = "c9a0ee31b2a14cbcfcb56ca369037319b4ad4847" |
| 15 | ESW_REV[2024.1] = "ca5a8225f1105d64a66ed1e99b98f7b8635faf39" | 15 | ESW_REV[2024.1] = "cecc2ff6d66a8fae4ff5232f85e2b1ae9b015add" |
| 16 | SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" | 16 | SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" |
| 17 | 17 | ||
| 18 | EMBEDDEDSW_BRANCHARG ?= "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH') != '']}" | 18 | EMBEDDEDSW_BRANCHARG ?= "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH') != '']}" |