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| author | Sivaprasad Addepalli <sivaprasad.addepalli@xilinx.com> | 2023-10-13 20:28:30 +0530 |
|---|---|---|
| committer | Siva Addepalli <sivaprasad.addepalli@xilinx.com> | 2023-10-13 22:17:10 +0530 |
| commit | cacf35fc667fa48299a289022dd217ac2fcb75a6 (patch) | |
| tree | 4706d69dfbcd230572827e3006809c570ac0ef0f /meta-xilinx-standalone/classes | |
| parent | bceea9b18e3c33b91098a26ff00a851defc89cb7 (diff) | |
| download | meta-xilinx-cacf35fc667fa48299a289022dd217ac2fcb75a6.tar.gz | |
u-boot-xlnx : Updated SRCREV for 2024.1_7279
arm64: zynqmp: Remove kv260 PL overlays
test: py: tests: Add test case to write and read multiple files from MMC
test: py: tests: Extend i2c test to cover all buses
spi: cadence_qspi: Fix versal ospi indirect write timed out issue
configs: zynq: Disable the config CONFIG_SPI_FLASH_USE_4K_SECTORS
spi: cadence_ospi_versal: Add support for 64-bit address
arm64: zynqmp: Remove unused xlnx,phy-type DT property
net: phy: xilinx_phy: Get rid of using property xlnx, phy-type
Revert "arm64: zynqmp: Add the fclk node"
arm64: versal-net: Add missing xlnx,versal-firmware string
arm64: zynqmp: Add output-enable pins to SOM KD240
arm64: versal-net: Append xlnx,versal-clk to clock node
arm64: zynqmp: Enable uart0 with pinctrl description
arm64: zynqmp: Add support for K26 rev2 boards
arm64: zynqmp: Setup default si570 frequency to 156.25MHz
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
Diffstat (limited to 'meta-xilinx-standalone/classes')
0 files changed, 0 insertions, 0 deletions