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authorMark Hatle <mark.hatle@amd.com>2024-06-04 16:51:04 -0600
committerMark Hatle <mark.hatle@amd.com>2024-06-04 17:00:14 -0600
commit195e1fa9fb13b21bc41af4e0747d4646caeb65e5 (patch)
tree27e92386d23080a44149b7ef0678e1bbddff2a2e /meta-xilinx-standalone-sdt/classes-recipe
parent3ea2f6cddd54881585084e7cb6f948c398ed980a (diff)
downloadmeta-xilinx-195e1fa9fb13b21bc41af4e0747d4646caeb65e5.tar.gz
various: Remove SOC_VARIANT, split versal and versal-net, add machine_features
SOC_VARIANT has been remove, we are now only using the YP standard SOC_FAMILY configuration. The defined families are: zynq, zynqmp, versal and versal-net. Our decision of breaking up versal-net from versal, is based on the SoC CPU changes from cortexa72/r5 to cortexa78/r52, thus we're treating it as a different SoC family. In order to capture the individual capabilities that we used to handle via SOC_VARIANT, we have defined the following features (some may have been previously defined): - mali400 (zynqmp eg and ev) - vcu (zynqmp ev) - rfsoc (zynqmp dr RF capabiltiies) - aie - (versal ai & premium) - vdu - (versal ai) SOC_VARIANT_ARCH and SOC_FAMILY_ARCH are now obsolete and replaced by MACHINE_ARCH. This is based on the guideline that any recipes that use MACHINE_FEATURES should be MACHINE_ARCH specific. Signed-off-by: Mark Hatle <mark.hatle@amd.com>
Diffstat (limited to 'meta-xilinx-standalone-sdt/classes-recipe')
-rw-r--r--meta-xilinx-standalone-sdt/classes-recipe/esw.bbclass27
1 files changed, 10 insertions, 17 deletions
diff --git a/meta-xilinx-standalone-sdt/classes-recipe/esw.bbclass b/meta-xilinx-standalone-sdt/classes-recipe/esw.bbclass
index a87e1dad..abd08a5d 100644
--- a/meta-xilinx-standalone-sdt/classes-recipe/esw.bbclass
+++ b/meta-xilinx-standalone-sdt/classes-recipe/esw.bbclass
@@ -36,19 +36,7 @@ do_configure[depends] += "device-tree:do_deploy"
36do_compile[depends] += "device-tree:do_deploy" 36do_compile[depends] += "device-tree:do_deploy"
37do_install[depends] += "device-tree:do_deploy" 37do_install[depends] += "device-tree:do_deploy"
38 38
39def get_xlnx_cmake_machine(fam, variant, d): 39def get_xlnx_cmake_processor(tune, machine, d):
40 cmake_machine = fam
41 if (fam == 'zynqmp'):
42 cmake_machine = 'ZynqMP'
43 elif (fam == 'versal'):
44 cmake_machine = 'Versal'
45 if (variant == 'net'):
46 cmake_machine = 'VersalNet'
47 elif (fam == 'zynq'):
48 cmake_machine = 'Zynq'
49 return cmake_machine
50
51def get_xlnx_cmake_processor(tune, machine, variant, d):
52 cmake_processor = tune 40 cmake_processor = tune
53 if tune.startswith('microblaze'): 41 if tune.startswith('microblaze'):
54 if (machine == 'psu_pmu_0'): 42 if (machine == 'psu_pmu_0'):
@@ -67,12 +55,17 @@ def get_xlnx_cmake_processor(tune, machine, variant, d):
67 cmake_processor = 'cortexa53' 55 cmake_processor = 'cortexa53'
68 elif tune == 'cortexa72': 56 elif tune == 'cortexa72':
69 cmake_processor = 'cortexa72' 57 cmake_processor = 'cortexa72'
70 if (variant == 'net'): 58 elif tune == 'cortexa78':
71 cmake_processor = 'cortexa78' 59 cmake_processor = 'cortexa78'
72 return cmake_processor 60 return cmake_processor
73 61
74XLNX_CMAKE_MACHINE = "${@get_xlnx_cmake_machine(d.getVar('SOC_FAMILY'), d.getVar('SOC_VARIANT'), d)}" 62XLNX_CMAKE_MACHINE = "undefined"
75XLNX_CMAKE_PROCESSOR = "${@get_xlnx_cmake_processor(d.getVar('DEFAULTTUNE'), d.getVar('ESW_MACHINE'), d.getVar('SOC_VARIANT'), d)}" 63XLNX_CMAKE_MACHINE:zynq = "Zynq"
64XLNX_CMAKE_MACHINE:zynqmp = "ZynqMP"
65XLNX_CMAKE_MACHINE:versal = "Versal"
66XLNX_CMAKE_MACHINE:versal-net = "VersalNet"
67
68XLNX_CMAKE_PROCESSOR = "${@get_xlnx_cmake_processor(d.getVar('DEFAULTTUNE'), d.getVar('ESW_MACHINE'), d)}"
76XLNX_CMAKE_SYSTEM_NAME ?= "Generic" 69XLNX_CMAKE_SYSTEM_NAME ?= "Generic"
77XLNX_CMAKE_BSP_VARS ?= "" 70XLNX_CMAKE_BSP_VARS ?= ""
78 71