Initial restructure/split of meta-xilinx-bsp

Create a new meta-xilinx-core, move core functionality to the core, keeping
board specific files in the bsp layer.

zynqmp-generic changed from require <board> to include, so if meta-xilinx-bsp
is not available it will not fail.

Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>

171 files changed, 21024 insertions, 0 deletions

diff --git a/meta-xilinx-core/COPYING.MIT b/meta-xilinx-core/COPYING.MIT
new file mode 100644
index 00000000..89de3547
--- /dev/null
+++ b/meta-xilinx-core/COPYING.MIT
@@ -0,0 +1,17 @@
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
diff --git a/meta-xilinx-core/README.md b/meta-xilinx-core/README.md
new file mode 100644
index 00000000..cb6c06c8
--- /dev/null
+++ b/meta-xilinx-core/README.md
@@ -0,0 +1,56 @@
+meta-xilinx-core
+================
+
+This layer provides support for MicroBlaze, Zynq and ZynqMP.
+
+
+Maintainers, Mailing list, Patches
+==================================
+
+Please send any patches, pull requests, comments or questions for this layer to
+the [meta-xilinx mailing list](https://lists.yoctoproject.org/listinfo/meta-xilinx):
+
+        meta-xilinx@lists.yoctoproject.org
+
+Maintainers:
+
+        Sai Hari Chandana Kalluri <chandana.kalluri@xilinx.com>
+        Mark Hatle <mark.hatle@xilinx.com>
+
+Dependencies
+============
+
+This layer depends on:
+
+        URI: git://git.openembedded.org/bitbake
+
+        URI: git://git.openembedded.org/openembedded-core
+        layers: meta
+
+Recipe Licenses
+===============
+
+Due to licensing restrictions some recipes in this layer rely on closed source
+or restricted content provided by Xilinx. In order to use these recipes you must
+accept or agree to the licensing terms (e.g. EULA, Export Compliance, NDA,
+Redistribution, etc). This layer **does not enforce** any legal requirement, it
+is the **responsibility of the user** the ensure that they are in compliance
+with any licenses or legal requirements for content used.
+
+In order to use recipes that rely on restricted content the `xilinx` license
+flag must be white-listed in the build configuration (e.g. `local.conf`). This
+can be done on a per package basis:
+
+        LICENSE_FLAGS_WHITELIST += "xilinx_pmu-rom"
+
+or generally:
+
+        LICENSE_FLAGS_WHITELIST += "xilinx"
+
+Generally speaking Xilinx content that is provided as a restricted download
+cannot be obtained without a Xilinx account, in order to use this content you
+must first download it with your Xilinx account and place the downloaded content
+in the `downloads/` directory of your build or on a `PREMIRROR`. Attempting to
+fetch the content using bitbake will fail, indicating the URL from which to
+acquire the content.
+
diff --git a/meta-xilinx-core/README.qemu.md b/meta-xilinx-core/README.qemu.md
new file mode 100644
index 00000000..992e0618
--- /dev/null
+++ b/meta-xilinx-core/README.qemu.md
@@ -0,0 +1,25 @@
+
+ZynqMP - PMU ROM
+----------------
+
+Since Xilinx tool release v2017.1 multiple components (arm-trusted-firmware,
+linux, u-boot, etc.) require the PMU firmware to be loaded. For QEMU this also
+means that the PMU ROM must be loaded so that the PMU firmware can be used.
+
+The PMU ROM is not available for download separately from a location that can be
+accessed without a Xilinx account. As such the PMU ROM must be obtained manually
+by the user. The PMU ROM is available in the ZCU102 PetaLinux BSP, but can be
+extracted without the need for the PetaLinux tools.
+
+Download the BSP (you will need a Xilinx account and agreement to terms):
+
+https://www.xilinx.com/member/forms/download/xef.html?filename=xilinx-zcu102-v2017.1-final.bsp&akdm=1
+
+Once downloaded the PMU ROM can be extracted using the following command and
+place `pmu-rom.elf` in the `deploy/images/zcu102-zynqmp/` directory.
+
+```
+# tar -O -xf xilinx-zcu102-v2017.1-final.bsp \
+    xilinx-zcu102-2017.1/pre-built/linux/images/pmu_rom_qemu_sha3.elf > pmu-rom.elf
+```
+
diff --git a/meta-xilinx-core/classes/fpgamanager_custom.bbclass b/meta-xilinx-core/classes/fpgamanager_custom.bbclass
new file mode 100644
index 00000000..0b5fa249
--- /dev/null
+++ b/meta-xilinx-core/classes/fpgamanager_custom.bbclass
@@ -0,0 +1,85 @@
+LICENSE = "MIT"
+LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/MIT;md5=0835ade698e0bcf8506ecda2f7b4f302"
+
+inherit devicetree
+
+DEPENDS = "dtc-native bootgen-native"
+
+COMPATIBLE_MACHINE ?= "^$"
+COMPATIBLE_MACHINE:zynqmp = ".*"
+COMPATIBLE_MACHINE:zynq = ".*"
+
+PROVIDES = ""
+
+do_fetch[cleandirs] = "${B}"
+
+DT_PADDING_SIZE = "0x1000"
+BOOTGEN_FLAGS ?= " -arch ${SOC_FAMILY} ${@bb.utils.contains('SOC_FAMILY','zynqmp','-w','-process_bitstream bin',d)}"
+
+S ?= "${WORKDIR}"
+FW_DIR ?= ""
+DTSI_PATH ?= ""
+DT_FILES_PATH = "${S}/${DTSI_PATH}"
+
+python (){
+
+    if "git://" in d.getVar("SRC_URI") or "https://" in d.getVar("SRC_URI"):
+        d.setVar("S",'${WORKDIR}/git/'+d.getVar("FW_DIR"))
+    else:
+        if d.getVar("SRC_URI").count(".dtsi") != 1 or d.getVar("SRC_URI").count(".bit") != 1 \
+            or d.getVar("SRC_URI").count("shell.json") != 1:
+            raise bb.parse.SkipRecipe("Need one '.dtsi', one '.bit' and one 'shell.json' file added to SRC_URI")
+
+        d.setVar("DTSI_PATH",os.path.dirname([a for a in d.getVar('SRC_URI').split('file://') if '.dtsi' in a][0]))
+        d.setVar("BIT_PATH",os.path.dirname([a for a in d.getVar('SRC_URI').split('file://') if '.bit' in a][0]))
+        d.setVar("JSON_PATH",os.path.dirname([a for a in d.getVar('SRC_URI').split('file://') if 'shell.json' in a][0]))
+
+        #optional input
+        if '.xclbin' in d.getVar("SRC_URI"):
+            d.setVar("XCL_PATH",os.path.dirname([a for a in d.getVar('SRC_URI').split('file://') if '.xclbin' in a][0]))
+}
+python do_configure() {
+    import glob, re, shutil
+
+    if bb.utils.contains('MACHINE_FEATURES', 'fpga-overlay', False, True, d):
+        bb.warn("Using fpga-manager.bbclass requires fpga-overlay MACHINE_FEATURE to be enabled")
+
+    #renaming firmware-name using $PN as bitstream will be renamed using $PN when generating the bin file
+    orig_dtsi = glob.glob(d.getVar('S')+ (d.getVar('DTSI_PATH') or '') + '/*.dtsi')[0]
+    new_dtsi = d.getVar('S') + '/pl.dtsi_firmwarename'
+    with open(new_dtsi, 'w') as newdtsi:
+        with open(orig_dtsi) as olddtsi:
+            for line in olddtsi:
+                newdtsi.write(re.sub('firmware-name.*\".*\"','firmware-name = \"'+d.getVar('PN')+'.bit.bin\"',line))
+    shutil.move(new_dtsi,orig_dtsi)
+}
+
+python devicetree_do_compile:append() {
+    import glob, subprocess
+    pn = d.getVar('PN')
+    biffile = pn + '.bif'
+
+    with open(biffile, 'w') as f:
+        f.write('all:\n{\n\t' + glob.glob(d.getVar('S')+(d.getVar('BIT_PATH') or '') + '/*.bit')[0] + '\n}')
+
+    bootgenargs = ["bootgen"] + (d.getVar("BOOTGEN_FLAGS") or "").split()
+    bootgenargs += ["-image", biffile, "-o", pn + ".bit.bin"]
+    subprocess.run(bootgenargs, check = True)
+
+    if not os.path.isfile(pn + ".bit.bin"):
+        bb.fatal("bootgen failed. Enable -log debug with bootgen and check logs")
+}
+
+do_install() {
+    install -d ${D}/${nonarch_base_libdir}/firmware/xilinx/${PN}/
+    install -Dm 0644 *.dtbo ${D}/${nonarch_base_libdir}/firmware/xilinx/${PN}/${PN}.dtbo
+    install -Dm 0644 ${PN}.bit.bin ${D}/${nonarch_base_libdir}/firmware/xilinx/${PN}/${PN}.bit.bin
+    if ls ${S}/${XCL_PATH}/*.xclbin >/dev/null 2>&1; then
+        install -Dm 0644 ${S}/${XCL_PATH}/*.xclbin ${D}/${nonarch_base_libdir}/firmware/xilinx/${PN}/${PN}.xclbin
+    fi
+    install -Dm 0644 ${S}/${JSON_PATH}/shell.json ${D}/${nonarch_base_libdir}/firmware/xilinx/${PN}/shell.json
+}
+
+do_deploy[noexec] = "1"
+
+FILES:${PN} += "${nonarch_base_libdir}/firmware/xilinx/${PN}"
diff --git a/meta-xilinx-core/classes/image-types-xilinx-qemu.bbclass b/meta-xilinx-core/classes/image-types-xilinx-qemu.bbclass
new file mode 100644
index 00000000..63318087
--- /dev/null
+++ b/meta-xilinx-core/classes/image-types-xilinx-qemu.bbclass
@@ -0,0 +1,10 @@
+# Define the 'qemu-sd' conversion type
+#
+# This conversion type pads any image to the 512K boundary to ensure that the
+# image file can be used directly with QEMU's SD emulation which requires the
+# block device to match that of valid SD card sizes (which are multiples of
+# 512K).
+
+CONVERSIONTYPES:append = " qemu-sd"
+CONVERSION_CMD:qemu-sd = "cp ${IMAGE_NAME}${IMAGE_NAME_SUFFIX}.${type} ${IMAGE_NAME}${IMAGE_NAME_SUFFIX}.${type}.qemu-sd; truncate -s %256M ${IMAGE_NAME}${IMAGE_NAME_SUFFIX}.${type}.qemu-sd"
+CONVERSION_DEPENDS_qemu-sd = "coreutils-native"
diff --git a/meta-xilinx-core/classes/image-wic-utils.bbclass b/meta-xilinx-core/classes/image-wic-utils.bbclass
new file mode 100644
index 00000000..562f3263
--- /dev/null
+++ b/meta-xilinx-core/classes/image-wic-utils.bbclass
@@ -0,0 +1,51 @@
+# Helper/utility functions to work with the IMAGE_BOOT_FILES variable and its
+# expected behvaior with regards to the contents of the DEPLOY_DIR_IMAGE.
+#
+# The use of these functions assume that the deploy directory is populated with
+# any dependent files/etc. Such that the recipe using these functions depends
+# on the recipe that provides the files being used/queried.
+
+def boot_files_split_expand(d):
+    # IMAGE_BOOT_FILES has extra renaming info in the format '<source>;<target>'
+    for f in (d.getVar("IMAGE_BOOT_FILES") or "").split(" "):
+        parts = f.split(";", 1)
+        sources = [parts[0].strip()]
+        if "*" in parts[0]:
+            # has glob part
+            import glob
+            deployroot = d.getVar("DEPLOY_DIR_IMAGE")
+            sources = []
+            for i in glob.glob(os.path.join(deployroot, parts[0])):
+                sources.append(os.path.basename(i))
+
+        # for all sources, yield an entry
+        for s in sources:
+            if len(parts) == 2:
+                yield s, parts[1].strip()
+            yield s, s
+
+def boot_files_bitstream(d):
+    expectedfiles = [("bitstream", True)]
+    expectedexts = [(".bit", True), (".bin", False)]
+    # search for bitstream paths, use the renamed file. First matching is used
+    for source, target in boot_files_split_expand(d):
+        # skip boot.bin and u-boot.bin, it is not a bitstream
+        skip = ["boot.bin", "u-boot.bin"]
+        if source in skip or target in skip:
+            continue
+
+        for e, t in expectedfiles:
+            if source == e or target == e:
+                return target, t
+        for e, t in expectedexts:
+            if source.endswith(e) or target.endswith(e):
+                return target, t
+    return "", False
+
+def boot_files_dtb_filepath(d):
+    dtbs = (d.getVar("IMAGE_BOOT_FILES") or "").split(" ")
+    for source, target in boot_files_split_expand(d):
+        if target.endswith(".dtb"):
+            return target
+    return ""
+
diff --git a/meta-xilinx-core/classes/kernel-simpleimage.bbclass b/meta-xilinx-core/classes/kernel-simpleimage.bbclass
new file mode 100644
index 00000000..110ee254
--- /dev/null
+++ b/meta-xilinx-core/classes/kernel-simpleimage.bbclass
@@ -0,0 +1,35 @@
+python __anonymous () {
+    kerneltypes = set((d.getVar("KERNEL_IMAGETYPE") or "").split())
+    kerneltypes |= set((d.getVar("KERNEL_IMAGETYPES") or "").split())
+    if any(t.startswith("simpleImage.") for t in kerneltypes):
+        # Enable building of simpleImage
+        bb.build.addtask('do_prep_simpleimage', 'do_compile', 'do_configure', d)
+    uarch = d.getVar("UBOOT_ARCH")
+    if uarch == "microblaze":
+        d.appendVarFlag('do_prep_simpleimage', 'depends', ' virtual/dtb:do_populate_sysroot')
+}
+
+do_prep_simpleimage[dirs] += "${B}"
+do_prep_simpleimage () {
+    install -d ${B}/arch/${ARCH}/boot/dts
+    for type in ${KERNEL_IMAGETYPES} ; do
+        if [ -z "${type##*simpleImage*}" ] && [ ${ARCH} = "microblaze" ]; then
+            ext="${type##*.}"
+            # Microblaze simpleImage only works with dts file
+            cp ${RECIPE_SYSROOT}/boot/devicetree/${ext}.dts ${B}/arch/${ARCH}/boot/dts/
+        fi
+    done
+}
+
+do_deploy:append () {
+    for type in ${KERNEL_IMAGETYPES} ; do
+        if [ -z "${type##*simpleImage*}" ] && [ ${ARCH} = "microblaze" ]; then
+            base_name=${type}-${KERNEL_IMAGE_NAME}
+            install -m 0644 ${KERNEL_OUTPUT_DIR}/${type}.strip $deployDir/${base_name}.strip
+            install -m 0644 ${KERNEL_OUTPUT_DIR}/${type}.unstrip $deployDir/${base_name}.unstrip
+            symlink_name=${type}-${KERNEL_IMAGE_LINK_NAME}
+            ln -sf ${base_name}.strip $deployDir/${symlink_name}.strip
+            ln -sf ${base_name}.unstrip $deployDir/${symlink_name}.unstrip
+        fi
+    done
+}
diff --git a/meta-xilinx-core/classes/qemuboot-xilinx.bbclass b/meta-xilinx-core/classes/qemuboot-xilinx.bbclass
new file mode 100644
index 00000000..48dfa6e2
--- /dev/null
+++ b/meta-xilinx-core/classes/qemuboot-xilinx.bbclass
@@ -0,0 +1,27 @@
+
+# enable the overrides for the context of the conf only
+OVERRIDES .= ":qemuboot-xilinx"
+
+# Default machine targets for Xilinx QEMU (FDT Generic)
+# Allow QB_MACHINE to be overridden by a BSP config
+QB_MACHINE ?= "${QB_MACHINE_XILINX}"
+QB_RNG=""
+QB_MACHINE_XILINX:aarch64 = "-machine arm-generic-fdt"
+QB_MACHINE_XILINX:arm = "-M arm-generic-fdt-7series"
+QB_MACHINE_XILINX:microblaze = "-M microblaze-fdt-plnx"
+
+# defaults
+QB_DEFAULT_KERNEL ?= "none"
+
+inherit qemuboot
+
+# rewrite the qemuboot with the custom sysroot bindir
+python do_write_qemuboot_conf:append() {
+    val = os.path.join(d.getVar('BASE_WORKDIR'), d.getVar('BUILD_SYS'), 'qemu-xilinx-helper-native/1.0-r1/recipe-sysroot-native/usr/bin/')
+    cf.set('config_bsp', 'STAGING_BINDIR_NATIVE', '%s' % val)
+
+    # write out the updated version from this append
+    with open(qemuboot, 'w') as f:
+        cf.write(f)
+}
+
diff --git a/meta-xilinx-core/classes/xilinx-fetch-restricted.bbclass b/meta-xilinx-core/classes/xilinx-fetch-restricted.bbclass
new file mode 100644
index 00000000..a778ec7d
--- /dev/null
+++ b/meta-xilinx-core/classes/xilinx-fetch-restricted.bbclass
@@ -0,0 +1,35 @@
+# This class is setup to override the default fetching for the target recipe.
+# When fetching it forces PREMIRROR only fetching so that no attempts are made
+# to fetch the Xilinx downloads that are restricted to authenticated users only.
+#
+# The purpose of this class is to allow for automatation with pre-downloaded
+# content or content that is available with curated/user defined pre-mirrors
+# and or pre-populated downloads/ directories.
+
+python do_fetch() {
+    xilinx_restricted_url = "xilinx.com/member/forms/download"
+
+    src_uri = (d.getVar('SRC_URI') or "").split()
+    if len(src_uri) == 0:
+        return
+
+    for i in src_uri:
+        if xilinx_restricted_url in i:
+            # force the use of premirrors only, do not attempt download from xilinx.com
+            d.setVar("BB_FETCH_PREMIRRORONLY", "1")
+            break
+
+    try:
+        fetcher = bb.fetch2.Fetch(src_uri, d)
+        fetcher.download()
+    except bb.fetch2.NetworkAccess as e:
+        if xilinx_restricted_url in e.url:
+            # fatal on access to xilinx.com restricted downloads, print the url for manual download
+            bb.fatal("The following download cannot be fetched automatically. " \
+                "Please manually download the file and place it in the 'downloads' directory (or on an available PREMIRROR).\n" \
+                "  %s" % (e.url.split(";")[0]))
+        else:
+            bb.fatal(str(e))
+    except bb.fetch2.BBFetchException as e:
+        bb.fatal(str(e))
+}
diff --git a/meta-xilinx-core/classes/xilinx-platform-init.bbclass b/meta-xilinx-core/classes/xilinx-platform-init.bbclass
new file mode 100644
index 00000000..99f7863a
--- /dev/null
+++ b/meta-xilinx-core/classes/xilinx-platform-init.bbclass
@@ -0,0 +1,14 @@
+# This class should be included by any recipe that wants to access or provide
+# the platform init source files which are used to initialize a Zynq or ZynqMP
+# SoC.
+
+# Define the path to the xilinx platform init code/headers
+PLATFORM_INIT_DIR ?= "/usr/src/xilinx-platform-init"
+
+PLATFORM_INIT_STAGE_DIR = "${STAGING_DIR_HOST}${PLATFORM_INIT_DIR}"
+
+# Target files use for platform init
+PLATFORM_INIT_FILES ?= ""
+PLATFORM_INIT_FILES:zynq = "ps7_init_gpl.c ps7_init_gpl.h"
+PLATFORM_INIT_FILES:zynqmp = "psu_init_gpl.c psu_init_gpl.h"
+
diff --git a/meta-xilinx-core/classes/xilinx-testimage.bbclass b/meta-xilinx-core/classes/xilinx-testimage.bbclass
new file mode 100644
index 00000000..99519637
--- /dev/null
+++ b/meta-xilinx-core/classes/xilinx-testimage.bbclass
@@ -0,0 +1,11 @@
+inherit testimage
+
+HOSTTOOLS += 'ip ping ps scp ssh stty'
+
+python do_testimage:prepend () {
+    from oeqa.core.target.qemu import supported_fstypes
+    supported_fstypes.append('wic.qemu-sd')
+}
+
+IMAGE_AUTOLOGIN = "0"
+IMAGE_FSTYPES = "wic.qemu-sd"
diff --git a/meta-xilinx-core/classes/xlnx-standalone.bbclass b/meta-xilinx-core/classes/xlnx-standalone.bbclass
new file mode 100644
index 00000000..9232b1ef
--- /dev/null
+++ b/meta-xilinx-core/classes/xlnx-standalone.bbclass
@@ -0,0 +1,16 @@
+# Only enabled when ilp32 is enabled.
+def xlnx_ilp32_dict(machdata, d):
+    machdata["elf"] = {
+                        "aarch64" :   (183,    0,    0,          True,          32),
+                        "aarch64_be" :(183,    0,    0,          False,         32),
+                      }
+    return machdata
+
+# Only enabled when microblaze64 is enabled.
+def xlnx_mb64_dict(machdata, d):
+    machdata["elf"] = {
+                        "microblaze":  (189,   0,    0,          False,         64),
+                        "microblazeeb":(189,   0,    0,          False,         64),
+                        "microblazeel":(189,   0,    0,          True,          64),
+                      }
+    return machdata
diff --git a/meta-xilinx-core/conf/bblayers.conf.sample b/meta-xilinx-core/conf/bblayers.conf.sample
new file mode 100644
index 00000000..890ef3b6
--- /dev/null
+++ b/meta-xilinx-core/conf/bblayers.conf.sample
@@ -0,0 +1,37 @@
+LCONF_VERSION = "7"
+
+BBPATH = "${TOPDIR}"
+BBFILES ?= ""
+
+BBLAYERS ?= " \
+    ##OEROOT##/meta \
+    ##OEROOT##/meta-poky \
+    ##OEROOT##/../meta-openembedded/meta-perl \
+    ##OEROOT##/../meta-openembedded/meta-python \
+    ##OEROOT##/../meta-openembedded/meta-filesystems \
+    ##OEROOT##/../meta-openembedded/meta-gnome \
+    ##OEROOT##/../meta-openembedded/meta-multimedia \
+    ##OEROOT##/../meta-openembedded/meta-networking \
+    ##OEROOT##/../meta-openembedded/meta-webserver \
+    ##OEROOT##/../meta-openembedded/meta-xfce \
+    ##OEROOT##/../meta-openembedded/meta-initramfs \
+    ##OEROOT##/../meta-openembedded/meta-oe \
+    ##OEROOT##/../meta-browser/meta-chromium \
+    ##OEROOT##/../meta-qt5 \
+    ##OEROOT##/../meta-xilinx/meta-xilinx-core \
+    ##OEROOT##/../meta-xilinx/meta-xilinx-bsp \
+    ##OEROOT##/../meta-xilinx/meta-xilinx-pynq \
+    ##OEROOT##/../meta-xilinx/meta-xilinx-standalone \
+    ##OEROOT##/../meta-xilinx/meta-xilinx-contrib \
+    ##OEROOT##/../meta-xilinx-tools \
+    ##OEROOT##/../meta-petalinux \
+    ##OEROOT##/../meta-virtualization \
+    ##OEROOT##/../meta-openamp \
+    ##OEROOT##/../meta-jupyter \
+    ##OEROOT##/../meta-python2 \
+    ##OEROOT##/../meta-clang \
+"
+
+BBLAYERS_NON_REMOVABLE ?= " \
+    ##OEROOT##/meta \
+"
diff --git a/meta-xilinx-core/conf/layer.conf b/meta-xilinx-core/conf/layer.conf
new file mode 100644
index 00000000..c505501f
--- /dev/null
+++ b/meta-xilinx-core/conf/layer.conf
@@ -0,0 +1,42 @@
+# We have a conf and classes directory, add to BBPATH
+BBPATH .= ":${LAYERDIR}"
+
+# We have a packages directory, add to BBFILES
+BBFILES += "${LAYERDIR}/recipes-*/*/*.bb"
+BBFILES += "${LAYERDIR}/recipes-*/*/*.bbappend"
+
+BBFILE_COLLECTIONS += "xilinx"
+BBFILE_PATTERN_xilinx = "^${LAYERDIR}/"
+BBFILE_PRIORITY_xilinx = "5"
+
+BBFILES_DYNAMIC += " \
+openembedded-layer:${LAYERDIR}/dynamic-layers/openembedded-layer/recipes-*/*/*.bb \
+openembedded-layer:${LAYERDIR}/dynamic-layers/openembedded-layer/recipes-*/*/*.bbappend \
+chromium-browser-layer:${LAYERDIR}/dynamic-layers/chromium-browser-layer/recipes-*/*/*.bb \
+chromium-browser-layer:${LAYERDIR}/dynamic-layers/chromium-browser-layer/recipes-*/*/*.bbappend \
+"
+
+LAYERDEPENDS_xilinx = "core"
+
+LAYERSERIES_COMPAT_xilinx = " gatesgarth honister hardknott"
+
+SIGGEN_EXCLUDE_SAFE_RECIPE_DEPS += " \
+  *->zocl \
+  *->cairo \
+  *->libepoxy \
+  *->gstreamer1.0-plugins-base \
+  *->gtk+ \
+  *->gtk+3 \
+  *->libglu \
+  *->libsdl \
+  *->libsdl2 \
+  *->mesa \
+  *->mesa-gl \
+  *->qemu \
+  *->virglrenderer \
+  *->xserver-xorg \
+"
+
+XILINX_RELEASE_VERSION = "v2022.1"
+
+HOSTTOOLS += "xxd"
diff --git a/meta-xilinx-core/conf/local.conf.sample b/meta-xilinx-core/conf/local.conf.sample
new file mode 100644
index 00000000..5518196e
--- /dev/null
+++ b/meta-xilinx-core/conf/local.conf.sample
@@ -0,0 +1,278 @@
+#
+# This file is your local configuration file and is where all local user settings
+# are placed. The comments in this file give some guide to the options a new user
+# to the system might want to change but pretty much any configuration option can
+# be set in this file. More adventurous users can look at local.conf.extended
+# which contains other examples of configuration which can be placed in this file
+# but new users likely won't need any of them initially.
+#
+# Lines starting with the '#' character are commented out and in some cases the
+# default values are provided as comments to show people example syntax. Enabling
+# the option is a question of removing the # character and making any change to the
+# variable as required.
+
+#
+# Machine Selection
+#
+# You need to select a specific machine to target the build with. There are a selection
+# of emulated machines available which can boot and run in the QEMU emulator:
+#
+#MACHINE ?= "microblazeel-v11.0-bs-cmp-mh-div-generic.conf"
+#MACHINE ?= "zynq-generic"
+#MACHINE ?= "zynqmp-generic"
+#MACHINE ?= "versal-generic"
+#
+# There are also the following hardware board target machines included for 
+# demonstration purposes:
+#
+#MACHINE ?= "ultra96-zynqmp"
+#
+# This sets the default machine if no other machine is selected:
+MACHINE ??= "zynqmp-generic"
+
+#
+# Where to place downloads
+#
+# During a first build the system will download many different source code tarballs
+# from various upstream projects. This can take a while, particularly if your network
+# connection is slow. These are all stored in DL_DIR. When wiping and rebuilding you
+# can preserve this directory to speed up this part of subsequent builds. This directory
+# is safe to share between multiple builds on the same machine too.
+#
+# The default is a downloads directory under TOPDIR which is the build directory.
+#
+#DL_DIR ?= "${TOPDIR}/downloads"
+
+#
+# Where to place shared-state files
+#
+# BitBake has the capability to accelerate builds based on previously built output.
+# This is done using "shared state" files which can be thought of as cache objects
+# and this option determines where those files are placed.
+#
+# You can wipe out TMPDIR leaving this directory intact and the build would regenerate
+# from these files if no changes were made to the configuration. If changes were made
+# to the configuration, only shared state files where the state was still valid would
+# be used (done using checksums).
+#
+# The default is a sstate-cache directory under TOPDIR.
+#
+#SSTATE_DIR ?= "${TOPDIR}/sstate-cache"
+
+#
+# Where to place the build output
+#
+# This option specifies where the bulk of the building work should be done and
+# where BitBake should place its temporary files and output. Keep in mind that
+# this includes the extraction and compilation of many applications and the toolchain
+# which can use Gigabytes of hard disk space.
+#
+# The default is a tmp directory under TOPDIR.
+#
+#TMPDIR = "${TOPDIR}/tmp"
+
+#
+# Default policy config
+#
+# The distribution setting controls which policy settings are used as defaults.
+# The default value is fine for general Yocto project use, at least initially.
+# Ultimately when creating custom policy, people will likely end up subclassing
+# these defaults.
+#
+DISTRO ?= "petalinux"
+
+#
+# Package Management configuration
+#
+# This variable lists which packaging formats to enable. Multiple package backends
+# can be enabled at once and the first item listed in the variable will be used
+# to generate the root filesystems.
+# Options are:
+#  - 'package_deb' for debian style deb files
+#  - 'package_ipk' for ipk files are used by opkg (a debian style embedded package manager)
+#  - 'package_rpm' for rpm style packages
+# E.g.: PACKAGE_CLASSES ?= "package_rpm package_deb package_ipk"
+# We default to rpm:
+PACKAGE_CLASSES ?= "package_rpm"
+
+#
+# SDK target architecture
+#
+# This variable specifies the architecture to build SDK items for and means
+# you can build the SDK packages for architectures other than the machine you are
+# running the build on (i.e. building i686 packages on an x86_64 host).
+# Supported values are i686, x86_64, aarch64
+#SDKMACHINE ?= "i686"
+
+#
+# Extra image configuration defaults
+#
+# The EXTRA_IMAGE_FEATURES variable allows extra packages to be added to the generated
+# images. Some of these options are added to certain image types automatically. The
+# variable can contain the following options:
+#  "dbg-pkgs"       - add -dbg packages for all installed packages
+#                     (adds symbol information for debugging/profiling)
+#  "src-pkgs"       - add -src packages for all installed packages
+#                     (adds source code for debugging)
+#  "dev-pkgs"       - add -dev packages for all installed packages
+#                     (useful if you want to develop against libs in the image)
+#  "ptest-pkgs"     - add -ptest packages for all ptest-enabled packages
+#                     (useful if you want to run the package test suites)
+#  "tools-sdk"      - add development tools (gcc, make, pkgconfig etc.)
+#  "tools-debug"    - add debugging tools (gdb, strace)
+#  "eclipse-debug"  - add Eclipse remote debugging support
+#  "tools-profile"  - add profiling tools (oprofile, lttng, valgrind)
+#  "tools-testapps" - add useful testing tools (ts_print, aplay, arecord etc.)
+#  "debug-tweaks"   - make an image suitable for development
+#                     e.g. ssh root access has a blank password
+# There are other application targets that can be used here too, see
+# meta/classes/image.bbclass and meta/classes/core-image.bbclass for more details.
+# We default to enabling the debugging tweaks.
+EXTRA_IMAGE_FEATURES ?= "debug-tweaks"
+
+#
+# Additional image features
+#
+# The following is a list of additional classes to use when building images which
+# enable extra features. Some available options which can be included in this variable
+# are:
+#   - 'buildstats' collect build statistics
+USER_CLASSES ?= "buildstats"
+
+#
+# Runtime testing of images
+#
+# The build system can test booting virtual machine images under qemu (an emulator)
+# after any root filesystems are created and run tests against those images. It can also
+# run tests against any SDK that are built. To enable this uncomment these lines.
+# See classes/test{image,sdk}.bbclass for further details.
+#IMAGE_CLASSES += "testimage testsdk"
+#TESTIMAGE_AUTO:qemuall = "1"
+
+#
+# Interactive shell configuration
+#
+# Under certain circumstances the system may need input from you and to do this it
+# can launch an interactive shell. It needs to do this since the build is
+# multithreaded and needs to be able to handle the case where more than one parallel
+# process may require the user's attention. The default is iterate over the available
+# terminal types to find one that works.
+#
+# Examples of the occasions this may happen are when resolving patches which cannot
+# be applied, to use the devshell or the kernel menuconfig
+#
+# Supported values are auto, gnome, xfce, rxvt, screen, konsole (KDE 3.x only), none
+# Note: currently, Konsole support only works for KDE 3.x due to the way
+# newer Konsole versions behave
+#OE_TERMINAL = "auto"
+# By default disable interactive patch resolution (tasks will just fail instead):
+PATCHRESOLVE = "noop"
+
+#
+# Disk Space Monitoring during the build
+#
+# Monitor the disk space during the build. If there is less than 1GB of space or less
+# than 100K inodes in any key build location (TMPDIR, DL_DIR, SSTATE_DIR), gracefully
+# shutdown the build. If there is less than 100MB or 1K inodes, perform a hard abort
+# of the build. The reason for this is that running completely out of space can corrupt
+# files and damages the build in ways which may not be easily recoverable.
+# It's necessary to monitor /tmp, if there is no space left the build will fail
+# with very exotic errors.
+BB_DISKMON_DIRS ??= "\
+    STOPTASKS,${TMPDIR},1G,100K \
+    STOPTASKS,${DL_DIR},1G,100K \
+    STOPTASKS,${SSTATE_DIR},1G,100K \
+    STOPTASKS,/tmp,100M,100K \
+    ABORT,${TMPDIR},100M,1K \
+    ABORT,${DL_DIR},100M,1K \
+    ABORT,${SSTATE_DIR},100M,1K \
+    ABORT,/tmp,10M,1K"
+
+#
+# Shared-state files from other locations
+#
+# As mentioned above, shared state files are prebuilt cache data objects which can be
+# used to accelerate build time. This variable can be used to configure the system
+# to search other mirror locations for these objects before it builds the data itself.
+#
+# This can be a filesystem directory, or a remote url such as http or ftp. These
+# would contain the sstate-cache results from previous builds (possibly from other
+# machines). This variable works like fetcher MIRRORS/PREMIRRORS and points to the
+# cache locations to check for the shared objects.
+# NOTE: if the mirror uses the same structure as SSTATE_DIR, you need to add PATH
+# at the end as shown in the examples below. This will be substituted with the
+# correct path within the directory structure.
+#SSTATE_MIRRORS ?= "\
+#file://.* http://someserver.tld/share/sstate/PATH;downloadfilename=PATH \n \
+#file://.* file:///some/local/dir/sstate/PATH"
+
+XILINX_VER_MAIN = "2021.2"
+
+# Uncomment below lines to provide path for custom xsct trim
+#
+#EXTERNAL_XSCT_TARBALL = "/proj/yocto/xsct-trim/2021.2_xsct_daily_latest"
+#VALIDATE_XSCT_CHECKSUM = '0'
+
+#
+# Yocto Project SState Mirror
+#
+# The Yocto Project has prebuilt artefacts available for its releases, you can enable
+# use of these by uncommenting the following lines. This will mean the build uses
+# the network to check for artefacts at the start of builds, which does slow it down
+# equally, it will also speed up the builds by not having to build things if they are
+# present in the cache. It assumes you can download something faster than you can build it
+# which will depend on your network.
+# Note: For this to work you also need hash-equivalence passthrough to the matching server
+#
+#BB_HASHSERVE_UPSTREAM = "typhoon.yocto.io:8687"
+#SSTATE_MIRRORS ?= "file://.* http://sstate.yoctoproject.org/3.4/PATH;downloadfilename=PATH"
+
+#
+# Qemu configuration
+#
+# By default native qemu will build with a builtin VNC server where graphical output can be
+# seen. The line below enables the SDL UI frontend too.
+PACKAGECONFIG:append:pn-qemu-system-native = " sdl"
+# By default libsdl2-native will be built, if you want to use your host's libSDL instead of 
+# the minimal libsdl built by libsdl2-native then uncomment the ASSUME_PROVIDED line below.
+#ASSUME_PROVIDED += "libsdl2-native"
+
+# You can also enable the Gtk UI frontend, which takes somewhat longer to build, but adds
+# a handy set of menus for controlling the emulator.
+#PACKAGECONFIG:append:pn-qemu-system-native = " gtk+"
+
+#Add below lines to use runqemu for ZU+ machines
+PMU_FIRMWARE_DEPLOY_DIR ??= "${DEPLOY_DIR_IMAGE}"
+PMU_FIRMWARE_IMAGE_NAME ??= "pmu-firmware-${MACHINE}"
+
+#Enable the below line to use pmu-rom.elf from a specific path
+#PMU_ROM = "/proj/yocto/pmu-rom/pmu-rom.elf"
+
+#
+# Hash Equivalence
+#
+# Enable support for automatically running a local hash equivalence server and
+# instruct bitbake to use a hash equivalence aware signature generator. Hash
+# equivalence improves reuse of sstate by detecting when a given sstate
+# artifact can be reused as equivalent, even if the current task hash doesn't
+# match the one that generated the artifact.
+#
+# A shared hash equivalent server can be set with "<HOSTNAME>:<PORT>" format
+#
+#BB_HASHSERVE = "auto"
+#BB_SIGNATURE_HANDLER = "OEEquivHash"
+
+#
+# Memory Resident Bitbake
+#
+# Bitbake's server component can stay in memory after the UI for the current command
+# has completed. This means subsequent commands can run faster since there is no need
+# for bitbake to reload cache files and so on. Number is in seconds, after which the
+# server will shut down.
+#
+#BB_SERVER_TIMEOUT = "60"
+
+# CONF_VERSION is increased each time build/conf/ changes incompatibly and is used to
+# track the version of this file when it was generated. This can safely be ignored if
+# this doesn't mean anything to you.
+CONF_VERSION = "2"
diff --git a/meta-xilinx-core/conf/machine/include/README b/meta-xilinx-core/conf/machine/include/README
new file mode 100644
index 00000000..89a25faf
--- /dev/null
+++ b/meta-xilinx-core/conf/machine/include/README
@@ -0,0 +1,34 @@
+The files in this directory make up the infrastructure that defines
+a Xilinx FPGA based system.
+
+A machine.conf is expected to require the soc-<soc>.inc or
+soc-tune-include.inc file, followed by machine-xilinx-default.inc.
+Additionally, machine-xilinx-qemu.inc should be required if the
+machine supports QEMU.  Each of the 'generic' machines include
+these files.
+
+Doing the above, will ensure that someone can use the machine.conf
+in a multiconf setting by simply adjusting DEFAULTTUNE and/or
+other basic parameters.
+
+soc-tune-include.inc   - Load the correct tune file based on DEFAULTTUNE
+
+xilinx-microblaze.inc  - Microblaze architecture settings, loaded by
+                        soc-tune-include.inc
+
+soc-versal.inc         - Set the defaults for Versal, includes soc-tune-include
+
+soc-zynq.inc           - Set the defaults for Zynq, includes soc-tune-include
+
+soc-zynqmp.inc         - Set the defaults for ZynqMP, includes soc-tune-include
+
+machine-xilinx-default - Set Xilinx FPGA wide defaults, all machines
+                         should require this file.  It defines correct
+                         PREFERRED_PROVIDER for various components, as well as
+                         other settings.
+
+machine-xilinx-qemu    - Settings required for qemu-xilinx support.
+
+xilinx-board.inc       - enabled BOARD and BOARD_VARIANT.  This allows you to
+                         use only generic machines, and simply set which BOARD
+                         and optionally BOARD_VARIANT in the local.conf.
diff --git a/meta-xilinx-core/conf/machine/include/machine-xilinx-default.inc b/meta-xilinx-core/conf/machine/include/machine-xilinx-default.inc
new file mode 100644
index 00000000..d8b1e2d9
--- /dev/null
+++ b/meta-xilinx-core/conf/machine/include/machine-xilinx-default.inc
@@ -0,0 +1,71 @@
+# Default Xilinx BSP Machine settings
+
+MACHINE_FEATURES_BACKFILL_CONSIDERED += "rtc"
+
+# File System Configuration
+IMAGE_FSTYPES ?= "tar.gz cpio cpio.gz.u-boot"
+
+# Kernel Configuration
+PREFERRED_PROVIDER_virtual/kernel ??= "linux-xlnx"
+
+# U-Boot Configuration
+PREFERRED_PROVIDER_virtual/bootloader ??= "u-boot-xlnx"
+PREFERRED_PROVIDER_virtual/boot-bin ??= "${PREFERRED_PROVIDER_virtual/bootloader}"
+
+do_image_wic[depends] += "${@' '.join('%s:do_deploy' % r for r in (d.getVar('WIC_DEPENDS') or "").split())}"
+
+UBOOT_SUFFIX ?= "img"
+UBOOT_SUFFIX:microblaze ?= "bin"
+
+UBOOT_BINARY ?= "u-boot.${UBOOT_SUFFIX}"
+UBOOT_ELF ?= "u-boot"
+UBOOT_ELF:aarch64 ?= "u-boot.elf"
+
+#Hardware accelaration
+PREFERRED_PROVIDER_virtual/libgles1:mali400 = "libmali-xlnx"
+PREFERRED_PROVIDER_virtual/libgles2:mali400 = "libmali-xlnx"
+PREFERRED_PROVIDER_virtual/egl:mali400 = "libmali-xlnx"
+PREFERRED_PROVIDER_virtual/libgl:mali400 = "mesa-gl"
+PREFERRED_PROVIDER_virtual/mesa:mali400 = "mesa-gl"
+
+XSERVER ?= " \
+        xserver-xorg \
+        xf86-input-evdev \
+        xf86-input-mouse \
+        xf86-input-keyboard \
+        xf86-video-fbdev \
+        ${XSERVER_EXT} \
+        "
+
+IMAGE_BOOT_FILES ?= "${@get_default_image_boot_files(d)}"
+
+def get_default_image_boot_files(d):
+    files = []
+
+    # kernel images
+    kerneltypes = set((d.getVar("KERNEL_IMAGETYPE") or "").split())
+    kerneltypes |= set((d.getVar("KERNEL_IMAGETYPES") or "").split())
+    for i in kerneltypes:
+        files.append(i)
+
+    # u-boot image
+    if d.getVar("UBOOT_BINARY"):
+        files.append(d.getVar("UBOOT_BINARY"))
+
+    # device trees (device-tree only), these are first as they are likely desired over the kernel ones
+    if "device-tree" in (d.getVar("MACHINE_ESSENTIAL_EXTRA_RDEPENDS") or ""):
+        files.append("devicetree/*.dtb")
+
+
+    # device trees (kernel only)
+    if d.getVar("KERNEL_DEVICETREE"):
+        dtbs = d.getVar("KERNEL_DEVICETREE").split(" ")
+        dtbs = [os.path.basename(d) for d in dtbs]
+        for dtb in dtbs:
+            files.append(dtb)
+
+    return " ".join(files)
+
+XSERVER_EXT ?= ""
+
+FPGA_MNGR_RECONFIG_ENABLE ?= "1"
diff --git a/meta-xilinx-core/conf/machine/include/machine-xilinx-qemu.inc b/meta-xilinx-core/conf/machine/include/machine-xilinx-qemu.inc
new file mode 100644
index 00000000..c2093ca6
--- /dev/null
+++ b/meta-xilinx-core/conf/machine/include/machine-xilinx-qemu.inc
@@ -0,0 +1,55 @@
+# This include is used to setup default QEMU and qemuboot config for meta-xilinx
+# machines.
+
+# Use the xilinx specific version for these users
+IMAGE_CLASSES += "qemuboot-xilinx"
+
+# depend on qemu-helper-native, which will depend on QEMU
+EXTRA_IMAGEDEPENDS += "qemu-helper-native"
+
+PREFERRED_PROVIDER_qemu-helper-native = "qemu-xilinx-helper-native"
+PREFERRED_PROVIDER_qemu = "qemu-xilinx"
+PREFERRED_PROVIDER_qemu-native = "qemu-xilinx-native"
+PREFERRED_PROVIDER_nativesdk-qemu = "nativesdk-qemu-xilinx"
+
+def qemu_default_dtb(d):
+    if d.getVar("IMAGE_BOOT_FILES", True):
+        dtbs = d.getVar("IMAGE_BOOT_FILES", True).split(" ")
+        # IMAGE_BOOT_FILES has extra renaming info in the format '<source>;<target>'
+        # Note: Wildcard sources work here only because runqemu expands them at run time
+        dtbs = [f.split(";")[0] for f in dtbs]
+        dtbs = [f for f in dtbs if f.endswith(".dtb")]
+        if len(dtbs) != 0:
+            return dtbs[0]
+    return ""
+
+def qemu_default_serial(d):
+    if d.getVar("SERIAL_CONSOLES", True):
+        first_console = d.getVar("SERIAL_CONSOLES", True).split(" ")[0]
+        speed, console = first_console.split(";", 1)
+        # zynqmp uses earlycon and stdout (in dtb)
+        if "zynqmp" in d.getVar("MACHINEOVERRIDES", True).split(":"):
+            return ""
+        return "console=%s,%s earlyprintk" % (console, speed)
+    return ""
+
+def qemu_target_binary(d):
+    ta = d.getVar("TARGET_ARCH", True)
+    if ta == "microblazeeb":
+        ta = "microblaze"
+    elif ta == "arm":
+        ta = "aarch64"
+    return "qemu-system-%s" % ta
+
+def qemu_zynqmp_unhalt(d, multiarch):
+    if multiarch:
+        return "-global xlnx,zynqmp-boot.cpu-num=0 -global xlnx,zynqmp-boot.use-pmufw=true"
+    return "-device loader,addr=0xfd1a0104,data=0x8000000e,data-len=4 -device loader,addr=0xfd1a0104,data=0x8000000e,data-len=4"
+
+# For qemuboot, default setup across all machines in meta-xilinx
+QB_SYSTEM_NAME:aarch64 ?= "${@qemu_target_binary(d)}-multiarch"
+QB_SYSTEM_NAME ?= "${@qemu_target_binary(d)}"
+QB_DEFAULT_FSTYPE ?= "cpio"
+QB_DTB ?= "${@qemu_default_dtb(d)}"
+QB_KERNEL_CMDLINE_APPEND ?= "${@qemu_default_serial(d)}"
+
diff --git a/meta-xilinx-core/conf/machine/include/soc-tune-include.inc b/meta-xilinx-core/conf/machine/include/soc-tune-include.inc
new file mode 100644
index 00000000..539879d4
--- /dev/null
+++ b/meta-xilinx-core/conf/machine/include/soc-tune-include.inc
@@ -0,0 +1,16 @@
+DEFAULTTUNE ??= "armv8a"
+
+# Unfortunately various tunefiles don't include each other, so create
+# a list of things to require based on the DEFAULTTUNE setting.
+TUNEFILE[cortexr5] = "conf/machine/include/arm/armv7r/tune-cortexr5.inc"
+TUNEFILE[cortexa9thf-neon] = "conf/machine/include/arm/armv7a/tune-cortexa9.inc"
+TUNEFILE[armv8a] = "conf/machine/include/arm/arch-armv8a.inc"
+TUNEFILE[cortexa53] = "conf/machine/include/arm/armv8a/tune-cortexa53.inc"
+TUNEFILE[cortexa72] = "conf/machine/include/arm/armv8a/tune-cortexa72.inc"
+TUNEFILE[cortexa72-cortexa53] = "conf/machine/include/arm/armv8a/tune-cortexa72-cortexa53.inc"
+TUNEFILE[microblaze] = "conf/machine/include/xilinx-microblaze.inc"
+
+# Default to arch-armv8a.inc
+TUNEFILE = "${@ d.getVarFlag('TUNEFILE', d.getVar('DEFAULTTUNE')) or 'conf/machine/include/arm/arch-armv8a.inc'}"
+
+require ${TUNEFILE}
diff --git a/meta-xilinx-core/conf/machine/include/soc-versal.inc b/meta-xilinx-core/conf/machine/include/soc-versal.inc
new file mode 100644
index 00000000..f2a033ad
--- /dev/null
+++ b/meta-xilinx-core/conf/machine/include/soc-versal.inc
@@ -0,0 +1,35 @@
+DEFAULTTUNE ?= "cortexa72-cortexa53"
+SOC_FAMILY ?= "versal"
+
+# Available SOC_VARIANT's for versal:
+# "prime"    - Versal deafult Prime Devices
+# "premium"  - Versal Premium Devices
+# "hbm"      - Versal HMB Devices
+# "ai-core"  - Versal AI-core Devices
+# "ai-edge"  - Versal AI-Edge Devices
+
+SOC_VARIANT ?= "prime"
+
+require xilinx-soc-family.inc
+require soc-tune-include.inc
+
+# Linux Configuration
+KERNEL_IMAGETYPE ?= "Image"
+
+WIC_DEPENDS ?= "virtual/kernel virtual/bootloader virtual/boot-bin virtual/arm-trusted-firmware"
+
+UBOOT_ELF ?= "u-boot.elf"
+
+# Default, if multiconfig is off, call plm/psm-firmware directly, otherwise call the versal-fw multiconfig version
+# The Linux compatible plm/psm-firmware though requires meta-xilinx-tools
+PLM_DEPENDS ?= "${@bb.utils.contains('BBMULTICONFIG', 'versal-fw', '', 'plm-firmware:do_deploy', d)}"
+PLM_MCDEPENDS ?= "${@bb.utils.contains('BBMULTICONFIG', 'versal-fw', 'mc::versal-fw:plm-firmware:do_deploy', '', d)}"
+PLM_DEPLOY_DIR ?= "${@bb.utils.contains('BBMULTICONFIG', 'versal-fw', '${TOPDIR}/tmp-microblaze-versal-fw/deploy/images/${MACHINE}', '${DEPLOY_DIR_IMAGE}', d)}"
+PLM_DEPLOY_DIR[vardepsexclude] += "TOPDIR"
+PLM_IMAGE_NAME ?= "${@bb.utils.contains('BBMULTICONFIG', 'versal-fw', 'plm-versal-mb', 'plm-${MACHINE}', d)}"
+
+PSM_DEPENDS ?= "${@bb.utils.contains('BBMULTICONFIG', 'versal-fw', '', 'psm-firmware:do_deploy', d)}"
+PSM_MCDEPENDS ?= "${@bb.utils.contains('BBMULTICONFIG', 'versal-fw', 'mc::versal-fw:psm-firmware:do_deploy', '', d)}"
+PSM_FIRMWARE_DEPLOY_DIR ?= "${@bb.utils.contains('BBMULTICONFIG', 'versal-fw', '${TOPDIR}/tmp-microblaze-versal-fw/deploy/images/${MACHINE}', '${DEPLOY_DIR_IMAGE}', d)}"
+PSM_DEPLOY_DIR[vardepsexclude] += "TOPDIR"
+PSM_FIRMWARE_IMAGE_NAME ?= "${@bb.utils.contains('BBMULTICONFIG', 'versal-fw', 'psm-firmware-versal-mb', 'psm-firmware-${MACHINE}', d)}"
diff --git a/meta-xilinx-core/conf/machine/include/soc-zynq.inc b/meta-xilinx-core/conf/machine/include/soc-zynq.inc
new file mode 100644
index 00000000..88d48a92
--- /dev/null
+++ b/meta-xilinx-core/conf/machine/include/soc-zynq.inc
@@ -0,0 +1,32 @@
+DEFAULTTUNE ?= "cortexa9thf-neon"
+SOC_FAMILY ?= "zynq"
+
+# Available SOC_VARIANT's for zynq:
+# 7zs - Zynq-7000 Single A9 Core
+# 7z  - Zynq-7000 Dual A9 Core
+
+SOC_VARIANT ?= "7z"
+
+require xilinx-soc-family.inc
+require soc-tune-include.inc
+
+# Linux Configuration
+KERNEL_IMAGETYPE ?= "uImage"
+KERNEL_IMAGETYPES += "zImage"
+
+# Set default load address.
+# Override with KERNEL_EXTRA_ARGS_<board> += "..." in machine file if required
+KERNEL_EXTRA_ARGS:zynq += "UIMAGE_LOADADDR=0x8000"
+
+# WIC Specific dependencies
+WIC_DEPENDS ?= "virtual/kernel virtual/bootloader virtual/boot-bin"
+
+UBOOT_ELF ?= "u-boot.elf"
+
+# Default, if multiconfig is off, the fsbl is in the regular deploydir, otherwise
+# it is located under a multiconfig specific deploydir
+FSBL_DEPENDS ?= "${@bb.utils.contains('BBMULTICONFIG', 'fsbl-fw', '', 'fsbl-firmware:do_deploy', d)}"
+FSBL_MCDEPENDS ?= "${@bb.utils.contains('BBMULTICONFIG', 'fsbl-fw', 'mc::fsbl-fw:fsbl-firmware:do_deploy', '', d)}"
+FSBL_DEPLOY_DIR ?= "${@bb.utils.contains('BBMULTICONFIG', 'fsbl-fw', '${TOPDIR}/tmp-fsbl-fw/deploy/images/${MACHINE}', '${DEPLOY_DIR_IMAGE}', d)}"
+FSBL_DEPLOY_DIR[vardepsexclude] += "TOPDIR"
+FSBL_IMAGE_NAME ?= "fsbl-${MACHINE}"
diff --git a/meta-xilinx-core/conf/machine/include/soc-zynqmp.inc b/meta-xilinx-core/conf/machine/include/soc-zynqmp.inc
new file mode 100644
index 00000000..e32fd617
--- /dev/null
+++ b/meta-xilinx-core/conf/machine/include/soc-zynqmp.inc
@@ -0,0 +1,51 @@
+DEFAULTTUNE ?= "cortexa72-cortexa53"
+SOC_FAMILY ?= "zynqmp"
+
+# Available SOC_VARIANT's for zynqmp:
+# "cg" - Zynq UltraScale+  CG Devices
+# "eg" - Zynq UltraScale+  EG Devices
+# "ev" - Zynq UltraScale+  EV Devices
+# "dr" - Zynq UltraScale+  DR Devices
+
+SOC_VARIANT ?= "eg"
+
+require xilinx-soc-family.inc
+
+GRAPHICSOVERRIDES = ""
+GRAPHICSOVERRIDES:zynqmp-eg = "mali400:"
+GRAPHICSOVERRIDES:zynqmp-ev = "mali400:vcu:"
+
+MACHINEOVERRIDES =. "${GRAPHICSOVERRIDES}"
+
+require soc-tune-include.inc
+
+# Linux Configuration
+KERNEL_IMAGETYPE ?= "Image"
+
+# Support multilib on zynqmp
+DEFAULTTUNE:virtclass-multilib-lib32 ?= "armv7vethf-neon-vfpv4"
+
+WIC_DEPENDS ?= "virtual/kernel virtual/bootloader virtual/boot-bin virtual/arm-trusted-firmware"
+
+UBOOT_SUFFIX ?= "bin"
+
+XSERVER_EXT:zynqmp ?= "xf86-video-armsoc"
+
+# Default PMU ROM
+PMU_ROM ?= "${DEPLOY_DIR_IMAGE}/pmu-rom.elf"
+
+# Default, if multiconfig is off, call pmu-firmware directly, otherwise call the zynqmp-pmufw multiconfig version
+# The Linux compatible pmu-firmware though requires meta-xilinx-tools
+PMU_DEPENDS ?= "${@bb.utils.contains('BBMULTICONFIG', 'zynqmp-pmufw', '', 'pmu-firmware:do_deploy', d)}"
+PMU_MCDEPENDS ?= "${@bb.utils.contains('BBMULTICONFIG', 'zynqmp-pmufw', 'mc::zynqmp-pmufw:pmu-firmware:do_deploy', '', d)}"
+PMU_FIRMWARE_DEPLOY_DIR ?= "${@bb.utils.contains('BBMULTICONFIG', 'zynqmp-pmufw', '${TOPDIR}/tmp-microblaze-zynqmp-pmufw/deploy/images/${MACHINE}', '${DEPLOY_DIR_IMAGE}', d)}"
+PMU_FIRMWARE_DEPLOY_DIR[vardepsexclude] += "TOPDIR"
+PMU_FIRMWARE_IMAGE_NAME ?= "${@bb.utils.contains('BBMULTICONFIG', 'zynqmp-pmufw', 'pmu-firmware-zynqmp-pmu', 'pmu-firmware-${MACHINE}', d)}"
+
+# Default, if multiconfig is off, the fsbl is in the regular deploydir, otherwise
+# it is located under a multiconfig specific deploydir
+FSBL_DEPENDS ?= "${@bb.utils.contains('BBMULTICONFIG', 'fsbl-fw', '', 'fsbl-firmware:do_deploy', d)}"
+FSBL_MCDEPENDS ?= "${@bb.utils.contains('BBMULTICONFIG', 'fsbl-fw', 'mc::fsbl-fw:fsbl-firmware:do_deploy', '', d)}"
+FSBL_DEPLOY_DIR ?= "${@bb.utils.contains('BBMULTICONFIG', 'fsbl-fw', '${TOPDIR}/tmp-fsbl-fw/deploy/images/${MACHINE}', '${DEPLOY_DIR_IMAGE}', d)}"
+FSBL_DEPLOY_DIR[vardepsexclude] += "TOPDIR"
+FSBL_IMAGE_NAME ?= "fsbl-${MACHINE}"
diff --git a/meta-xilinx-core/conf/machine/include/xilinx-board.inc b/meta-xilinx-core/conf/machine/include/xilinx-board.inc
new file mode 100644
index 00000000..18b04742
--- /dev/null
+++ b/meta-xilinx-core/conf/machine/include/xilinx-board.inc
@@ -0,0 +1,12 @@
+BOARD ??= ""
+BOARD_VARIANT ??= ""
+
+MACHINEOVERRIDES .= "${@['', ':${BOARD}']['${BOARD}' != '']}"
+MACHINEOVERRIDES .= "${@['', ':${BOARD}-${BOARD_VARIANT}']['${BOARD_VARIANT}' != '']}"
+
+
+BOARD_ARCH ?= "${@['${BOARD}', '${MACHINE_ARCH}'][d.getVar('BOARD')=='']}"
+BOARDVARIANT_ARCH ?= "${@['${BOARD}-${BOARD_VARIANT}','${BOARD_ARCH}'][d.getVar('BOARD_VARIANT')=='']}"
+
+PACKAGE_EXTRA_ARCHS:append = "${@['', ' ${BOARD_ARCH}'][d.getVar('BOARDVARIANT_ARCH') != d.getVar('MACHINE_ARCH')]}"
+PACKAGE_EXTRA_ARCHS:append = "${@['', ' ${BOARDVARIANT_ARCH}'][d.getVar('BOARDVARIANT_ARCH') != d.getVar('BOARD_ARCH')]}"
diff --git a/meta-xilinx-core/conf/machine/include/xilinx-microblaze.inc b/meta-xilinx-core/conf/machine/include/xilinx-microblaze.inc
new file mode 100644
index 00000000..76d77cd1
--- /dev/null
+++ b/meta-xilinx-core/conf/machine/include/xilinx-microblaze.inc
@@ -0,0 +1,17 @@
+# To avoid the require overriding previous defaults we use the override to make this the default
+TUNE_FEATURES_save := "${TUNE_FEATURES:tune-microblaze}"
+
+require conf/machine/include/microblaze/tune-microblaze.inc
+
+# Reset the default value back to what it was previously set to...
+TUNE_FEATURES:tune-microblaze := "${TUNE_FEATURES_save}"
+
+# Various microblaze architecture defaults
+
+# microblaze does not get on with pie for reasons not looked into as yet
+GCCPIE:microblaze = ""
+GLIBCPIE:microblaze = ""
+SECURITY_CFLAGS:microblaze = ""
+SECURITY_LDFLAGS:microblaze = ""
+# Microblaze does not support gnu hash style
+LINKER_HASH_STYLE:microblaze = "sysv"
diff --git a/meta-xilinx-core/conf/machine/include/xilinx-soc-family.inc b/meta-xilinx-core/conf/machine/include/xilinx-soc-family.inc
new file mode 100644
index 00000000..dd54f5c6
--- /dev/null
+++ b/meta-xilinx-core/conf/machine/include/xilinx-soc-family.inc
@@ -0,0 +1,10 @@
+SOC_VARIANT ??= ""
+MACHINEOVERRIDES =. "${@['', '${SOC_FAMILY}-${SOC_VARIANT}:']['${SOC_VARIANT}' != '']}"
+
+require conf/machine/include/soc-family.inc
+
+SOC_FAMILY_ARCH ?= "${SOC_FAMILY}"
+SOC_VARIANT_ARCH ?= "${@['${SOC_FAMILY}-${SOC_VARIANT}','${SOC_FAMILY}'][d.getVar('SOC_VARIANT')=='']}"
+
+PACKAGE_EXTRA_ARCHS:append = " ${SOC_FAMILY_ARCH}"
+PACKAGE_EXTRA_ARCHS:append = "${@['', ' ${SOC_VARIANT_ARCH}'][d.getVar('SOC_VARIANT_ARCH') != d.getVar('SOC_FAMILY_ARCH')]}"
diff --git a/meta-xilinx-core/conf/machine/microblaze-generic.conf b/meta-xilinx-core/conf/machine/microblaze-generic.conf
new file mode 100644
index 00000000..6dfa9997
--- /dev/null
+++ b/meta-xilinx-core/conf/machine/microblaze-generic.conf
@@ -0,0 +1,32 @@
+#@TYPE: Machine
+#@NAME: microblaze-generic
+#@DESCRIPTION: Generic microblaze defaults to little-endian v11.0 barrel-shift pattern-compare reorder divide-hard multiple-high support
+
+# Set the default for a modern full feature microblaze...
+TUNE_FEATURES:tune-microblaze ?= "microblaze v11.0 barrel-shift pattern-compare reorder divide-hard multiply-high"
+DEFAULTTUNE ?= "microblaze"
+
+require conf/machine/include/soc-tune-include.inc
+require conf/machine/include/machine-xilinx-default.inc
+require conf/machine/include/machine-xilinx-qemu.inc
+require conf/machine/include/xilinx-board.inc
+
+# The default MACHINE_ARCH is dynmic for microblaze, since the architecture is not fixed
+# Based on core bitbake.conf
+DEF_MACHINE_ARCH = "${@[d.getVar('TUNE_PKGARCH'), d.getVar('MACHINE')][bool(d.getVar('MACHINE'))].replace('-', '_')}"
+# Enable a dynamic machine_arch
+MB_MACHINE_ARCH = "${@[d.getVar('TUNE_PKGARCH'), d.getVar('TUNE_PKGARCH') + '-generic'][bool(d.getVar('MACHINE'))].replace('-', '_')}"
+
+MACHINE_ARCH = "${@['${MB_MACHINE_ARCH}', '${DEF_MACHINE_ARCH}']['microblaze-generic' != "${MACHINE}"]}"
+
+MACHINE_FEATURES = ""
+
+KERNEL_IMAGETYPE = "linux.bin.ub"
+KERNEL_IMAGETYPES = ""
+
+SERIAL_CONSOLES ?= "115200;ttyS0"
+
+EXTRA_IMAGEDEPENDS += "libyaml-native python3-cython-native python3-pyyaml-native"
+
+UBOOT_MACHINE ?= "microblaze-generic_defconfig"
+UBOOT_INITIAL_ENV = ""
diff --git a/meta-xilinx-core/conf/machine/versal-generic.conf b/meta-xilinx-core/conf/machine/versal-generic.conf
new file mode 100644
index 00000000..2b0cd495
--- /dev/null
+++ b/meta-xilinx-core/conf/machine/versal-generic.conf
@@ -0,0 +1,86 @@
+#@TYPE: Machine
+#@NAME: Generic versal
+#@DESCRIPTION: versal devices
+
+require conf/machine/include/soc-versal.inc
+require conf/machine/include/machine-xilinx-default.inc
+require conf/machine/include/machine-xilinx-qemu.inc
+require conf/machine/include/xilinx-board.inc
+
+MACHINE_FEATURES += "rtc ext2 ext3 vfat usbhost"
+
+EXTRA_IMAGEDEPENDS += "libyaml-native python3-cython-native python3-pyyaml-native"
+
+UBOOT_MACHINE ?= "xilinx_versal_virt_defconfig"
+
+SERIAL_CONSOLES ?= "115200;ttyAMA0"
+
+MACHINE_ESSENTIAL_EXTRA_RDEPENDS += "device-tree"
+
+HDF_MACHINE = "vck190-versal"
+
+# Default SD image build onfiguration, use qemu-sd to pad
+IMAGE_CLASSES += "image-types-xilinx-qemu"
+IMAGE_FSTYPES += "wic.qemu-sd"
+WKS_FILES ?= "sdimage-bootpart.wks"
+
+EXTRA_IMAGEDEPENDS += " \
+   arm-trusted-firmware \
+   virtual/boot-bin \
+   virtual/bootloader \
+   virtual/psm-firmware \
+   virtual/plm \
+   u-boot-zynq-scr \
+   qemu-devicetrees \
+   virtual/cdo \
+"
+
+IMAGE_BOOT_FILES += " \
+    boot.bin \
+    ${@bb.utils.contains('PREFERRED_PROVIDER_virtual/dtb', 'device-tree', 'system.dtb', '', d)} \
+    Image \
+    boot.scr \
+"
+
+
+# This machine has a QEMU model, runqemu setup:
+QB_MEM = "-m 8G"
+QB_DEFAULT_KERNEL = "none"
+QB_NETWORK_DEVICE = ""
+QB_KERNEL_CMDLINE_APPEND ?= ""
+QB_NET = "none"
+
+QB_DEFAULT_FSTYPE:qemuboot-xilinx = "wic.qemu-sd"
+QB_OPT_APPEND:append:qemuboot-xilinx = " -boot mode=5"
+QB_ROOTFS_OPT:qemuboot-xilinx = " -drive if=sd,index=1,file=@ROOTFS@,format=raw"
+
+# Use booti 80000 6000000 4000000 to launch
+QB_OPT_APPEND ?= " -serial null -serial null -serial mon:stdio -display none"
+
+QEMU_HW_DTB_PATH = "${DEPLOY_DIR_IMAGE}/qemu-hw-devicetrees/multiarch"
+QEMU_HW_DTB_PS ?="${QEMU_HW_DTB_PATH}/board-versal-ps-vck190.dtb"
+QEMU_HW_DTB_PMC ?="${QEMU_HW_DTB_PATH}/board-versal-pmc-vc-p-a2197-00.dtb"
+
+QEMU_HW_DTB_PS_vp1202-versal = "${QEMU_HW_DTB_PATH}/board-versal-vp1202-ps-virt.dtb"
+QEMU_HW_DTB_PMC_vp1202-versal = "${QEMU_HW_DTB_PATH}/board-versal-vp1202-pmc-virt.dtb"
+
+QB_OPT_APPEND:append:qemuboot-xilinx = " \
+    -hw-dtb ${QEMU_HW_DTB_PS} \
+    -display none \
+    -net nic -net user,tftp=${DEPLOY_DIR_IMAGE} \
+    "
+
+# PLM instance args
+QB_PLM_OPT = " \
+    -M microblaze-fdt \
+    -device loader,file=${DEPLOY_DIR_IMAGE}/BOOT-${MACHINE}_bh.bin,addr=0xF201E000,force-raw  \
+    -device loader,addr=0xf0000000,data=0xba020004,data-len=4 \
+    -device loader,addr=0xf0000004,data=0xb800fffc,data-len=4 \
+    -device loader,file=${DEPLOY_DIR_IMAGE}/pmc_cdo.bin,addr=0xf2000000,force-raw \
+    -device loader,file=${DEPLOY_DIR_IMAGE}/plm-${MACHINE}.elf,cpu-num=1 \
+    -device loader,addr=0xF1110624,data=0x0,data-len=4 \
+    -device loader,addr=0xF1110620,data=0x1,data-len=4 \
+    -hw-dtb ${QEMU_HW_DTB_PMC} \
+    -display none \
+    "
+QB_OPT_APPEND:append:qemuboot-xilinx = " -plm-args '${QB_PLM_OPT}'"
diff --git a/meta-xilinx-core/conf/machine/zynq-generic.conf b/meta-xilinx-core/conf/machine/zynq-generic.conf
new file mode 100644
index 00000000..2fc6d27b
--- /dev/null
+++ b/meta-xilinx-core/conf/machine/zynq-generic.conf
@@ -0,0 +1,41 @@
+#@TYPE: Machine
+#@NAME: Generic Zynq
+#@DESCRIPTION: Generic Zynq Device
+
+require conf/machine/include/soc-zynq.inc
+require conf/machine/include/machine-xilinx-default.inc
+require conf/machine/include/machine-xilinx-qemu.inc
+require conf/machine/include/xilinx-board.inc
+
+MACHINE_FEATURES += "rtc ext2 ext3 vfat usbhost usbgadget"
+
+EXTRA_IMAGEDEPENDS += "libyaml-native python3-cython-native python3-pyyaml-native"
+
+UBOOT_MACHINE ?= "xilinx_zynq_virt_defconfig"
+
+SERIAL_CONSOLES ?= "115200;ttyPS0"
+
+MACHINE_ESSENTIAL_EXTRA_RDEPENDS += "device-tree"
+
+HDF_MACHINE = "zc702-zynq7"
+
+QB_MEM = "-m 1024"
+QB_NETWORK_DEVICE = "-net nic,netdev=eth0 -netdev user,id=eth0,tftp=/tftpboot -net nic"
+QB_DEFAULT_KERNEL:qemuboot-xilinx = "zImage"
+
+QB_SYSTEM_NAME ?= "${@qemu_target_binary(d)}"
+QB_DEFAULT_FSTYPE = "cpio.gz.u-boot"
+QB_DTB = "system.dtb"
+QB_ROOTFS_OPT:qemuboot-xilinx = " -drive if=sd,index=1,file=@ROOTFS@,format=raw"
+
+# Replicate BootROM like behaviour, having loaded SPL and PMU(ROM+FW)
+QB_OPT_APPEND = " \
+        -nographic -serial null -serial mon:stdio \
+        -initrd ${DEPLOY_DIR_IMAGE}/@ROOTFS@ \
+        -gdb tcp::9000 \
+        -device loader,addr=0xf8000008,data=0xDF0D,data-len=4 \
+        -device loader,addr=0xf8000140,data=0x00500801,data-len=4 \
+        -device loader,addr=0xf800012c,data=0x1ed044d,data-len=4 \
+        -device loader,addr=0xf8000108,data=0x0001e008,data-len=4 \
+        -device loader,addr=0xF8000910,data=0xF,data-len=0x4 \
+        "
diff --git a/meta-xilinx-core/conf/machine/zynqmp-generic.conf b/meta-xilinx-core/conf/machine/zynqmp-generic.conf
new file mode 100644
index 00000000..eb9d4bc4
--- /dev/null
+++ b/meta-xilinx-core/conf/machine/zynqmp-generic.conf
@@ -0,0 +1,85 @@
+#@TYPE: Machine
+#@NAME: Generic zynqmp
+#@DESCRIPTION: zynqmp devices
+
+# CG is the lowest common demoninator, so use this by default
+SOC_VARIANT ?= "cg"
+
+require conf/machine/include/soc-zynqmp.inc
+require conf/machine/include/machine-xilinx-default.inc
+require conf/machine/include/machine-xilinx-qemu.inc
+require conf/machine/include/xilinx-board.inc
+
+# Machine features must result in a superset
+# Basic features:
+MACHINE_FEATURES += "rtc ext2 ext3 vfat usbhost"
+# Ultra96 features:
+MACHINE_FEATURES += " usbgadget wifi bluetooth"
+
+EXTRA_IMAGEDEPENDS += "libyaml-native python3-cython-native python3-pyyaml-native"
+
+UBOOT_MACHINE ?= "xilinx_zynqmp_virt_defconfig"
+SPL_BINARY ?= "spl/boot.bin"
+
+# Default SD image build onfiguration, use qemu-sd to pad
+IMAGE_CLASSES += "image-types-xilinx-qemu"
+IMAGE_FSTYPES += "wic.qemu-sd"
+WKS_FILES ?= "sdimage-bootpart.wks"
+
+SERIAL_CONSOLES ?= "115200;ttyPS0"
+
+MACHINE_ESSENTIAL_EXTRA_RDEPENDS += "device-tree"
+
+# We need a generic one that works with QEMU...
+HDF_MACHINE = "zcu102-zynqmp"
+
+EXTRA_IMAGEDEPENDS += " \
+                u-boot-zynq-uenv \
+                arm-trusted-firmware \
+                qemu-devicetrees \
+                virtual/boot-bin \
+                virtual/bootloader \
+                u-boot-zynq-scr \
+                "
+
+IMAGE_BOOT_FILES += " \
+                uEnv.txt \
+                atf-uboot.ub \
+                ${@bb.utils.contains('PREFERRED_PROVIDER_virtual/dtb', 'device-tree', 'system.dtb', '', d)} \
+                boot.scr \
+                "
+
+# This machine has a QEMU model, runqemu setup:
+QB_MEM = "-m 4096"
+QB_OPT_APPEND ?= "-nographic -serial mon:stdio -serial null"
+QB_NETWORK_DEVICE = "-net nic -net nic -net nic -net nic,netdev=net0,macaddr=@MAC@"
+
+# Replicate BootROM like behaviour, having loaded SPL and PMU(ROM+FW)
+QB_OPT_APPEND:append:qemuboot-xilinx = " \
+                -hw-dtb ${DEPLOY_DIR_IMAGE}/qemu-hw-devicetrees/multiarch/zcu102-arm.dtb \
+                ${@qemu_zynqmp_unhalt(d, True)} \
+                -device loader,file=${DEPLOY_DIR_IMAGE}/arm-trusted-firmware.elf,cpu-num=0 \
+                -device loader,file=${DEPLOY_DIR_IMAGE}/u-boot.elf \
+                -device loader,file=${DEPLOY_DIR_IMAGE}/system.dtb,addr=0x100000 \
+                "
+
+# Attach the rootfs disk image to the second SD interface of QEMU (which is SD0)
+QB_DEFAULT_FSTYPE:qemuboot-xilinx = "wic.qemu-sd"
+QB_OPT_APPEND:append:qemuboot-xilinx = " -boot mode=5"
+QB_ROOTFS_OPT:qemuboot-xilinx = " -drive if=sd,index=1,file=@ROOTFS@,format=raw"
+
+QB_PMU_OPT = " \
+                -M microblaze-fdt \
+                -display none \
+                -hw-dtb ${DEPLOY_DIR_IMAGE}/qemu-hw-devicetrees/multiarch/zynqmp-pmu.dtb \
+                -kernel ${PMU_ROM} \
+                -device loader,file=${PMU_FIRMWARE_DEPLOY_DIR}/${PMU_FIRMWARE_IMAGE_NAME}.elf \
+                -device loader,addr=0xfd1a0074,data=0x1011003,data-len=4 \
+                -device loader,addr=0xfd1a007C,data=0x1010f03,data-len=4 \
+                "
+QB_OPT_APPEND:append:qemuboot-xilinx = " -pmu-args '${QB_PMU_OPT}'"
+
+do_write_qemuboot_conf[depends] += "u-boot-zynq-uenv:do_deploy"
+
+# Board specific overrides
+include conf/machine/include/board/ultra96.inc
diff --git a/meta-xilinx-core/dynamic-layers/chromium-browser-layer/recipes-browser/chromium/chromium-x11_%.bbappend b/meta-xilinx-core/dynamic-layers/chromium-browser-layer/recipes-browser/chromium/chromium-x11_%.bbappend
new file mode 100644
index 00000000..bb792de2
--- /dev/null
+++ b/meta-xilinx-core/dynamic-layers/chromium-browser-layer/recipes-browser/chromium/chromium-x11_%.bbappend
@@ -0,0 +1,2 @@
+# Has a dependency on libmali
+PACKAGE_ARCH:mali400 = "${SOC_VARIANT_ARCH}"
diff --git a/meta-xilinx-core/dynamic-layers/openembedded-layer/recipes-core/opencl-headers/opencl-headers_%.bbappend b/meta-xilinx-core/dynamic-layers/openembedded-layer/recipes-core/opencl-headers/opencl-headers_%.bbappend
new file mode 100644
index 00000000..b90c754d
--- /dev/null
+++ b/meta-xilinx-core/dynamic-layers/openembedded-layer/recipes-core/opencl-headers/opencl-headers_%.bbappend
@@ -0,0 +1 @@
+ALLOW_EMPTY:${PN} = "1"
diff --git a/meta-xilinx-core/dynamic-layers/openembedded-layer/recipes-graphics/xorg-driver/xf86-video-armsoc/0001-armsoc_driver.c-Bypass-the-exa-layer-to-free-the-roo.patch b/meta-xilinx-core/dynamic-layers/openembedded-layer/recipes-graphics/xorg-driver/xf86-video-armsoc/0001-armsoc_driver.c-Bypass-the-exa-layer-to-free-the-roo.patch
new file mode 100644
index 00000000..2e024794
--- /dev/null
+++ b/meta-xilinx-core/dynamic-layers/openembedded-layer/recipes-graphics/xorg-driver/xf86-video-armsoc/0001-armsoc_driver.c-Bypass-the-exa-layer-to-free-the-roo.patch
@@ -0,0 +1,33 @@
+From 497de8b16265468cacad880f4a371756924ae0c1 Mon Sep 17 00:00:00 2001
+From: Madhurkiran Harikrishnan <madhurkiran.harikrishnan@xilinx.com>
+Date: Tue, 14 Apr 2020 15:25:13 -0700
+Subject: [xf86-video-armsoc][PATCH v2] armsoc_driver.c: Bypass the exa layer
+ to free the root pixmap
+
+Since the root pixmap was allocated through miCreateScreenResources,
+the exa layer is not aware of the pixmap resulting in the assertion
+to fail. Instead, we can directly invoke fbDestroyPixmap, thereby
+freeing the pixmap and avoiding a memory leak.
+
+Signed-off-by: Madhurkiran Harikrishnan <madhurkiran.harikrishnan@xilinx.com>
+---
+ src/armsoc_driver.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/src/armsoc_driver.c b/src/armsoc_driver.c
+index 3ace3c7..a4a1ba3 100644
+--- a/src/armsoc_driver.c
++++ b/src/armsoc_driver.c
+@@ -1259,7 +1259,8 @@ ARMSOCCloseScreen(CLOSE_SCREEN_ARGS_DECL)
+         * we do it here, before calling the CloseScreen chain which would just free pScreen->devPrivate in fbCloseScreen()
+         */
+        if (pScreen->devPrivate) {
+-               (void) (*pScreen->DestroyPixmap)(pScreen->devPrivate);
++               fbDestroyPixmap (pScreen->devPrivate);
++               armsoc_bo_unreference(pARMSOC->scanout);
+                pScreen->devPrivate = NULL;
+        }
+ 
+-- 
+2.7.4
+
diff --git a/meta-xilinx-core/dynamic-layers/openembedded-layer/recipes-graphics/xorg-driver/xf86-video-armsoc/0001-src-drmmode_xilinx-Add-the-dumb-gem-support-for-Xili.patch b/meta-xilinx-core/dynamic-layers/openembedded-layer/recipes-graphics/xorg-driver/xf86-video-armsoc/0001-src-drmmode_xilinx-Add-the-dumb-gem-support-for-Xili.patch
new file mode 100644
index 00000000..bf2169ee
--- /dev/null
+++ b/meta-xilinx-core/dynamic-layers/openembedded-layer/recipes-graphics/xorg-driver/xf86-video-armsoc/0001-src-drmmode_xilinx-Add-the-dumb-gem-support-for-Xili.patch
@@ -0,0 +1,141 @@
+From 630a8ea035fe2f075f6ea7f4bad0928f5b541c80 Mon Sep 17 00:00:00 2001
+From: Hyun Kwon <hyun.kwon@xilinx.com>
+Date: Wed, 21 Jan 2015 11:53:19 -0800
+Subject: [PATCH] src: drmmode_xilinx: Add the dumb gem support for Xilinx
+
+Add the dumb gem support for Xilinx
+
+Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com>
+Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
+Upstream-Status: Pending
+---
+ src/Makefile.am                     |  3 +-
+ src/armsoc_driver.c                 |  1 +
+ src/drmmode_driver.h                |  1 +
+ src/drmmode_xilinx/drmmode_xilinx.c | 76 +++++++++++++++++++++++++++++++++++++
+ 4 files changed, 80 insertions(+), 1 deletion(-)
+ create mode 100644 src/drmmode_xilinx/drmmode_xilinx.c
+
+diff --git a/src/Makefile.am b/src/Makefile.am
+index 3b2601927c..db5f110fb2 100644
+--- a/src/Makefile.am
++++ b/src/Makefile.am
+@@ -43,7 +43,8 @@ armsoc_drv_ladir = @moduledir@/drivers
+ DRMMODE_SRCS = drmmode_exynos/drmmode_exynos.c \
+        drmmode_pl111/drmmode_pl111.c \
+        drmmode_kirin/drmmode_kirin.c \
+-       drmmode_sti/drmmode_sti.c
++       drmmode_sti/drmmode_sti.c \
++       drmmode_xilinx/drmmode_xilinx.c
+ 
+ 
+ armsoc_drv_la_SOURCES = \
+diff --git a/src/armsoc_driver.c b/src/armsoc_driver.c
+index 83e74a7ed1..3ace3c7be5 100644
+--- a/src/armsoc_driver.c
++++ b/src/armsoc_driver.c
+@@ -737,6 +737,7 @@ static struct drmmode_interface *get_drmmode_implementation(int drm_fd)
+                &pl111_interface,
+                &kirin_interface,
+                &sti_interface,
++               &xilinx_interface,
+        };
+        int i;
+ 
+diff --git a/src/drmmode_driver.h b/src/drmmode_driver.h
+index 879fc60ddc..18245d591a 100644
+--- a/src/drmmode_driver.h
++++ b/src/drmmode_driver.h
+@@ -106,6 +106,7 @@ extern struct drmmode_interface exynos_interface;
+ extern struct drmmode_interface pl111_interface;
+ extern struct drmmode_interface kirin_interface;
+ extern struct drmmode_interface sti_interface;
++extern struct drmmode_interface xilinx_interface;
+ 
+ 
+ #endif
+diff --git a/src/drmmode_xilinx/drmmode_xilinx.c b/src/drmmode_xilinx/drmmode_xilinx.c
+new file mode 100644
+index 0000000000..f4faceb0b4
+--- /dev/null
++++ b/src/drmmode_xilinx/drmmode_xilinx.c
+@@ -0,0 +1,76 @@
++/*
++ * Xilinx X11 ARMSOC driver
++ *
++ * Author: Hyun Woo Kwon <hyun.kwon@xilinx.com>
++ *
++ * Copyright (C) 2014 Xilinx, Inc.
++ *
++ * Based on drmmode_exynos.c
++ *
++ * Copyright © 2013 ARM Limited.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice (including the next
++ * paragraph) shall be included in all copies or substantial portions of the
++ * Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
++ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
++ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
++ * SOFTWARE.
++ *
++ */
++
++#include <stdlib.h>
++
++#include <drm.h>
++#include <xf86drm.h>
++
++#include "../drmmode_driver.h"
++
++static int create_custom_gem(int fd, struct armsoc_create_gem *create_gem)
++{
++       struct drm_mode_create_dumb arg;
++       int ret;
++
++       memset(&arg, 0, sizeof(arg));
++       arg.height = create_gem->height;
++       arg.width = create_gem->width;
++       arg.bpp = create_gem->bpp;
++
++       ret = drmIoctl(fd, DRM_IOCTL_MODE_CREATE_DUMB, &arg);
++       if (ret)
++               return ret;
++
++       create_gem->height = arg.height;
++       create_gem->width = arg.width;
++       create_gem->bpp = arg.bpp;
++       create_gem->handle = arg.handle;
++       create_gem->pitch = arg.pitch;
++       create_gem->size = arg.size;
++
++       return 0;
++}
++
++struct drmmode_interface xilinx_interface = {
++       "xlnx"                /* name of drm driver */,
++       1                     /* use_page_flip_events */,
++       1                     /* use_early_display */,
++       0                     /* cursor width */,
++       0                     /* cursor_height */,
++       0                     /* cursor padding */,
++       HWCURSOR_API_NONE     /* cursor_api */,
++       NULL                  /* init_plane_for_cursor */,
++       0                     /* vblank_query_supported */,
++       create_custom_gem     /* create_custom_gem */,
++};
++
+-- 
+2.11.0
+
diff --git a/meta-xilinx-core/dynamic-layers/openembedded-layer/recipes-graphics/xorg-driver/xf86-video-armsoc_%.bbappend b/meta-xilinx-core/dynamic-layers/openembedded-layer/recipes-graphics/xorg-driver/xf86-video-armsoc_%.bbappend
new file mode 100644
index 00000000..f7b52f58
--- /dev/null
+++ b/meta-xilinx-core/dynamic-layers/openembedded-layer/recipes-graphics/xorg-driver/xf86-video-armsoc_%.bbappend
@@ -0,0 +1,5 @@
+FILESEXTRAPATHS:prepend := "${THISDIR}/xf86-video-armsoc:"
+
+SRC_URI:append = " file://0001-src-drmmode_xilinx-Add-the-dumb-gem-support-for-Xili.patch \
+                   file://0001-armsoc_driver.c-Bypass-the-exa-layer-to-free-the-roo.patch \
+                "
diff --git a/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc b/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc
new file mode 100644
index 00000000..94925fa9
--- /dev/null
+++ b/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc
@@ -0,0 +1,103 @@
+DESCRIPTION = "ARM Trusted Firmware"
+
+LICENSE = "BSD"
+LIC_FILES_CHKSUM ?= "file://license.rst;md5=1dd070c98a281d18d9eefd938729b031"
+
+PROVIDES = "virtual/arm-trusted-firmware"
+
+inherit deploy
+
+DEPENDS += "u-boot-mkimage-native"
+
+S = "${WORKDIR}/git"
+B = "${WORKDIR}/build"
+
+SYSROOT_DIRS += "/boot"
+
+XILINX_RELEASE_VERSION ?= ""
+ATF_VERSION ?= "2.2"
+ATF_VERSION_EXTENSION ?= "-xilinx-${XILINX_RELEASE_VERSION}"
+PV = "${ATF_VERSION}${ATF_VERSION_EXTENSION}+git${SRCPV}"
+
+BRANCH ?= ""
+REPO ?= "git://github.com/Xilinx/arm-trusted-firmware.git;protocol=https"
+BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}"
+SRC_URI = "${REPO};${BRANCHARG}"
+
+inherit image-artifact-names
+
+ATF_BASE_NAME ?= "${PN}-${PKGE}-${PKGV}-${PKGR}${IMAGE_VERSION_SUFFIX}"
+
+# Specify a default in case boardvariant isn't available
+BOARDVARIANT_ARCH ??= "${MACHINE_ARCH}"
+PACKAGE_ARCH = "${BOARDVARIANT_ARCH}"
+
+COMPATIBLE_MACHINE ?= "^$"
+COMPATIBLE_MACHINE:zynqmp = ".*"
+COMPATIBLE_MACHINE:versal = ".*"
+
+PLATFORM:zynqmp = "zynqmp"
+PLATFORM:versal = "versal"
+
+# requires CROSS_COMPILE set by hand as there is no configure script
+export CROSS_COMPILE="${TARGET_PREFIX}"
+
+# Let the Makefile handle setting up the CFLAGS and LDFLAGS as it is a standalone application
+CFLAGS[unexport] = "1"
+LDFLAGS[unexport] = "1"
+AS[unexport] = "1"
+LD[unexport] = "1"
+
+ATF_CONSOLE ?= ""
+ATF_CONSOLE:zynqmp = "cadence"
+ATF_CONSOLE:versal ?= "pl011"
+
+DEBUG_ATF ?= ""
+DEBUG_ATF:versal ?= "1"
+
+EXTRA_OEMAKE:zynqmp:append = "${@' ZYNQMP_CONSOLE=${ATF_CONSOLE}' if d.getVar('ATF_CONSOLE', True) != '' else ''}"
+EXTRA_OEMAKE:append:versal = "${@' VERSAL_CONSOLE=${ATF_CONSOLE}' if d.getVar('ATF_CONSOLE', True) != '' else ''}"
+EXTRA_OEMAKE:append = " ${@bb.utils.contains('DEBUG_ATF', '1', ' DEBUG=${DEBUG_ATF}', '', d)}"
+
+OUTPUT_DIR = "${@bb.utils.contains('DEBUG_ATF', '1', '${B}/${PLATFORM}/debug', '${B}/${PLATFORM}/release', d)}"
+
+ATF_MEM_BASE ?= "0x1000"
+ATF_MEM_SIZE ?= "0x7ffff"
+
+EXTRA_OEMAKE:zynqmp:append = "${@' ZYNQMP_ATF_MEM_BASE=${ATF_MEM_BASE}' if d.getVar('ATF_MEM_BASE', True) != '' else ''}"
+EXTRA_OEMAKE:zynqmp:append = "${@' ZYNQMP_ATF_MEM_SIZE=${ATF_MEM_SIZE}' if d.getVar('ATF_MEM_SIZE', True) != '' else ''}"
+
+EXTRA_OEMAKE:append:versal = "${@' VERSAL_ATF_MEM_BASE=${ATF_MEM_BASE}' if d.getVar('ATF_MEM_BASE', True) != '' else ''}"
+EXTRA_OEMAKE:append:versal = "${@' VERSAL_ATF_MEM_SIZE=${ATF_MEM_SIZE}' if d.getVar('ATF_MEM_SIZE', True) != '' else ''}"
+EXTRA_OEMAKE:append:vc-p-a2197-00-versal =" VERSAL_PLATFORM=silicon"
+
+do_configure() {
+        oe_runmake clean -C ${S} BUILD_BASE=${B} PLAT=${PLATFORM}
+}
+
+do_compile() {
+        oe_runmake -C ${S} BUILD_BASE=${B} PLAT=${PLATFORM} RESET_TO_BL31=1 bl31
+}
+
+do_install() {
+        install -d ${D}/boot
+        install -Dm 0644 ${OUTPUT_DIR}/bl31/bl31.elf ${D}/boot/${PN}.elf
+}
+
+do_deploy() {
+        install -d ${DEPLOYDIR}
+        install -m 0644 ${OUTPUT_DIR}/bl31/bl31.elf ${DEPLOYDIR}/${ATF_BASE_NAME}.elf
+        ln -sf ${ATF_BASE_NAME}.elf ${DEPLOYDIR}/${PN}.elf
+        install -m 0644 ${OUTPUT_DIR}/bl31.bin ${DEPLOYDIR}/${ATF_BASE_NAME}.bin
+        ln -sf ${ATF_BASE_NAME}.bin ${DEPLOYDIR}/${PN}.bin
+
+        # Get the entry point address from the elf.
+        BL31_BASE_ADDR=$(${READELF} -h ${OUTPUT_DIR}/bl31/bl31.elf | egrep -m 1 -i "entry point.*?0x" | sed -r 's/.*?(0x.*?)/\1/g')
+        mkimage -A arm64 -O arm-trusted-firmware -T kernel -C none \
+                -a $BL31_BASE_ADDR -e $BL31_BASE_ADDR \
+                -d ${OUTPUT_DIR}/bl31.bin ${DEPLOYDIR}/${ATF_BASE_NAME}.ub
+        ln -sf ${ATF_BASE_NAME}.ub ${DEPLOYDIR}/${PN}.ub
+        ln -sf ${ATF_BASE_NAME}.ub ${DEPLOYDIR}/atf-uboot.ub
+}
+addtask deploy before do_build after do_compile
+FILES:${PN} += "/boot/${PN}.elf"
diff --git a/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2021.2.bb b/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2021.2.bb
new file mode 100644
index 00000000..f69ed50c
--- /dev/null
+++ b/meta-xilinx-core/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware_2021.2.bb
@@ -0,0 +1,8 @@
+ATF_VERSION = "2.4"
+SRCREV = "9188496b9b23a665782bb3d2c2b9e3b29b7fb4e2"
+BRANCH = "xlnx_rebase_v2.4"
+LIC_FILES_CHKSUM = "file://license.rst;md5=1dd070c98a281d18d9eefd938729b031"
+
+
+include arm-trusted-firmware.inc
+
diff --git a/meta-xilinx-core/recipes-bsp/base-pdi/base-pdi_1.0.bb b/meta-xilinx-core/recipes-bsp/base-pdi/base-pdi_1.0.bb
new file mode 100644
index 00000000..4e940642
--- /dev/null
+++ b/meta-xilinx-core/recipes-bsp/base-pdi/base-pdi_1.0.bb
@@ -0,0 +1,35 @@
+DESCRIPTION = "Recipe to deploy base pdi"
+
+LICENSE = "CLOSED"
+
+PROVIDES = "virtual/base-pdi"
+
+COMPATIBLE_MACHINE = "^$"
+COMPATIBLE_MACHINE:versal = "versal"
+
+PACKAGE_ARCH ?= "${MACHINE_ARCH}"
+
+do_compile[noexec] = "1"
+
+PDI_PATH ?= ""
+SRC_URI += "${@['file://'+d.getVar('PDI_PATH'),''][d.getVar('PDI_PATH') == '']}"
+
+python() {
+    if d.getVar('PDI_SKIP_CHECK') != "1" and not d.getVar('PDI_PATH'):
+        raise bb.parse.SkipRecipe("PDI_PATH is not configured with the base design pdi")
+}
+
+#base install will just take from PDI_PATH variable
+#will need to bbappend to this in meta-xilinx-tools to use xsct to extract pdi from xsa and install
+do_install() {
+
+    if [ -f ${WORKDIR}/${PDI_PATH} ];then
+        install -d ${D}/boot
+        install -m 0644 ${WORKDIR}/${PDI_PATH} ${D}/boot/base-design.pdi
+    else
+        bbfatal "No base pdi supplied"
+    fi
+}
+SYSROOT_DIRS += "/boot"
+
+FILES:${PN} += "/boot/*"
diff --git a/meta-xilinx-core/recipes-bsp/bootbin/machine-xilinx-versal.inc b/meta-xilinx-core/recipes-bsp/bootbin/machine-xilinx-versal.inc
new file mode 100644
index 00000000..a9c58aa2
--- /dev/null
+++ b/meta-xilinx-core/recipes-bsp/bootbin/machine-xilinx-versal.inc
@@ -0,0 +1,35 @@
+#Extra args for versal
+BOOTGEN_EXTRA_ARGS += "-dump bh"
+
+# specify BIF common attribute for FSBL
+BIF_COMMON_ATTR ?= ""
+
+# specify BIF partition attributes required for BOOT.bin
+BIF_PARTITION_ATTR ?= "base-pdi plmfw psmfw device-tree arm-trusted-firmware u-boot-xlnx"
+
+# specify BIF partition attributes for base-pdi
+BIF_PARTITION_ATTR[base-pdi] ?= "type=bootimage"
+BIF_PARTITION_IMAGE[base-pdi] ?= "${RECIPE_SYSROOT}/boot/base-design.pdi"
+
+# specify BIF partition attributes for plmfw
+BIF_PARTITION_ATTR[plmfw] ?= "type=bootloader"
+BIF_PARTITION_IMAGE[plmfw] ?= "${RECIPE_SYSROOT}/boot/plmfw.elf"
+
+# specify BIF partition attributes for psmfw
+BIF_PARTITION_ATTR[psmfw] ?= "core=psm"
+BIF_PARTITION_IMAGE[psmfw] ?= "${RECIPE_SYSROOT}/boot/psmfw.elf"
+
+# specify BIF partition attributes for device-tree
+BIF_PARTITION_ATTR[device-tree] ?= "type=raw, load=0x1000"
+BIF_PARTITION_IMAGE[device-tree] ?= "${RECIPE_SYSROOT}/boot/devicetree/system-top.dtb"
+BIF_PARTITION_ID[device-tree] ?= "0x1c000000"
+
+# specify BIF partition attributes for u-boot
+BIF_PARTITION_ATTR[u-boot-xlnx] ?= "core=a72-0, exception_level = el-2"
+BIF_PARTITION_IMAGE[u-boot-xlnx] ?= "${RECIPE_SYSROOT}/boot/u-boot.elf"
+BIF_PARTITION_ID[u-boot-xlnx] ?= "0x1c000000"
+
+# specify BIF partition attributes for arm-trusted-firmware
+BIF_PARTITION_ATTR[arm-trusted-firmware] ?= "core=a72-0, exception_level = el-3, trustzone"
+BIF_PARTITION_IMAGE[arm-trusted-firmware] ?= "${RECIPE_SYSROOT}/boot/arm-trusted-firmware.elf"
+BIF_PARTITION_ID[arm-trusted-firmware] ?= "0x1c000000"
diff --git a/meta-xilinx-core/recipes-bsp/bootbin/machine-xilinx-zynq.inc b/meta-xilinx-core/recipes-bsp/bootbin/machine-xilinx-zynq.inc
new file mode 100644
index 00000000..b8d75c4f
--- /dev/null
+++ b/meta-xilinx-core/recipes-bsp/bootbin/machine-xilinx-zynq.inc
@@ -0,0 +1,17 @@
+#specify BIF partition attributes required for BOOT.bin
+BIF_PARTITION_ATTR ?= "fsbl bitstream u-boot"
+
+#specify BIF partition attributes for FSBL
+#bootloader is FSBL. Location where FSBL binary is present and dependency to build FSBL
+BIF_PARTITION_ATTR[fsbl] ?= "bootloader"
+BIF_PARTITION_IMAGE[fsbl] ?= "${DEPLOY_DIR_IMAGE}/fsbl-${MACHINE}.elf"
+BIF_PARTITION_DEPENDS[fsbl] ?= "virtual/fsbl:do_deploy"
+
+#specify BIF partition attributes for u-boot
+#Location where u-boot binary is present
+BIF_PARTITION_IMAGE[u-boot] ?= "${DEPLOY_DIR_IMAGE}/u-boot-${MACHINE}.elf"
+BIF_PARTITION_DEPENDS[u-boot] ?= "virtual/bootloader:do_deploy"
+
+# enable bitstream-Note this is not enabled by default (missing in BIF_PARTITION_ATTR)
+BIF_PARTITION_IMAGE[bitstream] ?= "${DEPLOY_DIR_IMAGE}/download-${MACHINE}.bit"
+BIF_PARTITION_DEPENDS[bitstream] ?= "virtual/bitstream:do_deploy"
diff --git a/meta-xilinx-core/recipes-bsp/bootbin/machine-xilinx-zynqmp.inc b/meta-xilinx-core/recipes-bsp/bootbin/machine-xilinx-zynqmp.inc
new file mode 100644
index 00000000..4eb404c1
--- /dev/null
+++ b/meta-xilinx-core/recipes-bsp/bootbin/machine-xilinx-zynqmp.inc
@@ -0,0 +1,33 @@
+# specify BIF common attribute for FSBL
+BIF_COMMON_ATTR ?= ""
+
+# specify BIF partition attributes required for BOOT.bin
+BIF_PARTITION_ATTR = "fsbl pmufw arm-trusted-firmware device-tree u-boot-xlnx"
+
+# specify BIF partition attributes for FSBL
+# bootloader is FSBL. Location where FSBL binary is present and dependency to build FSBL
+BIF_PARTITION_ATTR[fsbl] ?= "bootloader, destination_cpu=a53-0"
+BIF_PARTITION_IMAGE[fsbl] ?= "${RECIPE_SYSROOT}/boot/fsbl.elf"
+
+# specify BIF partition attributes for PMU Firmware
+# destination cpu for PMU. Location where PMU binary is present and dependency to build PMU Firmware
+BIF_PARTITION_ATTR[pmufw] ?= "destination_cpu=pmu"
+BIF_PARTITION_IMAGE[pmufw] ?= "${RECIPE_SYSROOT}/boot/pmufw.elf"
+
+# specify BIF partition attributes for ATF
+# destination cpu for ATF, security levels. Location where ATF binary is present (dependency is not required as ATF is always built for ZU+, see zcu102-zynqmp.conf)
+BIF_PARTITION_ATTR[arm-trusted-firmware] ?= "destination_cpu=a53-0,exception_level=el-3,trustzone"
+BIF_PARTITION_IMAGE[arm-trusted-firmware] ?= "${RECIPE_SYSROOT}/boot/arm-trusted-firmware.elf"
+
+# specify BIF partition attributes for u-boot
+# destination cpu for u-boot, security levels. Location where u-boot binary is present (dependency is not required as u-boot is always built for ZU+, see zcu102-zynqmp.conf)
+BIF_PARTITION_ATTR[u-boot-xlnx] ?= "destination_cpu=a53-0,exception_level=el-2"
+BIF_PARTITION_IMAGE[u-boot-xlnx] ?= "${RECIPE_SYSROOT}/boot/u-boot.elf"
+
+# specify BIF partition attributes for dtb
+BIF_PARTITION_ATTR[device-tree] ?= "destination_cpu=a53-0,load=0x100000"
+BIF_PARTITION_IMAGE[device-tree] ?= "${RECIPE_SYSROOT}/boot/devicetree/system-top.dtb"
+
+# enable bitstream-Note this is not enabled by default (missing in BIF_PARTITION_ATTR)
+BIF_PARTITION_ATTR[bitstream] ?= "destination_device=pl"
+BIF_PARTITION_IMAGE[bitstream] ?= "${DEPLOY_DIR_IMAGE}/download-${MACHINE}.bit"
diff --git a/meta-xilinx-core/recipes-bsp/bootbin/xilinx-bootbin_1.0.bb b/meta-xilinx-core/recipes-bsp/bootbin/xilinx-bootbin_1.0.bb
new file mode 100644
index 00000000..532da106
--- /dev/null
+++ b/meta-xilinx-core/recipes-bsp/bootbin/xilinx-bootbin_1.0.bb
@@ -0,0 +1,171 @@
+SUMMARY = "Generates boot.bin using bootgen tool"
+DESCRIPTION = "Manages task dependencies and creation of boot.bin. Use the \
+BIF_PARTITION_xyz global variables and flags to determine what makes it into \
+the image."
+
+LICENSE = "BSD"
+
+include machine-xilinx-${SOC_FAMILY}.inc
+
+inherit deploy
+
+PROVIDES = "virtual/boot-bin"
+
+DEPENDS += "bootgen-native"
+
+# There is no bitstream recipe, so really depend on virtual/bitstream
+DEPENDS += "${@(d.getVar('BIF_PARTITION_ATTR') or "").replace('bitstream', 'virtual/bitstream')}"
+
+# Specify a default in case boardvariant isn't available
+BOARDVARIANT_ARCH ??= "${MACHINE_ARCH}"
+PACKAGE_ARCH = "${BOARDVARIANT_ARCH}"
+
+BIF_FILE_PATH ?= "${B}/bootgen.bif"
+
+LICENSE = "MIT"
+LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/MIT;md5=0835ade698e0bcf8506ecda2f7b4f302"
+
+SRC_URI += "${@('file://' + d.getVar("BIF_FILE_PATH")) if d.getVar("BIF_FILE_PATH") != (d.getVar('B') + '/bootgen.bif') else ''}"
+
+BOOTGEN_EXTRA_ARGS ?= ""
+
+do_patch[noexec] = "1"
+
+def create_bif(config, attrflags, attrimage, ids, common_attr, biffd, d):
+    import re, os
+    for cfg in config:
+        if cfg not in attrflags and common_attr:
+            error_msg = "%s: invalid ATTRIBUTE" % (cfg)
+            bb.error("BIF attribute Error: %s " % (error_msg))
+        else:
+            if common_attr:
+                cfgval = d.expand(attrflags[cfg]).split(',')
+                cfgstr = "\t [%s] %s\n" % (cfg,', '.join(cfgval))
+            else:
+                if cfg not in attrimage:
+                    error_msg = "%s: invalid or missing elf or image" % (cfg)
+                    bb.error("BIF atrribute Error: %s " % (error_msg))
+                imagestr = d.expand(attrimage[cfg])
+                if os.stat(imagestr).st_size == 0:
+                    bb.warn("Empty file %s, excluding from bif file" %(imagestr))
+                    continue
+                if cfg in attrflags:
+                    cfgval = d.expand(attrflags[cfg]).split(',')
+                    cfgstr = "\t [%s] %s\n" % (', '.join(cfgval), imagestr)
+                else:
+                    cfgstr = "\t %s\n" % (imagestr)
+            biffd.write(cfgstr)
+
+    return
+
+def create_versal_bif(config, attrflags, attrimage, ids, common_attr, biffd, d):
+    import re, os
+    id_dict = {}
+    for cfg in config:
+        if cfg not in attrflags and common_attr:
+            error_msg = "%s: invalid ATTRIBUTE" % (cfg)
+            bb.error("BIF attribute Error: %s " % (error_msg))
+        else:
+            if common_attr:
+                cfgval = d.expand(attrflags[cfg]).split(',')
+                #TODO: Does common attribute syntax change in similar way for versal?
+                cfgstr = "\t { %s %s }\n" % (cfg,', '.join(cfgval))
+                biffd.write(cfgstr)
+            else:
+                if cfg not in attrimage:
+                    error_msg = "%s: invalid or missing elf or image" % (cfg)
+                    bb.error("BIF atrribute Error: %s " % (error_msg))
+                imagestr = d.expand(attrimage[cfg])
+                if os.stat(imagestr).st_size == 0:
+                    bb.warn("Empty file %s, excluding from bif file" %(imagestr))
+                    continue
+                if cfg in attrflags:
+                    cfgval = d.expand(attrflags[cfg]).split(',')
+                    try:
+                        id = d.expand(ids[cfg])
+                    except:
+                        id = '0'
+                    cfgstr = "\t { %s, file=%s }\n" % (', '.join(cfgval), imagestr)
+                    try:
+                        id_dict[id] += cfgstr
+                    except:
+                        id_dict[id] = cfgstr
+                else:
+                    cfgstr = "\t %s\n" % (imagestr)
+    for id, string in id_dict.items():
+        biffd.write("\timage {\n")
+        if id != '0':
+            biffd.write("\t id = " + id + "\n")
+        biffd.write(string)
+        biffd.write("\t}\n")
+    return
+
+python do_configure() {
+    fp = d.getVar("BIF_FILE_PATH")
+    if fp == (d.getVar('B') + '/bootgen.bif'):
+        arch = d.getVar("SOC_FAMILY")
+        biffunc = {'versal':create_versal_bif, 'zynq':create_bif, 'zynqmp':create_bif}
+        biffd = open(fp, 'w')
+        biffd.write("the_ROM_image:\n")
+        biffd.write("{\n")
+
+        bifattr = (d.getVar("BIF_COMMON_ATTR") or "").split()
+        if bifattr:
+            attrflags = d.getVarFlags("BIF_COMMON_ATTR") or {}
+            biffunc[arch](bifattr, attrflags,'','', 1, biffd, d)
+
+        bifpartition = (d.getVar("BIF_PARTITION_ATTR") or "").split()
+        if bifpartition:
+            attrflags = d.getVarFlags("BIF_PARTITION_ATTR") or {}
+            attrimage = d.getVarFlags("BIF_PARTITION_IMAGE") or {}
+            ids = d.getVarFlags("BIF_PARTITION_ID") or {}
+            biffunc[arch](bifpartition, attrflags, attrimage, ids, 0, biffd, d)
+
+        biffd.write("}")
+        biffd.close()
+    else:
+        print("Using custom BIF file: " + d.getVar("BIF_FILE_PATH") )
+}
+
+do_configure[vardeps] += "BIF_PARTITION_ATTR BIF_PARTITION_IMAGE BIF_COMMON_ATTR"
+
+do_compile() {
+    cd ${WORKDIR}
+    rm -f ${B}/BOOT.bin
+    if [ "${BIF_FILE_PATH}" != "${B}/bootgen.bif" ];then
+        BIF_FILE_PATH="${WORKDIR}${BIF_FILE_PATH}"
+    fi
+    bootgen -image ${BIF_FILE_PATH} -arch ${SOC_FAMILY} ${BOOTGEN_EXTRA_ARGS} -w -o ${B}/BOOT.bin
+    if [ ! -e ${B}/BOOT.bin ]; then
+        bbfatal "bootgen failed. See log"
+    fi
+}
+
+do_install() {
+    install -d ${D}/boot
+    install -m 0644 ${B}/BOOT.bin ${D}/boot/BOOT.bin
+}
+
+inherit image-artifact-names
+
+QEMUQSPI_BASE_NAME ?= "QEMU_qspi-${MACHINE}${IMAGE_VERSION_SUFFIX}"
+
+BOOTBIN_BASE_NAME ?= "BOOT-${MACHINE}${IMAGE_VERSION_SUFFIX}"
+
+do_deploy() {
+    install -d ${DEPLOYDIR}
+    install -m 0644 ${B}/BOOT.bin ${DEPLOYDIR}/${BOOTBIN_BASE_NAME}.bin
+    ln -sf ${BOOTBIN_BASE_NAME}.bin ${DEPLOYDIR}/BOOT-${MACHINE}.bin
+    ln -sf ${BOOTBIN_BASE_NAME}.bin ${DEPLOYDIR}/boot.bin
+}
+
+do_deploy:append:versal () {
+
+    install -m 0644 ${B}/BOOT_bh.bin ${DEPLOYDIR}/${BOOTBIN_BASE_NAME}_bh.bin
+    ln -sf ${BOOTBIN_BASE_NAME}_bh.bin ${DEPLOYDIR}/BOOT-${MACHINE}_bh.bin
+}
+
+FILES:${PN} += "/boot/BOOT.bin"
+SYSROOT_DIRS += "/boot"
+
+addtask do_deploy before do_build after do_compile
diff --git a/meta-xilinx-core/recipes-bsp/bootbin/xilinx-mcs_1.0.bb b/meta-xilinx-core/recipes-bsp/bootbin/xilinx-mcs_1.0.bb
new file mode 100644
index 00000000..bcfe900d
--- /dev/null
+++ b/meta-xilinx-core/recipes-bsp/bootbin/xilinx-mcs_1.0.bb
@@ -0,0 +1,70 @@
+SUMMARY = "Generates boot.mcs using vivado"
+DESCRIPTION = "Manages task dependencies and creation of boot.mcs for microblaze"
+
+LICENSE = "BSD"
+
+PROVIDES = "virtual/boot-bin"
+
+DEPENDS = "bitstream-microblaze"
+
+PACKAGE_ARCH = "${MACHINE_ARCH}"
+
+COMPATIBLE_MACHINE ?= "^$"
+COMPATIBLE_MACHINE:microblaze = ".*"
+
+inherit deploy image-artifact-names
+
+do_fetch[noexec] = "1"
+do_unpack[noexec] = "1"
+do_patch[noexec] = "1"
+
+PROC ??= "kc705_i/microblaze_0"
+PROC:kc705 = "kc705_i/microblaze_0"
+
+FLASH_SIZE ??= "0x80"
+FLASH_INTERFACE ??= "BPIx16"
+MB_OUT_FORMAT  ??= "mcs"
+BOOT_EXT = "${@d.getVar('MB_OUT_FORMAT').lower()}"
+
+BITSTREAM_FILE ?= "${RECIPE_SYSROOT}/boot/bitstream/download.bit"
+B = "${WORKDIR}/build"
+WR_CFGMEM_MISC ?= "-loadbit \" up 0 ${BITSTREAM_FILE}\""
+
+do_check_for_vivado() {
+        bbnote "Checking Vivado install path"
+        which "vivado" 2>/dev/null || {
+                bbfatal "Vivado not found! Please add \"INHERIT += \"vivado\"\" to your local.conf"
+  }
+}
+
+addtask do_check_for_vivado before do_configure
+
+do_configure() {
+    echo " write_cfgmem -force -format ${MB_OUT_FORMAT} -size ${FLASH_SIZE} -interface ${FLASH_INTERFACE} ${WR_CFGMEM_MISC} ${B}/BOOT.${BOOT_EXT} " > ${B}/write_cfgmem_boot_mcs.tcl
+    if [ ! -e ${B}/write_cfgmem_boot_mcs.tcl ]; then
+        bbfatal "write_cfgmem_boot_mcs.tcl creation failed. See log for details"
+    fi
+}
+
+
+do_compile() {
+    vivado -log "${B}/cfgmem_mcs.log" -jou "${B}/cfgmem_mcs.jou" -mode batch -s ${B}/write_cfgmem_boot_mcs.tcl
+    if [ ! -e ${B}/BOOT.${BOOT_EXT} ]; then
+        bbfatal "BOOT.${BOOT_EXT} failed. See log"
+    fi
+}
+
+do_install() {
+        :
+}
+
+BOOT_BASE_NAME ?= "BOOT-${MACHINE}${IMAGE_VERSION_SUFFIX}"
+
+do_deploy() {
+    #install BOOT.mcs
+    if [ -e ${B}/BOOT.${BOOT_EXT} ]; then
+        install -Dm 0644 ${B}/BOOT.${BOOT_EXT} ${DEPLOYDIR}/${BOOT_BASE_NAME}.${BOOT_EXT}
+        ln -sf ${BOOT_BASE_NAME}.${BOOT_EXT} ${DEPLOYDIR}/BOOT-${MACHINE}.${BOOT_EXT}
+    fi
+}
+addtask do_deploy before do_build after do_compile
diff --git a/meta-xilinx-core/recipes-bsp/bootgen/bootgen_1.0.bb b/meta-xilinx-core/recipes-bsp/bootgen/bootgen_1.0.bb
new file mode 100644
index 00000000..236da302
--- /dev/null
+++ b/meta-xilinx-core/recipes-bsp/bootgen/bootgen_1.0.bb
@@ -0,0 +1,31 @@
+SUMMARY = "Building and installing bootgen"
+DESCRIPTION = "Building and installing bootgen, a Xilinx tool that lets you stitch binary files together and generate device boot images"
+
+LICENSE = "Apache-2.0"
+LIC_FILES_CHKSUM = "file://LICENSE;md5=d526b6d0807bf263b97da1da876f39b1"
+
+S = "${WORKDIR}/git"
+
+DEPENDS += "openssl"
+RDEPENDS:${PN} += "openssl"
+
+REPO ?= "git://github.com/Xilinx/bootgen.git;protocol=https"
+BRANCH ?= "xlnx_rel_v2021.2"
+SRCREV = "5b6fe16a2bfd7ced4d90b70b0ba6fbf325e81e97"
+
+BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}"
+SRC_URI = "${REPO};${BRANCHARG}"
+
+EXTRA_OEMAKE += 'CROSS_COMPILER="${CXX}" -C ${S}'
+CXXFLAGS:append = " -std=c++0x"
+
+TARGET_CC_ARCH += "${LDFLAGS}"
+
+do_install() {
+    install -d ${D}${bindir}
+    install -Dm 0755 ${S}/bootgen ${D}${bindir}
+}
+
+FILES:${PN} = "${bindir}/bootgen"
+
+BBCLASSEXTEND = "native nativesdk"
diff --git a/meta-xilinx-core/recipes-bsp/cdo/extract-cdo_1.0.bb b/meta-xilinx-core/recipes-bsp/cdo/extract-cdo_1.0.bb
new file mode 100644
index 00000000..37c284ad
--- /dev/null
+++ b/meta-xilinx-core/recipes-bsp/cdo/extract-cdo_1.0.bb
@@ -0,0 +1,34 @@
+DESCRIPTION = "Recipe to copy external cdos"
+
+LICENSE = "CLOSED"
+
+inherit deploy
+
+PROVIDES = "virtual/cdo"
+
+DEPENDS += "bootgen-native"
+
+do_compile[depends] += "virtual/boot-bin:do_deploy"
+
+COMPATIBLE_MACHINE = "^$"
+COMPATIBLE_MACHINE:versal = "versal"
+
+PACKAGE_ARCH ?= "${MACHINE_ARCH}"
+
+B = "${WORKDIR}/build"
+
+BOOTGEN_CMD ?= "bootgen"
+BOOTGEN_ARGS ?= "-arch versal"
+BOOTGEN_OUTFILE ?= "${DEPLOY_DIR_IMAGE}/boot.bin"
+
+#The following line creates the pmc_cdo.bin file at the same dir as the boot.bin which is DEPLOY_DIR_IMAGE
+do_compile() {
+    ${BOOTGEN_CMD} ${BOOTGEN_ARGS} -dump ${BOOTGEN_OUTFILE} pmc_cdo
+}
+
+do_deploy() {
+    install -d ${DEPLOYDIR}/CDO
+    install -m 0644 ${DEPLOY_DIR_IMAGE}/pmc_cdo.bin ${DEPLOYDIR}/CDO/pmc_cdo.bin
+}
+
+addtask do_deploy after do_install
diff --git a/meta-xilinx-core/recipes-bsp/device-tree/device-tree.bb b/meta-xilinx-core/recipes-bsp/device-tree/device-tree.bb
new file mode 100644
index 00000000..3e71eeaf
--- /dev/null
+++ b/meta-xilinx-core/recipes-bsp/device-tree/device-tree.bb
@@ -0,0 +1,69 @@
+SUMMARY = "Xilinx BSP device trees"
+DESCRIPTION = "Xilinx BSP device trees from within layer."
+SECTION = "bsp"
+
+# the device trees from within the layer are licensed as MIT, kernel includes are GPL
+LICENSE = "MIT & GPLv2"
+LIC_FILES_CHKSUM = " \
+                file://${COMMON_LICENSE_DIR}/MIT;md5=0835ade698e0bcf8506ecda2f7b4f302 \
+                file://${COMMON_LICENSE_DIR}/GPL-2.0-or-later;md5=fed54355545ffd980b814dab4a3b312c \
+                "
+
+inherit devicetree image-artifact-names
+
+#this way of going through SRC_URI is better but if dts is including other dtsis, need to add all of them to SRC_URI..
+#SRC_URI += "file://${SYSTEM_DTFILE}"
+#DT_FILES_PATH = "${@d.getVar('WORKDIR')+'/'+os.path.dirname(d.getVar('SYSTEM_DTFILE'))}"
+
+DT_FILES_PATH = "${@os.path.dirname(d.getVar('SYSTEM_DTFILE')) if d.getVar('SYSTEM_DTFILE') else d.getVar('S')}"
+
+COMPATIBLE_MACHINE:zynqmp = ".*"
+COMPATIBLE_MACHINE:versal = ".*"
+
+# Device-trees are inherently board specific
+BOARD_ARCH ??= "${MACHINE_ARCH}"
+PACKAGE_ARCH = "${BOARD_ARCH}"
+
+DEPENDS += "python3-dtc-native"
+
+PROVIDES = "virtual/dtb"
+
+# common zynq include
+SRC_URI:append:zynq = " file://zynq-7000-qspi-dummy.dtsi"
+
+# device tree sources for the various machines
+COMPATIBLE_MACHINE:picozed-zynq7 = ".*"
+SRC_URI:append:picozed-zynq7 = " file://picozed-zynq7.dts"
+
+COMPATIBLE_MACHINE:qemu-zynq7 = ".*"
+SRC_URI:append:qemu-zynq7 = " file://qemu-zynq7.dts"
+
+COMPATIBLE_MACHINE:zybo-linux-bd-zynq7 = ".*"
+SRC_URI:append:zybo-linux-bd-zynq7 = " \
+                file://zybo-linux-bd-zynq7.dts \
+                file://pcw.dtsi \
+                file://pl.dtsi \
+                "
+
+COMPATIBLE_MACHINE:kc705-microblazeel = ".*"
+SRC_URI:append:kc705-microblazeel = " \
+                file://kc705-microblazeel.dts \
+                file://pl.dtsi \
+                file://system-conf.dtsi \
+                "
+
+DTB_FILE_NAME = "${@os.path.basename(d.getVar('SYSTEM_DTFILE')).replace('.dts', '.dtb') if d.getVar('SYSTEM_DTFILE') else ''}"
+DTB_BASE_NAME ?= "${MACHINE}-system${IMAGE_VERSION_SUFFIX}"
+
+devicetree_do_deploy:append() {
+    if [ -n "${DTB_FILE_NAME}" ]; then
+        if [ -e "${DEPLOYDIR}/devicetree/${DTB_FILE_NAME}" ]; then
+            # We need the output to be system.dtb for WIC setup to match XSCT flow
+            ln -sf devicetree/${DTB_FILE_NAME} ${DEPLOYDIR}/${DTB_BASE_NAME}.dtb
+            ln -sf devicetree/${DTB_FILE_NAME} ${DEPLOYDIR}/${MACHINE}-system.dtb
+            ln -sf devicetree/${DTB_FILE_NAME} ${DEPLOYDIR}/system.dtb
+        else
+            bberror "Expected filename ${DTB_FILE_NAME} doesn't exist in ${DEPLOYDIR}/devicetree"
+        fi
+    fi
+}
diff --git a/meta-xilinx-core/recipes-bsp/device-tree/files/kc705-microblazeel/kc705-microblazeel.dts b/meta-xilinx-core/recipes-bsp/device-tree/files/kc705-microblazeel/kc705-microblazeel.dts
new file mode 100644
index 00000000..45e488c1
--- /dev/null
+++ b/meta-xilinx-core/recipes-bsp/device-tree/files/kc705-microblazeel/kc705-microblazeel.dts
@@ -0,0 +1,56 @@
+/dts-v1/;
+/include/ "pl.dtsi"
+/include/ "system-conf.dtsi"
+/ {
+        hard-reset-gpios = <&reset_gpio 0 1>;
+        aliases {
+                ethernet0 = &axi_ethernet;
+                i2c0 = &iic_main;
+                serial0 = &rs232_uart;
+        };
+        memory {
+                device_type = "memory";
+                reg = <0x80000000 0x40000000>;
+        };
+};
+
+&iic_main {
+        i2cswitch@74 {
+                compatible = "nxp,pca9548";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg = <0x74>;
+                i2c@0 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0>;
+                        si570: clock-generator@5d {
+                                #clock-cells = <0>;
+                                compatible = "silabs,si570";
+                                temperature-stability = <50>;
+                                reg = <0x5d>;
+                                factory-fout = <156250000>;
+                                clock-frequency = <148500000>;
+                        };
+                };
+                i2c@3 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <3>;
+                        eeprom@54 {
+                                compatible = "at,24c08";
+                                reg = <0x54>;
+                        };
+                };
+        };
+};
+
+&axi_ethernet {
+        phy-handle = <&phy0>;
+        axi_ethernet_mdio: mdio {
+                phy0: phy@7 {
+                        device_type = "ethernet-phy";
+                        reg = <7>;
+                };
+        };
+};
diff --git a/meta-xilinx-core/recipes-bsp/device-tree/files/kc705-microblazeel/pl.dtsi b/meta-xilinx-core/recipes-bsp/device-tree/files/kc705-microblazeel/pl.dtsi
new file mode 100644
index 00000000..43bc2ab7
--- /dev/null
+++ b/meta-xilinx-core/recipes-bsp/device-tree/files/kc705-microblazeel/pl.dtsi
@@ -0,0 +1,445 @@
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "xlnx,microblaze";
+        model = "Xilinx MicroBlaze";
+        cpus {
+                #address-cells = <1>;
+                #cpus = <1>;
+                #size-cells = <0>;
+                microblaze_0: cpu@0 {
+                        bus-handle = <&amba_pl>;
+                        clock-frequency = <200000000>;
+                        clocks = <&clk_cpu>;
+                        compatible = "xlnx,microblaze-10.0";
+                        d-cache-baseaddr = <0x0000000080000000>;
+                        d-cache-highaddr = <0x00000000bfffffff>;
+                        d-cache-line-size = <0x20>;
+                        d-cache-size = <0x4000>;
+                        device_type = "cpu";
+                        i-cache-baseaddr = <0x0000000080000000>;
+                        i-cache-highaddr = <0x00000000bfffffff>;
+                        i-cache-line-size = <0x10>;
+                        i-cache-size = <0x4000>;
+                        interrupt-handle = <&microblaze_0_axi_intc>;
+                        model = "microblaze,10.0";
+                        timebase-frequency = <200000000>;
+                        xlnx,addr-size = <0x20>;
+                        xlnx,addr-tag-bits = <0x10>;
+                        xlnx,allow-dcache-wr = <0x1>;
+                        xlnx,allow-icache-wr = <0x1>;
+                        xlnx,area-optimized = <0x0>;
+                        xlnx,async-interrupt = <0x1>;
+                        xlnx,async-wakeup = <0x3>;
+                        xlnx,avoid-primitives = <0x0>;
+                        xlnx,base-vectors = <0x0000000000000000>;
+                        xlnx,branch-target-cache-size = <0x0>;
+                        xlnx,cache-byte-size = <0x4000>;
+                        xlnx,d-axi = <0x1>;
+                        xlnx,d-lmb = <0x1>;
+                        xlnx,d-lmb-mon = <0x0>;
+                        xlnx,daddr-size = <0x20>;
+                        xlnx,data-size = <0x20>;
+                        xlnx,dc-axi-mon = <0x0>;
+                        xlnx,dcache-addr-tag = <0x10>;
+                        xlnx,dcache-always-used = <0x1>;
+                        xlnx,dcache-byte-size = <0x4000>;
+                        xlnx,dcache-data-width = <0x0>;
+                        xlnx,dcache-force-tag-lutram = <0x0>;
+                        xlnx,dcache-line-len = <0x8>;
+                        xlnx,dcache-use-writeback = <0x0>;
+                        xlnx,dcache-victims = <0x0>;
+                        xlnx,debug-counter-width = <0x20>;
+                        xlnx,debug-enabled = <0x1>;
+                        xlnx,debug-event-counters = <0x5>;
+                        xlnx,debug-external-trace = <0x0>;
+                        xlnx,debug-interface = <0x0>;
+                        xlnx,debug-latency-counters = <0x1>;
+                        xlnx,debug-profile-size = <0x0>;
+                        xlnx,debug-trace-async-reset = <0x0>;
+                        xlnx,debug-trace-size = <0x2000>;
+                        xlnx,div-zero-exception = <0x1>;
+                        xlnx,dp-axi-mon = <0x0>;
+                        xlnx,dynamic-bus-sizing = <0x0>;
+                        xlnx,ecc-use-ce-exception = <0x0>;
+                        xlnx,edge-is-positive = <0x1>;
+                        xlnx,enable-discrete-ports = <0x0>;
+                        xlnx,endianness = <0x1>;
+                        xlnx,fault-tolerant = <0x0>;
+                        xlnx,fpu-exception = <0x0>;
+                        xlnx,freq = <0xbebc200>;
+                        xlnx,fsl-exception = <0x0>;
+                        xlnx,fsl-links = <0x0>;
+                        xlnx,i-axi = <0x0>;
+                        xlnx,i-lmb = <0x1>;
+                        xlnx,i-lmb-mon = <0x0>;
+                        xlnx,iaddr-size = <0x20>;
+                        xlnx,ic-axi-mon = <0x0>;
+                        xlnx,icache-always-used = <0x1>;
+                        xlnx,icache-data-width = <0x0>;
+                        xlnx,icache-force-tag-lutram = <0x0>;
+                        xlnx,icache-line-len = <0x4>;
+                        xlnx,icache-streams = <0x1>;
+                        xlnx,icache-victims = <0x8>;
+                        xlnx,ill-opcode-exception = <0x1>;
+                        xlnx,imprecise-exceptions = <0x0>;
+                        xlnx,instr-size = <0x20>;
+                        xlnx,interconnect = <0x2>;
+                        xlnx,interrupt-is-edge = <0x0>;
+                        xlnx,interrupt-mon = <0x0>;
+                        xlnx,ip-axi-mon = <0x0>;
+                        xlnx,lockstep-master = <0x0>;
+                        xlnx,lockstep-select = <0x0>;
+                        xlnx,lockstep-slave = <0x0>;
+                        xlnx,mmu-dtlb-size = <0x4>;
+                        xlnx,mmu-itlb-size = <0x2>;
+                        xlnx,mmu-privileged-instr = <0x0>;
+                        xlnx,mmu-tlb-access = <0x3>;
+                        xlnx,mmu-zones = <0x2>;
+                        xlnx,num-sync-ff-clk = <0x2>;
+                        xlnx,num-sync-ff-clk-debug = <0x2>;
+                        xlnx,num-sync-ff-clk-irq = <0x1>;
+                        xlnx,num-sync-ff-dbg-clk = <0x1>;
+                        xlnx,num-sync-ff-dbg-trace-clk = <0x2>;
+                        xlnx,number-of-pc-brk = <0x1>;
+                        xlnx,number-of-rd-addr-brk = <0x0>;
+                        xlnx,number-of-wr-addr-brk = <0x0>;
+                        xlnx,opcode-0x0-illegal = <0x1>;
+                        xlnx,optimization = <0x0>;
+                        xlnx,pc-width = <0x20>;
+                        xlnx,piaddr-size = <0x20>;
+                        xlnx,pvr = <0x2>;
+                        xlnx,pvr-user1 = <0x00>;
+                        xlnx,pvr-user2 = <0x00000000>;
+                        xlnx,reset-msr = <0x00000000>;
+                        xlnx,reset-msr-bip = <0x0>;
+                        xlnx,reset-msr-dce = <0x0>;
+                        xlnx,reset-msr-ee = <0x0>;
+                        xlnx,reset-msr-eip = <0x0>;
+                        xlnx,reset-msr-ice = <0x0>;
+                        xlnx,reset-msr-ie = <0x0>;
+                        xlnx,sco = <0x0>;
+                        xlnx,trace = <0x0>;
+                        xlnx,unaligned-exceptions = <0x1>;
+                        xlnx,use-barrel = <0x1>;
+                        xlnx,use-branch-target-cache = <0x0>;
+                        xlnx,use-config-reset = <0x0>;
+                        xlnx,use-dcache = <0x1>;
+                        xlnx,use-div = <0x1>;
+                        xlnx,use-ext-brk = <0x0>;
+                        xlnx,use-ext-nm-brk = <0x0>;
+                        xlnx,use-extended-fsl-instr = <0x0>;
+                        xlnx,use-fpu = <0x0>;
+                        xlnx,use-hw-mul = <0x2>;
+                        xlnx,use-icache = <0x1>;
+                        xlnx,use-interrupt = <0x2>;
+                        xlnx,use-mmu = <0x3>;
+                        xlnx,use-msr-instr = <0x1>;
+                        xlnx,use-non-secure = <0x0>;
+                        xlnx,use-pcmp-instr = <0x1>;
+                        xlnx,use-reorder-instr = <0x1>;
+                        xlnx,use-stack-protection = <0x0>;
+                };
+        };
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                clk_cpu: clk_cpu@0 {
+                        #clock-cells = <0>;
+                        clock-frequency = <200000000>;
+                        clock-output-names = "clk_cpu";
+                        compatible = "fixed-clock";
+                        reg = <0>;
+                };
+                clk_bus_0: clk_bus_0@1 {
+                        #clock-cells = <0>;
+                        clock-frequency = <200000000>;
+                        clock-output-names = "clk_bus_0";
+                        compatible = "fixed-clock";
+                        reg = <1>;
+                };
+        };
+        amba_pl: amba_pl {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                ranges ;
+                axi_ethernet: ethernet@40c00000 {
+                        axistream-connected = <&axi_ethernet_dma>;
+                        axistream-control-connected = <&axi_ethernet_dma>;
+                        clock-frequency = <100000000>;
+                        compatible = "xlnx,axi-ethernet-1.00.a";
+                        device_type = "network";
+                        interrupt-parent = <&microblaze_0_axi_intc>;
+                        interrupts = <4 2>;
+                        phy-mode = "gmii";
+                        reg = <0x40c00000 0x40000>;
+                        xlnx = <0x0>;
+                        xlnx,axiliteclkrate = <0x0>;
+                        xlnx,axisclkrate = <0x0>;
+                        xlnx,clockselection = <0x0>;
+                        xlnx,enableasyncsgmii = <0x0>;
+                        xlnx,gt-type = <0x0>;
+                        xlnx,gtinex = <0x0>;
+                        xlnx,gtlocation = <0x0>;
+                        xlnx,gtrefclksrc = <0x0>;
+                        xlnx,include-dre ;
+                        xlnx,instantiatebitslice0 = <0x0>;
+                        xlnx,phy-type = <0x1>;
+                        xlnx,phyaddr = <0x1>;
+                        xlnx,rable = <0x0>;
+                        xlnx,rxcsum = <0x0>;
+                        xlnx,rxlane0-placement = <0x0>;
+                        xlnx,rxlane1-placement = <0x0>;
+                        xlnx,rxmem = <0x1000>;
+                        xlnx,rxnibblebitslice0used = <0x0>;
+                        xlnx,tx-in-upper-nibble = <0x1>;
+                        xlnx,txcsum = <0x0>;
+                        xlnx,txlane0-placement = <0x0>;
+                        xlnx,txlane1-placement = <0x0>;
+                        axi_ethernet_mdio: mdio {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+                };
+                axi_ethernet_dma: dma@41e00000 {
+                        #dma-cells = <1>;
+                        axistream-connected = <&axi_ethernet>;
+                        axistream-control-connected = <&axi_ethernet>;
+                        clock-frequency = <200000000>;
+                        clock-names = "s_axi_lite_aclk";
+                        clocks = <&clk_bus_0>;
+                        compatible = "xlnx,eth-dma";
+                        interrupt-parent = <&microblaze_0_axi_intc>;
+                        interrupts = <3 2 2 2>;
+                        reg = <0x41e00000 0x10000>;
+                        xlnx,include-dre ;
+                };
+                axi_timer_0: timer@41c00000 {
+                        clock-frequency = <200000000>;
+                        clocks = <&clk_bus_0>;
+                        compatible = "xlnx,xps-timer-1.00.a";
+                        interrupt-parent = <&microblaze_0_axi_intc>;
+                        interrupts = <5 2>;
+                        reg = <0x41c00000 0x10000>;
+                        xlnx,count-width = <0x20>;
+                        xlnx,gen0-assert = <0x1>;
+                        xlnx,gen1-assert = <0x1>;
+                        xlnx,one-timer-only = <0x0>;
+                        xlnx,trig0-assert = <0x1>;
+                        xlnx,trig1-assert = <0x1>;
+                };
+                calib_complete_gpio: gpio@40010000 {
+                        #gpio-cells = <2>;
+                        compatible = "xlnx,xps-gpio-1.00.a";
+                        gpio-controller ;
+                        reg = <0x40010000 0x10000>;
+                        xlnx,all-inputs = <0x1>;
+                        xlnx,all-inputs-2 = <0x0>;
+                        xlnx,all-outputs = <0x0>;
+                        xlnx,all-outputs-2 = <0x0>;
+                        xlnx,dout-default = <0x00000000>;
+                        xlnx,dout-default-2 = <0x00000000>;
+                        xlnx,gpio-width = <0x1>;
+                        xlnx,gpio2-width = <0x20>;
+                        xlnx,interrupt-present = <0x0>;
+                        xlnx,is-dual = <0x0>;
+                        xlnx,tri-default = <0xFFFFFFFF>;
+                        xlnx,tri-default-2 = <0xFFFFFFFF>;
+                };
+                dip_switches_4bits: gpio@40020000 {
+                        #gpio-cells = <2>;
+                        compatible = "xlnx,xps-gpio-1.00.a";
+                        gpio-controller ;
+                        reg = <0x40020000 0x10000>;
+                        xlnx,all-inputs = <0x1>;
+                        xlnx,all-inputs-2 = <0x0>;
+                        xlnx,all-outputs = <0x0>;
+                        xlnx,all-outputs-2 = <0x0>;
+                        xlnx,dout-default = <0x00000000>;
+                        xlnx,dout-default-2 = <0x00000000>;
+                        xlnx,gpio-width = <0x4>;
+                        xlnx,gpio2-width = <0x20>;
+                        xlnx,interrupt-present = <0x0>;
+                        xlnx,is-dual = <0x0>;
+                        xlnx,tri-default = <0xFFFFFFFF>;
+                        xlnx,tri-default-2 = <0xFFFFFFFF>;
+                };
+                iic_main: i2c@40800000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        clock-frequency = <200000000>;
+                        clocks = <&clk_bus_0>;
+                        compatible = "xlnx,xps-iic-2.00.a";
+                        interrupt-parent = <&microblaze_0_axi_intc>;
+                        interrupts = <1 2>;
+                        reg = <0x40800000 0x10000>;
+                };
+                led_8bits: gpio@40030000 {
+                        #gpio-cells = <2>;
+                        compatible = "xlnx,xps-gpio-1.00.a";
+                        gpio-controller ;
+                        reg = <0x40030000 0x10000>;
+                        xlnx,all-inputs = <0x0>;
+                        xlnx,all-inputs-2 = <0x0>;
+                        xlnx,all-outputs = <0x1>;
+                        xlnx,all-outputs-2 = <0x0>;
+                        xlnx,dout-default = <0x00000000>;
+                        xlnx,dout-default-2 = <0x00000000>;
+                        xlnx,gpio-width = <0x8>;
+                        xlnx,gpio2-width = <0x20>;
+                        xlnx,interrupt-present = <0x0>;
+                        xlnx,is-dual = <0x0>;
+                        xlnx,tri-default = <0xFFFFFFFF>;
+                        xlnx,tri-default-2 = <0xFFFFFFFF>;
+                };
+                linear_flash: flash@60000000 {
+                        bank-width = <2>;
+                        compatible = "cfi-flash";
+                        reg = <0x60000000 0x8000000>;
+                        xlnx,axi-clk-period-ps = <0x1388>;
+                        xlnx,include-datawidth-matching-0 = <0x1>;
+                        xlnx,include-datawidth-matching-1 = <0x1>;
+                        xlnx,include-datawidth-matching-2 = <0x1>;
+                        xlnx,include-datawidth-matching-3 = <0x1>;
+                        xlnx,include-negedge-ioregs = <0x0>;
+                        xlnx,lflash-period-ps = <0x1388>;
+                        xlnx,linear-flash-sync-burst = <0x0>;
+                        xlnx,max-mem-width = <0x10>;
+                        xlnx,mem-a-lsb = <0x0>;
+                        xlnx,mem-a-msb = <0x1f>;
+                        xlnx,mem0-type = <0x2>;
+                        xlnx,mem0-width = <0x10>;
+                        xlnx,mem1-type = <0x0>;
+                        xlnx,mem1-width = <0x10>;
+                        xlnx,mem2-type = <0x0>;
+                        xlnx,mem2-width = <0x10>;
+                        xlnx,mem3-type = <0x0>;
+                        xlnx,mem3-width = <0x10>;
+                        xlnx,num-banks-mem = <0x1>;
+                        xlnx,page-size = <0x10>;
+                        xlnx,parity-type-mem-0 = <0x0>;
+                        xlnx,parity-type-mem-1 = <0x0>;
+                        xlnx,parity-type-mem-2 = <0x0>;
+                        xlnx,parity-type-mem-3 = <0x0>;
+                        xlnx,port-diff = <0x0>;
+                        xlnx,s-axi-en-reg = <0x0>;
+                        xlnx,s-axi-mem-addr-width = <0x20>;
+                        xlnx,s-axi-mem-data-width = <0x20>;
+                        xlnx,s-axi-mem-id-width = <0x1>;
+                        xlnx,s-axi-reg-addr-width = <0x5>;
+                        xlnx,s-axi-reg-data-width = <0x20>;
+                        xlnx,synch-pipedelay-0 = <0x1>;
+                        xlnx,synch-pipedelay-1 = <0x1>;
+                        xlnx,synch-pipedelay-2 = <0x1>;
+                        xlnx,synch-pipedelay-3 = <0x1>;
+                        xlnx,tavdv-ps-mem-0 = <0x1fbd0>;
+                        xlnx,tavdv-ps-mem-1 = <0x3a98>;
+                        xlnx,tavdv-ps-mem-2 = <0x3a98>;
+                        xlnx,tavdv-ps-mem-3 = <0x3a98>;
+                        xlnx,tcedv-ps-mem-0 = <0x1fbd0>;
+                        xlnx,tcedv-ps-mem-1 = <0x3a98>;
+                        xlnx,tcedv-ps-mem-2 = <0x3a98>;
+                        xlnx,tcedv-ps-mem-3 = <0x3a98>;
+                        xlnx,thzce-ps-mem-0 = <0x88b8>;
+                        xlnx,thzce-ps-mem-1 = <0x1b58>;
+                        xlnx,thzce-ps-mem-2 = <0x1b58>;
+                        xlnx,thzce-ps-mem-3 = <0x1b58>;
+                        xlnx,thzoe-ps-mem-0 = <0x1b58>;
+                        xlnx,thzoe-ps-mem-1 = <0x1b58>;
+                        xlnx,thzoe-ps-mem-2 = <0x1b58>;
+                        xlnx,thzoe-ps-mem-3 = <0x1b58>;
+                        xlnx,tlzwe-ps-mem-0 = <0xc350>;
+                        xlnx,tlzwe-ps-mem-1 = <0x0>;
+                        xlnx,tlzwe-ps-mem-2 = <0x0>;
+                        xlnx,tlzwe-ps-mem-3 = <0x0>;
+                        xlnx,tpacc-ps-flash-0 = <0x61a8>;
+                        xlnx,tpacc-ps-flash-1 = <0x61a8>;
+                        xlnx,tpacc-ps-flash-2 = <0x61a8>;
+                        xlnx,tpacc-ps-flash-3 = <0x61a8>;
+                        xlnx,twc-ps-mem-0 = <0x11170>;
+                        xlnx,twc-ps-mem-1 = <0x3a98>;
+                        xlnx,twc-ps-mem-2 = <0x3a98>;
+                        xlnx,twc-ps-mem-3 = <0x3a98>;
+                        xlnx,twp-ps-mem-0 = <0x13880>;
+                        xlnx,twp-ps-mem-1 = <0x2ee0>;
+                        xlnx,twp-ps-mem-2 = <0x2ee0>;
+                        xlnx,twp-ps-mem-3 = <0x2ee0>;
+                        xlnx,twph-ps-mem-0 = <0x13880>;
+                        xlnx,twph-ps-mem-1 = <0x2ee0>;
+                        xlnx,twph-ps-mem-2 = <0x2ee0>;
+                        xlnx,twph-ps-mem-3 = <0x2ee0>;
+                        xlnx,use-startup = <0x0>;
+                        xlnx,use-startup-int = <0x0>;
+                        xlnx,wr-rec-time-mem-0 = <0x186a0>;
+                        xlnx,wr-rec-time-mem-1 = <0x6978>;
+                        xlnx,wr-rec-time-mem-2 = <0x6978>;
+                        xlnx,wr-rec-time-mem-3 = <0x6978>;
+                };
+                microblaze_0_axi_intc: interrupt-controller@41200000 {
+                        #interrupt-cells = <2>;
+                        compatible = "xlnx,xps-intc-1.00.a";
+                        interrupt-controller ;
+                        reg = <0x41200000 0x10000>;
+                        xlnx,kind-of-intr = <0x0>;
+                        xlnx,num-intr-inputs = <0x6>;
+                };
+                push_buttons_5bits: gpio@40040000 {
+                        #gpio-cells = <2>;
+                        compatible = "xlnx,xps-gpio-1.00.a";
+                        gpio-controller ;
+                        reg = <0x40040000 0x10000>;
+                        xlnx,all-inputs = <0x1>;
+                        xlnx,all-inputs-2 = <0x0>;
+                        xlnx,all-outputs = <0x0>;
+                        xlnx,all-outputs-2 = <0x0>;
+                        xlnx,dout-default = <0x00000000>;
+                        xlnx,dout-default-2 = <0x00000000>;
+                        xlnx,gpio-width = <0x5>;
+                        xlnx,gpio2-width = <0x20>;
+                        xlnx,interrupt-present = <0x0>;
+                        xlnx,is-dual = <0x0>;
+                        xlnx,tri-default = <0xFFFFFFFF>;
+                        xlnx,tri-default-2 = <0xFFFFFFFF>;
+                };
+                reset_gpio: gpio@40000000 {
+                        #gpio-cells = <2>;
+                        compatible = "xlnx,xps-gpio-1.00.a";
+                        gpio-controller ;
+                        reg = <0x40000000 0x10000>;
+                        xlnx,all-inputs = <0x0>;
+                        xlnx,all-inputs-2 = <0x0>;
+                        xlnx,all-outputs = <0x1>;
+                        xlnx,all-outputs-2 = <0x0>;
+                        xlnx,dout-default = <0x00000000>;
+                        xlnx,dout-default-2 = <0x00000000>;
+                        xlnx,gpio-width = <0x1>;
+                        xlnx,gpio2-width = <0x20>;
+                        xlnx,interrupt-present = <0x0>;
+                        xlnx,is-dual = <0x0>;
+                        xlnx,tri-default = <0xFFFFFFFF>;
+                        xlnx,tri-default-2 = <0xFFFFFFFF>;
+                };
+                rs232_uart: serial@44a00000 {
+                        clock-frequency = <200000000>;
+                        clocks = <&clk_bus_0>;
+                        compatible = "xlnx,xps-uart16550-2.00.a", "ns16550a";
+                        current-speed = <115200>;
+                        device_type = "serial";
+                        interrupt-parent = <&microblaze_0_axi_intc>;
+                        interrupts = <0 2>;
+                        port-number = <0>;
+                        reg = <0x44a00000 0x10000>;
+                        reg-offset = <0x1000>;
+                        reg-shift = <2>;
+                        xlnx,external-xin-clk-hz = <0x17d7840>;
+                        xlnx,external-xin-clk-hz-d = <0x19>;
+                        xlnx,has-external-rclk = <0x0>;
+                        xlnx,has-external-xin = <0x0>;
+                        xlnx,is-a-16550 = <0x1>;
+                        xlnx,s-axi-aclk-freq-hz-d = "200.0";
+                        xlnx,use-modem-ports = <0x1>;
+                        xlnx,use-user-ports = <0x1>;
+                };
+        };
+};
diff --git a/meta-xilinx-core/recipes-bsp/device-tree/files/kc705-microblazeel/system-conf.dtsi b/meta-xilinx-core/recipes-bsp/device-tree/files/kc705-microblazeel/system-conf.dtsi
new file mode 100644
index 00000000..09b26c6a
--- /dev/null
+++ b/meta-xilinx-core/recipes-bsp/device-tree/files/kc705-microblazeel/system-conf.dtsi
@@ -0,0 +1,43 @@
+/*
+ * CAUTION: This file is automatically generated by PetaLinux SDK.
+ * DO NOT modify this file
+ */
+
+
+/ {
+        chosen {
+                bootargs = "console=ttyS0,115200 earlyprintk";
+                stdout-path = "serial0:115200n8";
+        };
+};
+
+&axi_ethernet {
+        local-mac-address = [00 0a 35 00 22 01];
+};
+
+&linear_flash {
+        reg = <0x60000000 0x08000000>;
+        #address-cells = <1>;
+        #size-cells = <1>;
+        partition@0x00000000 {
+                label = "fpga";
+                reg = <0x00000000 0x00b00000>;
+        };
+        partition@0x00b00000 {
+                label = "boot";
+                reg = <0x00b00000 0x00080000>;
+        };
+        partition@0x00b80000 {
+                label = "bootenv";
+                reg = <0x00b80000 0x00020000>;
+        };
+        partition@0x00ba0000 {
+                label = "kernel";
+                reg = <0x00ba0000 0x00c00000>;
+        };
+        partition@0x017a0000 {
+                label = "spare";
+                reg = <0x017a0000 0x00000000>;
+        };
+};
+
diff --git a/meta-xilinx-core/recipes-bsp/device-tree/files/picozed-zynq7.dts b/meta-xilinx-core/recipes-bsp/device-tree/files/picozed-zynq7.dts
new file mode 100644
index 00000000..6f9b653a
--- /dev/null
+++ b/meta-xilinx-core/recipes-bsp/device-tree/files/picozed-zynq7.dts
@@ -0,0 +1,98 @@
+/dts-v1/;
+/include/ "zynq-7000.dtsi"
+/include/ "zynq-7000-qspi-dummy.dtsi"
+
+/ {
+        model = "Avnet picoZed";
+        compatible = "avnet,picozed", "xlnx,zynq-7000";
+
+        aliases {
+                ethernet0 = &gem0;
+                serial0 = &uart1;
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x0 0x40000000>;
+        };
+
+        chosen {
+                bootargs = "earlyprintk";
+                stdout-path = "serial0:115200n8";
+        };
+
+        usb_phy0: phy0 {
+                compatible = "usb-nop-xceiv";
+                #phy-cells = <0>;
+                reset-gpios = <&gpio0 7 1>; /* MIO 7, GPIO_ACTIVE_LOW */
+        };
+};
+
+&gem0 {
+        status = "okay";
+        phy-mode = "rgmii-id";
+        phy-handle = <&ethernet_phy>;
+
+        ethernet_phy: ethernet-phy@0 {
+                compatible = "marvell,88e1512", "marvell,88e1510";
+                device_type = "ethernet-phy";
+                reg = <0>;
+        };
+};
+
+&sdhci1 {
+        status = "okay";
+        /* SD1 is onnected to a non-removable eMMC flash device */
+        non-removable;
+};
+
+&uart1 {
+        status = "okay";
+};
+
+&usb0 {
+        status = "okay";
+        dr_mode = "host";
+        usb-phy = <&usb_phy0>;
+};
+
+&qspi {
+        status = "okay";
+        primary_flash: ps7-qspi@0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "micron,m25p80", "spansion,s25fl128s", "jedec,spi-nor";
+                reg = <0x0>;
+                spi-max-frequency = <50000000>;
+                /* Example 16M partition table using U-Boot + U-Boot SPL */
+                partition@0x0 {
+                        label = "boot";
+                        reg = <0x0 0xe0000>;
+                };
+                partition@0xe0000 {
+                        label = "ubootenv";
+                        reg = <0xe0000 0x20000>;
+                };
+                partition@0x100000 {
+                        label = "uboot";
+                        reg = <0x100000 0x100000>;
+                };
+                partition@0x200000 {
+                        label = "kernel";
+                        reg = <0x200000 0x4f0000>;
+                };
+                partition@0x6f0000 {
+                        label = "devicetree";
+                        reg = <0x6f0000 0x10000>;
+                };
+                partition@0x700000 {
+                        label = "rootfs";
+                        reg = <0x700000 0x400000>;
+                };
+                partition@0xb00000 {
+                        label = "spare";
+                        reg = <0xb00000 0x500000>;
+                };
+        };
+};
+
diff --git a/meta-xilinx-core/recipes-bsp/device-tree/files/qemu-zynq7.dts b/meta-xilinx-core/recipes-bsp/device-tree/files/qemu-zynq7.dts
new file mode 100644
index 00000000..cd0694d6
--- /dev/null
+++ b/meta-xilinx-core/recipes-bsp/device-tree/files/qemu-zynq7.dts
@@ -0,0 +1,85 @@
+/dts-v1/;
+/include/ "zynq-7000.dtsi"
+/include/ "zynq-7000-qspi-dummy.dtsi"
+
+/ {
+        model = "Zynq A9 QEMU";
+        compatible = "qemu,xilinx-zynq-a9", "xlnx,zynq-7000";
+
+        aliases {
+                ethernet0 = &gem0;
+                serial0 = &uart1;
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x0 0x40000000>;
+        };
+
+        chosen {
+                bootargs = "earlyprintk";
+                stdout-path = "serial0:115200n8";
+        };
+};
+
+&amba {
+        /* Setup a fixed 25 MHz clock (100Mbps) to trick the ethernet driver */
+        fixednetclk: clock {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <25000000>;
+        };
+};
+
+&gem0 {
+        status = "okay";
+        clocks = <&clkc 30>, <&clkc 30>, <&fixednetclk>, <&fixednetclk>, <&clkc 30>;
+        phy-mode = "rgmii-id";
+        phy-handle = <&ethernet_phy>;
+
+        ethernet_phy: ethernet-phy@23 {
+                device_type = "ethernet-phy";
+                reg = <23>;
+        };
+};
+
+&sdhci0 {
+        status = "okay";
+};
+
+&uart1 {
+        status = "okay";
+};
+
+&qspi {
+        status = "okay";
+        is-dual = <1>;
+        primary_flash: ps7-qspi@0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "st,m25p80";
+                reg = <0x0>;
+                spi-max-frequency = <50000000>;
+                partition@0x00000000 {
+                        label = "boot";
+                        reg = <0x00000000 0x00500000>;
+                };
+                partition@0x00500000 {
+                        label = "bootenv";
+                        reg = <0x00500000 0x00020000>;
+                };
+                partition@0x00520000 {
+                        label = "config";
+                        reg = <0x00520000 0x00020000>;
+                };
+                partition@0x00540000 {
+                        label = "image";
+                        reg = <0x00540000 0x00a80000>;
+                };
+                partition@0x00fc0000 {
+                        label = "spare";
+                        reg = <0x00fc0000 0x00000000>;
+                };
+        };
+};
+
diff --git a/meta-xilinx-core/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pcw.dtsi b/meta-xilinx-core/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pcw.dtsi
new file mode 100644
index 00000000..0f678d39
--- /dev/null
+++ b/meta-xilinx-core/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pcw.dtsi
@@ -0,0 +1,63 @@
+/*
+ * CAUTION: This file is automatically generated by Xilinx.
+ * Version: HSI 2015.4
+ * Today is: Fri Mar  4 15:40:49 2016
+*/
+
+
+/ {
+        cpus {
+                cpu@0 {
+                        operating-points = <650000 1000000 325000 1000000>;
+                };
+        };
+};
+&gem0 {
+        phy-mode = "rgmii-id";
+        status = "okay";
+        xlnx,ptp-enet-clock = <0x6750918>;
+};
+&gpio0 {
+        emio-gpio-width = <64>;
+        gpio-mask-high = <0x0>;
+        gpio-mask-low = <0x5600>;
+};
+&i2c0 {
+        clock-frequency = <400000>;
+        status = "okay";
+};
+&i2c1 {
+        clock-frequency = <400000>;
+        status = "okay";
+};
+&intc {
+        num_cpus = <2>;
+        num_interrupts = <96>;
+};
+&qspi {
+        is-dual = <0>;
+        num-cs = <1>;
+        status = "okay";
+};
+&sdhci0 {
+        status = "okay";
+        xlnx,has-cd = <0x1>;
+        xlnx,has-power = <0x0>;
+        xlnx,has-wp = <0x1>;
+};
+&uart1 {
+        current-speed = <115200>;
+        device_type = "serial";
+        port-number = <0>;
+        status = "okay";
+};
+&usb0 {
+        dr_mode = "host";
+        phy_type = "ulpi";
+        status = "okay";
+        usb-reset = <&gpio0 46 0>;
+};
+&clkc {
+        fclk-enable = <0x3>;
+        ps-clk-frequency = <50000000>;
+};
diff --git a/meta-xilinx-core/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pl.dtsi b/meta-xilinx-core/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pl.dtsi
new file mode 100644
index 00000000..32bc7688
--- /dev/null
+++ b/meta-xilinx-core/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/pl.dtsi
@@ -0,0 +1,215 @@
+/*
+ * CAUTION: This file is automatically generated by Xilinx.
+ * Version: HSI 2015.4
+ * Today is: Fri Mar  4 15:40:49 2016
+*/
+
+
+/ {
+        amba_pl: amba_pl {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                ranges ;
+                axi_dynclk_0: axi_dynclk@43c10000 {
+                        compatible = "xlnx,axi-dynclk-1.0";
+                        reg = <0x43c10000 0x10000>;
+                        xlnx,s00-axi-addr-width = <0x5>;
+                        xlnx,s00-axi-data-width = <0x20>;
+                };
+                axi_gpio_btn: gpio@41210000 {
+                        #gpio-cells = <2>;
+                        compatible = "xlnx,xps-gpio-1.00.a";
+                        gpio-controller ;
+                        reg = <0x41210000 0x10000>;
+                        xlnx,all-inputs = <0x1>;
+                        xlnx,all-inputs-2 = <0x0>;
+                        xlnx,all-outputs = <0x0>;
+                        xlnx,all-outputs-2 = <0x0>;
+                        xlnx,dout-default = <0x00000000>;
+                        xlnx,dout-default-2 = <0x00000000>;
+                        xlnx,gpio-width = <0x4>;
+                        xlnx,gpio2-width = <0x20>;
+                        xlnx,interrupt-present = <0x0>;
+                        xlnx,is-dual = <0x0>;
+                        xlnx,tri-default = <0xFFFFFFFF>;
+                        xlnx,tri-default-2 = <0xFFFFFFFF>;
+                };
+                axi_gpio_hdmi: gpio@41230000 {
+                        #gpio-cells = <2>;
+                        compatible = "xlnx,xps-gpio-1.00.a";
+                        gpio-controller ;
+                        interrupt-parent = <&intc>;
+                        interrupts = <0 29 4>;
+                        reg = <0x41230000 0x10000>;
+                        xlnx,all-inputs = <0x1>;
+                        xlnx,all-inputs-2 = <0x0>;
+                        xlnx,all-outputs = <0x0>;
+                        xlnx,all-outputs-2 = <0x0>;
+                        xlnx,dout-default = <0x00000000>;
+                        xlnx,dout-default-2 = <0x00000000>;
+                        xlnx,gpio-width = <0x1>;
+                        xlnx,gpio2-width = <0x20>;
+                        xlnx,interrupt-present = <0x1>;
+                        xlnx,is-dual = <0x0>;
+                        xlnx,tri-default = <0xFFFFFFFF>;
+                        xlnx,tri-default-2 = <0xFFFFFFFF>;
+                };
+                axi_gpio_led: gpio@41200000 {
+                        #gpio-cells = <2>;
+                        compatible = "xlnx,xps-gpio-1.00.a";
+                        gpio-controller ;
+                        reg = <0x41200000 0x10000>;
+                        xlnx,all-inputs = <0x0>;
+                        xlnx,all-inputs-2 = <0x0>;
+                        xlnx,all-outputs = <0x1>;
+                        xlnx,all-outputs-2 = <0x0>;
+                        xlnx,dout-default = <0x00000000>;
+                        xlnx,dout-default-2 = <0x00000000>;
+                        xlnx,gpio-width = <0x4>;
+                        xlnx,gpio2-width = <0x20>;
+                        xlnx,interrupt-present = <0x0>;
+                        xlnx,is-dual = <0x0>;
+                        xlnx,tri-default = <0xFFFFFFFF>;
+                        xlnx,tri-default-2 = <0xFFFFFFFF>;
+                };
+                axi_gpio_sw: gpio@41220000 {
+                        #gpio-cells = <2>;
+                        compatible = "xlnx,xps-gpio-1.00.a";
+                        gpio-controller ;
+                        reg = <0x41220000 0x10000>;
+                        xlnx,all-inputs = <0x1>;
+                        xlnx,all-inputs-2 = <0x0>;
+                        xlnx,all-outputs = <0x0>;
+                        xlnx,all-outputs-2 = <0x0>;
+                        xlnx,dout-default = <0x00000000>;
+                        xlnx,dout-default-2 = <0x00000000>;
+                        xlnx,gpio-width = <0x4>;
+                        xlnx,gpio2-width = <0x20>;
+                        xlnx,interrupt-present = <0x0>;
+                        xlnx,is-dual = <0x0>;
+                        xlnx,tri-default = <0xFFFFFFFF>;
+                        xlnx,tri-default-2 = <0xFFFFFFFF>;
+                };
+                axi_i2s_adi_0: axi_i2s_adi@43c20000 {
+                        compatible = "xlnx,axi-i2s-adi-1.0";
+                        reg = <0x43c20000 0x10000>;
+                        xlnx,bclk-pol = <0x0>;
+                        xlnx,dma-type = <0x1>;
+                        xlnx,has-rx = <0x1>;
+                        xlnx,has-tx = <0x1>;
+                        xlnx,lrclk-pol = <0x0>;
+                        xlnx,num-ch = <0x1>;
+                        xlnx,s-axi-min-size = <0x000001FF>;
+                        xlnx,slot-width = <0x18>;
+                };
+                axi_vdma_0: dma@43000000 {
+                        #dma-cells = <1>;
+                        compatible = "xlnx,axi-vdma-1.00.a";
+                        clocks = <&clkc 15>;
+                        clock-names = "s_axi_lite_aclk";
+                        interrupt-parent = <&intc>;
+                        interrupts = <0 30 4>;
+                        reg = <0x43000000 0x10000>;
+                        xlnx,flush-fsync = <0x1>;
+                        xlnx,num-fstores = <0x1>;
+                        dma-channel@43000000 {
+                                compatible = "xlnx,axi-vdma-mm2s-channel";
+                                interrupts = <0 30 4>;
+                                xlnx,datawidth = <0x20>;
+                                xlnx,device-id = <0x0>;
+                        };
+                };
+                v_tc_0: v_tc@43c00000 {
+                        compatible = "xlnx,v-tc-6.1";
+                        interrupt-parent = <&intc>;
+                        interrupts = <0 31 4>;
+                        reg = <0x43c00000 0x10000>;
+                        xlnx,det-achroma-en = <0x0>;
+                        xlnx,det-avideo-en = <0x1>;
+                        xlnx,det-fieldid-en = <0x0>;
+                        xlnx,det-hblank-en = <0x1>;
+                        xlnx,det-hsync-en = <0x1>;
+                        xlnx,det-vblank-en = <0x1>;
+                        xlnx,det-vsync-en = <0x1>;
+                        xlnx,detect-en = <0x0>;
+                        xlnx,fsync-hstart0 = <0x0>;
+                        xlnx,fsync-hstart1 = <0x0>;
+                        xlnx,fsync-hstart10 = <0x0>;
+                        xlnx,fsync-hstart11 = <0x0>;
+                        xlnx,fsync-hstart12 = <0x0>;
+                        xlnx,fsync-hstart13 = <0x0>;
+                        xlnx,fsync-hstart14 = <0x0>;
+                        xlnx,fsync-hstart15 = <0x0>;
+                        xlnx,fsync-hstart2 = <0x0>;
+                        xlnx,fsync-hstart3 = <0x0>;
+                        xlnx,fsync-hstart4 = <0x0>;
+                        xlnx,fsync-hstart5 = <0x0>;
+                        xlnx,fsync-hstart6 = <0x0>;
+                        xlnx,fsync-hstart7 = <0x0>;
+                        xlnx,fsync-hstart8 = <0x0>;
+                        xlnx,fsync-hstart9 = <0x0>;
+                        xlnx,fsync-vstart0 = <0x0>;
+                        xlnx,fsync-vstart1 = <0x0>;
+                        xlnx,fsync-vstart10 = <0x0>;
+                        xlnx,fsync-vstart11 = <0x0>;
+                        xlnx,fsync-vstart12 = <0x0>;
+                        xlnx,fsync-vstart13 = <0x0>;
+                        xlnx,fsync-vstart14 = <0x0>;
+                        xlnx,fsync-vstart15 = <0x0>;
+                        xlnx,fsync-vstart2 = <0x0>;
+                        xlnx,fsync-vstart3 = <0x0>;
+                        xlnx,fsync-vstart4 = <0x0>;
+                        xlnx,fsync-vstart5 = <0x0>;
+                        xlnx,fsync-vstart6 = <0x0>;
+                        xlnx,fsync-vstart7 = <0x0>;
+                        xlnx,fsync-vstart8 = <0x0>;
+                        xlnx,fsync-vstart9 = <0x0>;
+                        xlnx,gen-achroma-en = <0x0>;
+                        xlnx,gen-achroma-polarity = <0x1>;
+                        xlnx,gen-auto-switch = <0x0>;
+                        xlnx,gen-avideo-en = <0x1>;
+                        xlnx,gen-avideo-polarity = <0x1>;
+                        xlnx,gen-cparity = <0x0>;
+                        xlnx,gen-f0-vblank-hend = <0x500>;
+                        xlnx,gen-f0-vblank-hstart = <0x500>;
+                        xlnx,gen-f0-vframe-size = <0x2ee>;
+                        xlnx,gen-f0-vsync-hend = <0x500>;
+                        xlnx,gen-f0-vsync-hstart = <0x500>;
+                        xlnx,gen-f0-vsync-vend = <0x2d9>;
+                        xlnx,gen-f0-vsync-vstart = <0x2d4>;
+                        xlnx,gen-f1-vblank-hend = <0x500>;
+                        xlnx,gen-f1-vblank-hstart = <0x500>;
+                        xlnx,gen-f1-vframe-size = <0x2ee>;
+                        xlnx,gen-f1-vsync-hend = <0x500>;
+                        xlnx,gen-f1-vsync-hstart = <0x500>;
+                        xlnx,gen-f1-vsync-vend = <0x2d9>;
+                        xlnx,gen-f1-vsync-vstart = <0x2d4>;
+                        xlnx,gen-fieldid-en = <0x0>;
+                        xlnx,gen-fieldid-polarity = <0x1>;
+                        xlnx,gen-hactive-size = <0x500>;
+                        xlnx,gen-hblank-en = <0x1>;
+                        xlnx,gen-hblank-polarity = <0x1>;
+                        xlnx,gen-hframe-size = <0x672>;
+                        xlnx,gen-hsync-en = <0x1>;
+                        xlnx,gen-hsync-end = <0x596>;
+                        xlnx,gen-hsync-polarity = <0x1>;
+                        xlnx,gen-hsync-start = <0x56e>;
+                        xlnx,gen-interlaced = <0x0>;
+                        xlnx,gen-vactive-size = <0x2d0>;
+                        xlnx,gen-vblank-en = <0x1>;
+                        xlnx,gen-vblank-polarity = <0x1>;
+                        xlnx,gen-video-format = <0x2>;
+                        xlnx,gen-vsync-en = <0x1>;
+                        xlnx,gen-vsync-polarity = <0x1>;
+                        xlnx,generate-en = <0x1>;
+                        xlnx,has-axi4-lite = <0x1>;
+                        xlnx,has-intc-if = <0x0>;
+                        xlnx,interlace-en = <0x0>;
+                        xlnx,max-lines = <0x1000>;
+                        xlnx,max-pixels = <0x1000>;
+                        xlnx,num-fsyncs = <0x1>;
+                        xlnx,sync-en = <0x0>;
+                };
+        };
+};
diff --git a/meta-xilinx-core/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/zybo-linux-bd-zynq7.dts b/meta-xilinx-core/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/zybo-linux-bd-zynq7.dts
new file mode 100644
index 00000000..19654392
--- /dev/null
+++ b/meta-xilinx-core/recipes-bsp/device-tree/files/zybo-linux-bd-zynq7/zybo-linux-bd-zynq7.dts
@@ -0,0 +1,184 @@
+/dts-v1/;
+/include/ "skeleton.dtsi"
+/include/ "zynq-7000.dtsi"
+/include/ "zynq-7000-qspi-dummy.dtsi"
+/include/ "pcw.dtsi"
+/include/ "pl.dtsi"
+
+/ {
+        model = "Digilent-Zybo-Linux-BD-v2015.4";
+        aliases {
+                serial0 = &uart1;
+                ethernet0 = &gem0;
+                spi0 = &qspi;
+        };
+        chosen {
+                bootargs = "";
+                stdout-path = "serial0:115200n8";
+        };
+        memory {
+                device_type = "memory";
+                reg = <0x0 0x20000000>;
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                autorepeat;
+                btn4 {
+                        label = "btn4";
+                        gpios = <&gpio0 50 0>;
+                        linux,code = <108>; /* down */
+                        gpio-key,wakeup;
+                        autorepeat;
+                };
+                btn5 {
+                        label = "btn5";
+                        gpios = <&gpio0 51 0>;
+                        linux,code = <103>; /* up */
+                        gpio-key,wakeup;
+                        autorepeat;
+                };
+        };
+
+        usb_phy0: usb_phy@0 {
+                compatible = "usb-nop-xceiv";
+                #phy-cells = <0>;
+                reset-gpios = <&gpio0 46 1>;
+        };
+};
+
+&amba {
+        u-boot,dm-pre-reloc;
+};
+
+&amba_pl {
+        encoder_0: digilent_encoder {
+                compatible = "digilent,drm-encoder";
+                dglnt,edid-i2c = <&i2c1>;
+        };
+
+        xilinx_drm {
+                compatible = "xlnx,drm";
+                xlnx,vtc = <&v_tc_0>;
+                xlnx,connector-type = "HDMIA";
+                xlnx,encoder-slave = <&encoder_0>;
+                clocks = <&axi_dynclk_0>;
+                planes {
+                        xlnx,pixel-format = "xrgb8888";
+                        plane0 {
+                                dmas = <&axi_vdma_0 0>;
+                                dma-names = "dma0";
+                        };
+                };
+        };
+
+        i2s_clk: i2s_clk {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <12288000>;
+                clock-output-names = "i2s_clk";
+        };
+
+        sound {
+                compatible = "simple-audio-card";
+                simple-audio-card,name = "ZYBO-Sound-Card";
+                simple-audio-card,format = "i2s";
+                simple-audio-card,bitclock-master = <&dailink0_master>;
+                simple-audio-card,frame-master = <&dailink0_master>;
+                simple-audio-card,widgets =
+                        "Microphone", "Microphone Jack",
+                        "Headphone", "Headphone Jack",
+                        "Line", "Line In Jack";
+                simple-audio-card,routing =
+                        "MICIN", "Microphone Jack",
+                        "Headphone Jack", "LHPOUT",
+                        "Headphone Jack", "RHPOUT",
+                        "LLINEIN", "Line In Jack",
+                        "RLINEIN", "Line In Jack";
+                dailink0_master: simple-audio-card,cpu {
+                        clocks = <&i2s_clk>;
+                        sound-dai = <&axi_i2s_adi_0>;
+                };
+                simple-audio-card,codec {
+                        clocks = <&i2s_clk>;
+                        sound-dai = <&ssm2603>;
+                };
+        };
+};
+
+&axi_dynclk_0 {
+        compatible = "digilent,axi-dynclk";
+        #clock-cells = <0>;
+        clocks = <&clkc 15>;
+};
+
+&axi_i2s_adi_0 {
+        #sound-dai-cells = <0>;
+        compatible = "adi,axi-i2s-1.00.a";
+        clocks = <&clkc 15>, <&i2s_clk>;
+        clock-names = "axi", "ref";
+        dmas = <&dmac_s 0 &dmac_s 1>;
+        dma-names = "tx", "rx";
+};
+
+&gem0 {
+        phy-handle = <&phy0>;
+        phy-mode = "rgmii-id";
+        local-mac-address = [];
+        phy0: phy@0 {
+                device_type = "ethernet-phy";
+                reg = <0>;
+        };
+};
+
+&i2c0 {
+        eeprom@50 {
+                /* Microchip 24AA02E48 */
+                compatible = "microchip,24c02";
+                reg = <0x50>;
+        };
+
+        ssm2603: ssm2603@1a{
+                #sound-dai-cells = <0>;
+                compatible = "adi,ssm2603";
+                reg = <0x1a>;
+        };
+};
+
+&qspi {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        flash0: flash@0 {
+                compatible = "micron,m25p80", "s25fl128s";
+                reg = <0x0>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                spi-max-frequency = <50000000>;
+                partition@0x00000000 {
+                        label = "boot";
+                        reg = <0x00000000 0x00300000>;
+                };
+                partition@0x00300000 {
+                        label = "bootenv";
+                        reg = <0x00300000 0x00020000>;
+                };
+                partition@0x00320000 {
+                        label = "kernel";
+                        reg = <0x00320000 0x00a80000>;
+                };
+                partition@0x00da0000 {
+                        label = "spare";
+                        reg = <0x00da0000 0x00000000>;
+                };
+        };
+};
+
+&usb0 {
+        usb-phy = <&usb_phy0>;
+};
+
+&v_tc_0 {
+        compatible = "xlnx,v-tc-5.01.a";
+};
diff --git a/meta-xilinx-core/recipes-bsp/device-tree/files/zynq-7000-qspi-dummy.dtsi b/meta-xilinx-core/recipes-bsp/device-tree/files/zynq-7000-qspi-dummy.dtsi
new file mode 100644
index 00000000..d059a2da
--- /dev/null
+++ b/meta-xilinx-core/recipes-bsp/device-tree/files/zynq-7000-qspi-dummy.dtsi
@@ -0,0 +1,4 @@
+&amba {
+        /* empty defintion for kernels that don't have qspi node */
+        qspi: spi@e000d000 { };
+};
diff --git a/meta-xilinx-core/recipes-bsp/embeddedsw/fsbl.bb b/meta-xilinx-core/recipes-bsp/embeddedsw/fsbl.bb
new file mode 100644
index 00000000..2fa71309
--- /dev/null
+++ b/meta-xilinx-core/recipes-bsp/embeddedsw/fsbl.bb
@@ -0,0 +1,60 @@
+DESCRIPTION = "Xilinx First Stage Boot Loader"
+
+LICENSE = "MIT"
+
+PROVIDES = "virtual/fsbl"
+
+INHERIT_DEFAULT_DEPENDS = "1"
+
+COMPATIBLE_MACHINE = "^$"
+COMPATIBLE_MACHINE:zynq = "zynq"
+COMPATIBLE_MACHINE:zynqmp = "zynqmp"
+
+# Specify a default in case boardvariant isn't available
+BOARDVARIANT_ARCH ??= "${MACHINE_ARCH}"
+PACKAGE_ARCH = "${BOARDVARIANT_ARCH}"
+
+# Default would be a multiconfig (versal) build
+# For this to work, BBMULTICONFIG += "fsbl-fw" must be in the user's local.conf!
+FSBL_DEPENDS ??= ""
+FSBL_MCDEPENDS ??= "mc::fsbl-fw:fsbl-firmware:do_deploy"
+
+# This must be defined to the file output by whatever is providing the fsbl-firmware
+# The following sets the default, but the BSP may select a different name
+FSBL_IMAGE_NAME ??= "fsbl"
+FSBL_DEPLOY_DIR ??= "${TOPDIR}/tmp-fsbl-fw/deploy/images/${MACHINE}"
+
+# Default is for the multilib case (without the extension .elf/.bin)
+FSBL_FILE ??= "${FSBL_DEPLOY_DIR}/${FSBL_IMAGE_NAME}"
+FSBL_FILE[vardepsexclude] = "FSBL_DEPLOY_DIR"
+
+do_fetch[depends] += "${FSBL_DEPENDS}"
+do_fetch[mcdepends] += "${FSBL_MCDEPENDS}"
+
+inherit deploy
+
+do_install() {
+    if [ ! -e ${FSBL_FILE}.elf ]; then
+        echo "Unable to find FSBL_FILE (${FSBL_FILE}.elf)"
+        exit 1
+    fi
+
+    install -Dm 0644 ${FSBL_FILE}.elf ${D}/boot/${PN}.elf
+}
+
+# If the item is already in OUR deploy_image_dir, nothing to deploy!
+SHOULD_DEPLOY = "${@'false' if (d.getVar('FSBL_FILE')).startswith(d.getVar('DEPLOY_DIR_IMAGE')) else 'true'}"
+do_deploy() {
+    # If the item is already in OUR deploy_image_dir, nothing to deploy!
+    if ${SHOULD_DEPLOY}; then
+        install -Dm 0644 ${FSBL_FILE}.elf ${DEPLOYDIR}/${FSBL_IMAGE_NAME}.elf
+    fi
+}
+
+addtask deploy before do_build after do_install
+
+INSANE_SKIP:${PN} = "arch"
+INSANE_SKIP:${PN}-dbg = "arch"
+
+SYSROOT_DIRS += "/boot"
+FILES:${PN} = "/boot/${PN}.elf"
diff --git a/meta-xilinx-core/recipes-bsp/embeddedsw/plmfw.bb b/meta-xilinx-core/recipes-bsp/embeddedsw/plmfw.bb
new file mode 100644
index 00000000..70d234c9
--- /dev/null
+++ b/meta-xilinx-core/recipes-bsp/embeddedsw/plmfw.bb
@@ -0,0 +1,61 @@
+DESCRIPTION = "Platform Loader and Manager"
+SUMMARY = "Platform Loader and Manager for Versal devices"
+
+LICENSE = "MIT"
+
+PROVIDES = "virtual/plm"
+
+INHERIT_DEFAULT_DEPENDS = "1"
+
+COMPATIBLE_MACHINE = "^$"
+COMPATIBLE_MACHINE:versal = "versal"
+
+# Specify a default in case boardvariant isn't available
+BOARDVARIANT_ARCH ??= "${MACHINE_ARCH}"
+PACKAGE_ARCH = "${BOARDVARIANT_ARCH}"
+
+# Default would be a multiconfig (versal) build
+# For this to work, BBMULTICONFIG += "versal-fw" must be in the user's local.conf!
+PLM_DEPENDS ??= ""
+PLM_MCDEPENDS ??= "mc::versal-fw:plm-firmware:do_deploy"
+
+# This must be defined to the file output by whatever is providing the plm-firmware
+# The following sets the default, but the BSP may select a different name
+PLM_IMAGE_NAME ??= "plm-versal-mb"
+PLM_DEPLOY_DIR ??= "${TOPDIR}/tmp-microblaze-versal-fw/deploy/images/${MACHINE}"
+
+# Default is for the multilib case (without the extension .elf/.bin)
+PLM_FILE ??= "${PLM_DEPLOY_DIR}/${PLM_IMAGE_NAME}"
+PLM_FILE[vardepsexclude] = "PLM_DEPLOY_DIR"
+
+do_fetch[depends] += "${PLM_DEPENDS}"
+do_fetch[mcdepends] += "${PLM_MCDEPENDS}"
+
+inherit deploy
+
+do_install() {
+    if [ ! -e ${PLM_FILE}.elf ]; then
+        echo "Unable to find PLM_FILE (${PLM_FILE}.elf)"
+        exit 1
+    fi
+
+    install -Dm 0644 ${PLM_FILE}.elf ${D}/boot/${PN}.elf
+}
+
+# If the item is already in OUR deploy_image_dir, nothing to deploy!
+SHOULD_DEPLOY = "${@'false' if (d.getVar('PLM_FILE')).startswith(d.getVar('DEPLOY_DIR_IMAGE')) else 'true'}"
+do_deploy() {
+    # If the item is already in OUR deploy_image_dir, nothing to deploy!
+    if ${SHOULD_DEPLOY}; then
+        install -Dm 0644 ${PLM_FILE}.elf ${DEPLOYDIR}/${PLM_IMAGE_NAME}.elf
+        install -Dm 0644 ${PLM_FILE}.bin ${DEPLOYDIR}/${PLM_IMAGE_NAME}.bin
+    fi
+}
+
+addtask deploy before do_build after do_install
+
+INSANE_SKIP:${PN} = "arch"
+INSANE_SKIP:${PN}-dbg = "arch"
+
+SYSROOT_DIRS += "/boot"
+FILES:${PN} = "/boot/${PN}.elf"
diff --git a/meta-xilinx-core/recipes-bsp/embeddedsw/pmufw.bb b/meta-xilinx-core/recipes-bsp/embeddedsw/pmufw.bb
new file mode 100644
index 00000000..7371127c
--- /dev/null
+++ b/meta-xilinx-core/recipes-bsp/embeddedsw/pmufw.bb
@@ -0,0 +1,59 @@
+DESCRIPTION = "PMU Firmware"
+
+LICENSE = "MIT"
+
+PROVIDES = "virtual/pmu-firmware"
+
+INHERIT_DEFAULT_DEPENDS = "1"
+
+COMPATIBLE_MACHINE = "^$"
+COMPATIBLE_MACHINE:zynqmp = "zynqmp"
+
+# Specify a default in case boardvariant isn't available
+BOARDVARIANT_ARCH ??= "${MACHINE_ARCH}"
+PACKAGE_ARCH = "${BOARDVARIANT_ARCH}"
+
+# Default would be a multiconfig (zynqmp-pmufw) build
+# For this to work, BBMULTICONFIG += "zynqmp-pmufw" must be in the user's local.conf!
+PMU_DEPENDS ??= ""
+PMU_MCDEPENDS ??= "mc::zynqmp-pmufw:pmu-firmware:do_deploy"
+
+# This must be defined to the file output by whatever is providing the pmu-firmware
+# The following sets the default, but the BSP may select a different name
+PMU_FIRMWARE_IMAGE_NAME ??= "pmu-firmware-zynqmp-pmu"
+PMU_FIRMWARE_DEPLOY_DIR ??= "${TOPDIR}/tmp-microblaze-zynqmp-pmufw/deploy/images/${MACHINE}"
+
+# Default is for the multilib case (without the extension .elf/.bin)
+PMU_FILE ??= "${PMU_FIRMWARE_DEPLOY_DIR}/${PMU_FIRMWARE_IMAGE_NAME}"
+PMU_FILE[vardepsexclude] = "PMU_FIRMWARE_DEPLOY_DIR"
+
+do_fetch[depends] += "${PMU_DEPENDS}"
+do_fetch[mcdepends] += "${PMU_MCDEPENDS}"
+
+inherit deploy
+
+do_install() {
+    if [ ! -e ${PMU_FILE}.elf ]; then
+        echo "Unable to find PMU_FILE (${PMU_FILE}.elf)"
+        exit 1
+    fi
+
+    install -Dm 0644 ${PMU_FILE}.elf ${D}/boot/${PN}.elf
+}
+
+# If the item is already in OUR deploy_image_dir, nothing to deploy!
+SHOULD_DEPLOY = "${@'false' if (d.getVar('PMU_FILE')).startswith(d.getVar('DEPLOY_DIR_IMAGE')) else 'true'}"
+do_deploy() {
+    if ${SHOULD_DEPLOY}; then
+        install -Dm 0644 ${PMU_FILE}.elf ${DEPLOYDIR}/${PMU_FIRMWARE_IMAGE_NAME}.elf
+        install -Dm 0644 ${PMU_FILE}.bin ${DEPLOYDIR}/${PMU_FIRMWARE_IMAGE_NAME}.bin
+    fi
+}
+
+addtask deploy before do_build after do_install
+
+INSANE_SKIP:${PN} = "arch"
+INSANE_SKIP:${PN}-dbg = "arch"
+
+SYSROOT_DIRS += "/boot"
+FILES:${PN} = "/boot/${PN}.elf"
diff --git a/meta-xilinx-core/recipes-bsp/embeddedsw/psmfw.bb b/meta-xilinx-core/recipes-bsp/embeddedsw/psmfw.bb
new file mode 100644
index 00000000..5a885b3b
--- /dev/null
+++ b/meta-xilinx-core/recipes-bsp/embeddedsw/psmfw.bb
@@ -0,0 +1,61 @@
+DESCRIPTION = "PSM Firmware"
+SUMMARY = "PSM firmware for versal devices"
+
+LICENSE = "MIT"
+
+PROVIDES = "virtual/psm-firmware"
+
+INHERIT_DEFAULT_DEPENDS = "1"
+
+COMPATIBLE_MACHINE = "^$"
+COMPATIBLE_MACHINE:versal = "versal"
+
+# Specify a default in case boardvariant isn't available
+BOARDVARIANT_ARCH ??= "${MACHINE_ARCH}"
+PACKAGE_ARCH = "${BOARDVARIANT_ARCH}"
+
+# Default would be a multiconfig (versal) build
+# For this to work, BBMULTICONFIG += "versal-fw" must be in the user's local.conf!
+PSM_DEPENDS ??= ""
+PSM_MCDEPENDS ??= "mc::versal-fw:psm-firmware:do_deploy"
+
+# This must be defined to the file output by whatever is providing the psm-firmware
+# The following sets the default, but the BSP may select a different name
+PSM_FIRMWARE_IMAGE_NAME ??= "psm-firmware-versal-mb"
+PSM_FIRMWARE_DEPLOY_DIR ??= "${TOPDIR}/tmp-microblaze-versal-fw/deploy/images/${MACHINE}"
+
+# Default is for the multilib case (without the extension .elf/.bin)
+PSM_FILE ??= "${PSM_FIRMWARE_DEPLOY_DIR}/${PSM_FIRMWARE_IMAGE_NAME}"
+PSM_FILE[vardepsexclude] = "PSM_FIRMWARE_DEPLOY_DIR"
+
+do_fetch[depends] += "${PSM_DEPENDS}"
+do_fetch[mcdepends] += "${PSM_MCDEPENDS}"
+
+inherit deploy
+
+do_install() {
+    if [ ! -e ${PSM_FILE}.elf ]; then
+        echo "Unable to find PSM_FILE (${PSM_FILE}.elf)"
+        exit 1
+    fi
+
+    install -Dm 0644 ${PSM_FILE}.elf ${D}/boot/${PN}.elf
+}
+
+# If the item is already in OUR deploy_image_dir, nothing to deploy!
+SHOULD_DEPLOY = "${@'false' if (d.getVar('PSM_FILE')).startswith(d.getVar('DEPLOY_DIR_IMAGE')) else 'true'}"
+do_deploy() {
+    # If the item is already in OUR deploy_image_dir, nothing to deploy!
+    if ${SHOULD_DEPLOY}; then
+        install -Dm 0644 ${PSM_FILE}.elf ${DEPLOYDIR}/${PSM_FIRMWARE_IMAGE_NAME}.elf
+        install -Dm 0644 ${PSM_FILE}.bin ${DEPLOYDIR}/${PSM_FIRMWARE_IMAGE_NAME}.bin
+    fi
+}
+
+addtask deploy before do_build after do_install
+
+INSANE_SKIP:${PN} = "arch"
+INSANE_SKIP:${PN}-dbg = "arch"
+
+SYSROOT_DIRS += "/boot"
+FILES:${PN} = "/boot/${PN}.elf"
diff --git a/meta-xilinx-core/recipes-bsp/platform-init/platform-init.bb b/meta-xilinx-core/recipes-bsp/platform-init/platform-init.bb
new file mode 100644
index 00000000..cac8bbfc
--- /dev/null
+++ b/meta-xilinx-core/recipes-bsp/platform-init/platform-init.bb
@@ -0,0 +1,38 @@
+SUMMARY = "Xilinx Platform Headers"
+DESCRPTION = "Xilinx ps*_init_gpl.c/h platform init code, used for building u-boot-spl and fsbl"
+HOMEPAGE = "http://www.xilinx.com"
+SECTION = "bsp"
+
+INHIBIT_DEFAULT_DEPS = "1"
+
+PACKAGE_ARCH = "${MACHINE_ARCH}"
+
+inherit xilinx-platform-init
+
+COMPATIBLE_MACHINE = "$^"
+COMPATIBLE_MACHINE_picozed-zynq7 = "picozed-zynq7"
+
+LICENSE = "GPLv2+"
+LIC_FILES_CHKSUM = "file://${COREBASE}/meta/files/common-licenses/GPL-2.0;md5=801f80980d171dd6425610833a22dbe6"
+
+PROVIDES += "virtual/xilinx-platform-init"
+
+SRC_URI = "${@" ".join(["file://%s" % f for f in (d.getVar('PLATFORM_INIT_FILES') or "").split()])}"
+
+S = "${WORKDIR}"
+
+SYSROOT_DIRS += "${PLATFORM_INIT_DIR}"
+
+do_compile() {
+        :
+}
+
+do_install() {
+        install -d ${D}${PLATFORM_INIT_DIR}
+        for i in ${PLATFORM_INIT_FILES}; do
+                install -m 0644 ${S}/$i ${D}${PLATFORM_INIT_DIR}/
+        done
+}
+
+FILES:${PN} += "${PLATFORM_INIT_DIR}/*"
+
diff --git a/meta-xilinx-core/recipes-bsp/platform-init/platform-init/picozed-zynq7/ps7_init_gpl.c b/meta-xilinx-core/recipes-bsp/platform-init/platform-init/picozed-zynq7/ps7_init_gpl.c
new file mode 100644
index 00000000..5587ab25
--- /dev/null
+++ b/meta-xilinx-core/recipes-bsp/platform-init/platform-init/picozed-zynq7/ps7_init_gpl.c
@@ -0,0 +1,13191 @@
+/******************************************************************************
+* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+*
+*  This program is free software; you can redistribute it and/or modify
+*  it under the terms of the GNU General Public License as published by
+*  the Free Software Foundation; either version 2 of the License, or
+*  (at your option) any later version.
+*
+*  This program is distributed in the hope that it will be useful,
+*  but WITHOUT ANY WARRANTY; without even the implied warranty of
+*  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+*  GNU General Public License for more details.
+* 
+*  You should have received a copy of the GNU General Public License along
+*  with this program; if not, see <http://www.gnu.org/licenses/>
+*
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init_gpl.c
+*
+* This file is automatically generated 
+*
+*****************************************************************************/
+
+#include "ps7_init_gpl.h"
+
+unsigned long ps7_pll_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x4
+    // .. .. ==> 0XF8000110[7:4] = 0x00000004U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000040U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x3c
+    // .. .. .. ==> 0XF8000100[18:12] = 0x0000003CU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0003C000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0003C000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000003U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000300U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000300U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0x4
+    // .. .. ==> 0XF8000118[7:4] = 0x00000004U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000040U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000118[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x3c
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000003CU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0003C000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0003C000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0x23
+    // .. ==> 0XF8000128[13:8] = 0x00000023U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002300U
+    // .. DIVISOR1 = 0x3
+    // .. ==> 0XF8000128[25:20] = 0x00000003U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x10
+    // .. ==> 0XF8000140[13:8] = 0x00000010U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001000U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000140[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00101001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF800014C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800014C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0xa
+    // .. ==> 0XF800014C[13:8] = 0x0000000AU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. 
+    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000A01U),
+    // .. CLKACT0 = 0x0
+    // .. ==> 0XF8000150[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000150[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x28
+    // .. ==> 0XF8000150[13:8] = 0x00000028U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002800U
+    // .. 
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00002802U),
+    // .. CLKACT0 = 0x0
+    // .. ==> 0XF8000154[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x28
+    // .. ==> 0XF8000154[13:8] = 0x00000028U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002800U
+    // .. 
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00002802U),
+    // .. .. START: TRACE CLOCK
+    // .. .. FINISH: TRACE CLOCK
+    // .. .. CLKACT = 0x1
+    // .. .. ==> 0XF8000168[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000168[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR = 0xa
+    // .. .. ==> 0XF8000168[13:8] = 0x0000000AU
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000A01U),
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000170[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF8000170[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000170[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000180[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF8000180[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000180[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000190[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x3c
+    // .. .. ==> 0XF8000190[13:8] = 0x0000003CU
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00003C00U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000190[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00103C00U),
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x28
+    // .. .. ==> 0XF80001A0[13:8] = 0x00000028U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00002800U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00102800U),
+    // .. .. CLK_621_TRUE = 0x1
+    // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. .. DMA_CPU_2XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. USB0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[2:2] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. USB1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. GEM0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[6:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. .. GEM1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. SDI0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. SDI1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[11:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000800U
+    // .. .. SPI0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. SPI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. CAN0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. CAN1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. I2C0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[18:18] = 0x00000001U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. .. I2C1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. UART0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. UART1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. GPIO_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[22:22] = 0x00000001U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[23:23] = 0x00000001U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. .. SMC_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[24:24] = 0x00000001U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC084DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_3_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reserved_reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1a
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001AU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001AU
+    // .. .. reg_ddrc_t_rfc_min = 0xa0
+    // .. .. ==> 0XF8006014[13:6] = 0x000000A0U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00002800U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x16
+    // .. .. ==> 0XF8006018[15:10] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00005800U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x13
+    // .. .. ==> 0XF8006018[26:22] = 0x00000013U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x04C00000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x6
+    // .. .. ==> 0XF8006020[7:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
+    // .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006048, 0x0003F03FU ,0x0003C008U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
+    // .. .. ==> 0XF8006078[3:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
+    // .. .. ==> 0XF8006078[7:4] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U
+    // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
+    // .. .. ==> 0XF8006078[11:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_t_cksre = 0x6
+    // .. .. ==> 0XF8006078[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_t_cksrx = 0x6
+    // .. .. ==> 0XF8006078[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_t_ckesr = 0x4
+    // .. .. ==> 0XF8006078[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+    // .. .. reg_ddrc_t_ckpde = 0x2
+    // .. .. ==> 0XF800607C[3:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_ckpdx = 0x2
+    // .. .. ==> 0XF800607C[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. reg_ddrc_t_ckdpde = 0x2
+    // .. .. ==> 0XF800607C[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_ckdpdx = 0x2
+    // .. .. ==> 0XF800607C[15:12] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U
+    // .. .. reg_ddrc_t_ckcsx = 0x3
+    // .. .. ==> 0XF800607C[19:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. START: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+    // .. .. FINISH: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF800612C[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xa1
+    // .. .. ==> 0XF800612C[19:10] = 0x000000A1U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00028400U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00028400U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006130[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xa0
+    // .. .. ==> 0XF8006130[19:10] = 0x000000A0U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00028000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00028000U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x7
+    // .. .. ==> 0XF8006134[9:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000007U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xad
+    // .. .. ==> 0XF8006134[19:10] = 0x000000ADU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002B400U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002B407U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x7
+    // .. .. ==> 0XF8006138[9:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000007U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xad
+    // .. .. ==> 0XF8006138[19:10] = 0x000000ADU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002B400U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0002B407U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c
+    // .. .. ==> 0XF8006154[9:0] = 0x0000007CU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000007CU
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000007CU),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c
+    // .. .. ==> 0XF8006158[9:0] = 0x0000007CU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000007CU
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x0000007CU),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x87
+    // .. .. ==> 0XF800615C[9:0] = 0x00000087U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000087U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000087U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x87
+    // .. .. ==> 0XF8006160[9:0] = 0x00000087U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000087U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000087U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xf6
+    // .. .. ==> 0XF8006168[10:0] = 0x000000F6U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F6U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F6U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xf5
+    // .. .. ==> 0XF800616C[10:0] = 0x000000F5U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F5U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F5U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x102
+    // .. .. ==> 0XF8006170[10:0] = 0x00000102U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000102U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000102U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x102
+    // .. .. ==> 0XF8006174[10:0] = 0x00000102U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000102U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000102U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xbc
+    // .. .. ==> 0XF800617C[9:0] = 0x000000BCU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000BCU
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000BCU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xbc
+    // .. .. ==> 0XF8006180[9:0] = 0x000000BCU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000BCU
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000BCU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc7
+    // .. .. ==> 0XF8006184[9:0] = 0x000000C7U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C7U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C7U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc7
+    // .. .. ==> 0XF8006188[9:0] = 0x000000C7U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C7U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C7U),
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. .. 
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. .. 
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCI_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. reserved_INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE_B = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCI_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. reserved_SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. reserved_DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. reserved_DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. reserved_SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. reserved_SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. reserved_GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. reserved_RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x1
+    // .. ==> 0XF8000B6C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_SEL = 0x4
+    // .. ==> 0XF8000B6C[4:1] = 0x00000004U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000008U
+    // .. VREF_EXT_EN = 0x0
+    // .. ==> 0XF8000B6C[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. reserved_VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. reserved_REFIO_TEST = 0x0
+    // .. ==> 0XF8000B6C[11:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000000U
+    // .. reserved_REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. reserved_DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. reserved_CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000209U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reserved_VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reserved_VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reserved_VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reserved_VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reserved_VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[15:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reserved_INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reserved_TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reserved_TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reserved_TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. reserved_TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reserved_INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000700[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000700[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000700[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000700[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000700[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000700[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000700[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000704[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000704[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000704[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000704[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000708[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000708[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000708[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800070C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800070C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800070C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000710[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000710[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000710[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000714[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000714[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000714[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000718[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000718[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000718[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800071C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000720[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000720[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000720[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000720[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000724[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000724[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000724[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000724[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000724[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000728[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000728[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF8000728[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000728[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000728[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000680U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800072C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF800072C[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800072C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800072C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000680U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000730[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000730[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF8000730[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000730[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000730[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000680U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000734[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000734[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF8000734[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000734[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000734[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000680U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000738[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000738[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000738[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000738[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF8000738[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000738[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000738[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000680U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800073C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800073C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800073C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800073C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF800073C[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800073C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800073C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000680U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000740[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000740[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000740[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000740[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000744[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000744[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000744[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000744[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000748[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000748[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000748[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000748[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800074C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800074C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800074C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800074C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000750[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000750[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000750[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000750[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000754[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000754[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000754[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000754[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000758[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000758[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000758[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800075C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800075C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800075C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000760[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000760[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000760[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000764[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000764[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000764[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000768[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000768[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000768[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800076C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800076C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800076C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000770[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000770[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000770[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000774[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000774[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000774[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000774[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000778[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000778[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000778[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800077C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800077C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800077C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800077C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000780[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000780[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000780[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000784[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000784[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000784[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000788[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000788[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000788[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800078C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800078C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800078C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000790[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000790[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000790[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000790[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000794[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000794[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000794[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000798[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000798[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000798[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800079C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800079C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800079C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007A0[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007A0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007A4[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007A4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007A8[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007A8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007AC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007AC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007AC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007B0[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007B0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007B4[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007B4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007B8[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007BC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007BC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007BC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007BC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007BC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007BC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C0[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C4[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007C8[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007CC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007CC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007CC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+    // .. SDIO1_CD_SEL = 58
+    // .. ==> 0XF8000834[21:16] = 0x0000003AU
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x003A0000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000834, 0x003F0000U ,0x003A0000U),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: UART REGISTERS
+    // .. BDIV = 0x6
+    // .. ==> 0XE0001034[7:0] = 0x00000006U
+    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
+    // .. 
+    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+    // .. CD = 0x3e
+    // .. ==> 0XE0001018[15:0] = 0x0000003EU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
+    // .. 
+    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
+    // .. STPBRK = 0x0
+    // .. ==> 0XE0001000[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. STTBRK = 0x0
+    // .. ==> 0XE0001000[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. RSTTO = 0x0
+    // .. ==> 0XE0001000[6:6] = 0x00000000U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. TXDIS = 0x0
+    // .. ==> 0XE0001000[5:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. TXEN = 0x1
+    // .. ==> 0XE0001000[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. RXDIS = 0x0
+    // .. ==> 0XE0001000[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. RXEN = 0x1
+    // .. ==> 0XE0001000[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. TXRES = 0x1
+    // .. ==> 0XE0001000[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. RXRES = 0x1
+    // .. ==> 0XE0001000[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. 
+    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+    // .. CHMODE = 0x0
+    // .. ==> 0XE0001004[9:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
+    // .. NBSTOP = 0x0
+    // .. ==> 0XE0001004[7:6] = 0x00000000U
+    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. PAR = 0x4
+    // .. ==> 0XE0001004[5:3] = 0x00000004U
+    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
+    // .. CHRL = 0x0
+    // .. ==> 0XE0001004[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. CLKS = 0x0
+    // .. ==> 0XE0001004[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U),
+    // .. FINISH: UART REGISTERS
+    // .. START: TPIU WIDTH IN CASE OF EMIO
+    // .. .. START: TRACE LOCK ACCESS REGISTER
+    // .. .. a = 0XC5ACCE55
+    // .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. FINISH: TRACE LOCK ACCESS REGISTER
+    // .. .. START: TRACE CURRENT PORT SIZE
+    // .. .. a = 2
+    // .. .. ==> 0XF8803004[31:0] = 0x00000002U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000002U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U),
+    // .. .. FINISH: TRACE CURRENT PORT SIZE
+    // .. .. START: TRACE LOCK ACCESS REGISTER
+    // .. .. a = 0X0
+    // .. .. ==> 0XF8803FB0[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. FINISH: TRACE LOCK ACCESS REGISTER
+    // .. FINISH: TPIU WIDTH IN CASE OF EMIO
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. 
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x80
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x80
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_3_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_LVL_INP_EN_0 = 1
+    // .. ==> 0XF8000900[3:3] = 0x00000001U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. USER_LVL_OUT_EN_0 = 1
+    // .. ==> 0XF8000900[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. USER_LVL_INP_EN_1 = 1
+    // .. ==> 0XF8000900[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. USER_LVL_OUT_EN_1 = 1
+    // .. ==> 0XF8000900[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. 
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: TPIU WIDTH IN CASE OF EMIO
+    // .. .. START: TRACE LOCK ACCESS REGISTER
+    // .. .. a = 0XC5ACCE55
+    // .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. FINISH: TRACE LOCK ACCESS REGISTER
+    // .. .. START: TRACE CURRENT PORT SIZE
+    // .. .. a = 2
+    // .. .. ==> 0XF8803004[31:0] = 0x00000002U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000002U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U),
+    // .. .. FINISH: TRACE CURRENT PORT SIZE
+    // .. .. START: TRACE LOCK ACCESS REGISTER
+    // .. .. a = 0X0
+    // .. .. ==> 0XF8803FB0[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. FINISH: TRACE LOCK ACCESS REGISTER
+    // .. FINISH: TPIU WIDTH IN CASE OF EMIO
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. reserved_FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. reserved_FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. reserved_FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. reserved_FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. reserved_FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. reserved_FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. reserved_FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_debug_3_0[] = {
+    // START: top
+    // .. START: CROSS TRIGGER CONFIGURATIONS
+    // .. .. START: UNLOCKING CTI REGISTERS
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. FINISH: UNLOCKING CTI REGISTERS
+    // .. .. START: ENABLING CTI MODULES AND CHANNELS
+    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_pll_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x4
+    // .. .. ==> 0XF8000110[7:4] = 0x00000004U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000040U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x3c
+    // .. .. .. ==> 0XF8000100[18:12] = 0x0000003CU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0003C000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0003C000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000003U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000300U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000300U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0x4
+    // .. .. ==> 0XF8000118[7:4] = 0x00000004U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000040U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000118[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x3c
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000003CU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0003C000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0003C000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0x23
+    // .. ==> 0XF8000128[13:8] = 0x00000023U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002300U
+    // .. DIVISOR1 = 0x3
+    // .. ==> 0XF8000128[25:20] = 0x00000003U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x10
+    // .. ==> 0XF8000140[13:8] = 0x00000010U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001000U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000140[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00101001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF800014C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800014C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0xa
+    // .. ==> 0XF800014C[13:8] = 0x0000000AU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. 
+    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000A01U),
+    // .. CLKACT0 = 0x0
+    // .. ==> 0XF8000150[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000150[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x28
+    // .. ==> 0XF8000150[13:8] = 0x00000028U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002800U
+    // .. 
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00002802U),
+    // .. CLKACT0 = 0x0
+    // .. ==> 0XF8000154[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x28
+    // .. ==> 0XF8000154[13:8] = 0x00000028U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002800U
+    // .. 
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00002802U),
+    // .. .. START: TRACE CLOCK
+    // .. .. FINISH: TRACE CLOCK
+    // .. .. CLKACT = 0x1
+    // .. .. ==> 0XF8000168[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000168[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR = 0xa
+    // .. .. ==> 0XF8000168[13:8] = 0x0000000AU
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000A01U),
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000170[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF8000170[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000170[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000180[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF8000180[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000180[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000190[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x3c
+    // .. .. ==> 0XF8000190[13:8] = 0x0000003CU
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00003C00U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000190[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00103C00U),
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x28
+    // .. .. ==> 0XF80001A0[13:8] = 0x00000028U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00002800U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00102800U),
+    // .. .. CLK_621_TRUE = 0x1
+    // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. .. DMA_CPU_2XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. USB0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[2:2] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. USB1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. GEM0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[6:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. .. GEM1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. SDI0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. SDI1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[11:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000800U
+    // .. .. SPI0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. SPI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. CAN0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. CAN1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. I2C0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[18:18] = 0x00000001U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. .. I2C1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. UART0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. UART1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. GPIO_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[22:22] = 0x00000001U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[23:23] = 0x00000001U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. .. SMC_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[24:24] = 0x00000001U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC084DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_2_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_block = 0x1
+    // .. .. ==> 0XF8006004[20:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
+    // .. .. ==> 0XF8006004[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
+    // .. .. ==> 0XF8006004[26:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_open_bank = 0x0
+    // .. .. ==> 0XF8006004[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+    // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1a
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001AU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001AU
+    // .. .. reg_ddrc_t_rfc_min = 0xa0
+    // .. .. ==> 0XF8006014[13:6] = 0x000000A0U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00002800U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x16
+    // .. .. ==> 0XF8006018[15:10] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00005800U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x13
+    // .. .. ==> 0XF8006018[26:22] = 0x00000013U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x04C00000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x6
+    // .. .. ==> 0XF8006020[7:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_sdram = 0x1
+    // .. .. ==> 0XF8006020[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_clock_stop_en = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_loopback = 0x0
+    // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_max_rank_rd = 0xf
+    // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_debug_mode = 0x0
+    // .. .. ==> 0XF8006038[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_level_start = 0x0
+    // .. .. ==> 0XF8006038[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_level_start = 0x0
+    // .. .. ==> 0XF8006038[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_dq0_wait_t = 0x0
+    // .. .. ==> 0XF8006038[12:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    // .. .. reg_ddrc_rank0_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank0_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
+    // .. .. reg_ddrc_rank1_rd_odt = 0x1
+    // .. .. ==> 0XF8006048[8:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U
+    // .. .. reg_ddrc_rank1_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[11:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. .. reg_ddrc_rank2_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[20:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank2_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[23:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[26:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[29:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
+    // .. .. ==> 0XF8006058[7:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
+    // .. .. ==> 0XF8006058[15:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1
+    // .. .. ==> 0XF8006078[3:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1
+    // .. .. ==> 0XF8006078[7:4] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000010U
+    // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1
+    // .. .. ==> 0XF8006078[11:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_t_cksre = 0x6
+    // .. .. ==> 0XF8006078[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_t_cksrx = 0x6
+    // .. .. ==> 0XF8006078[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_t_ckesr = 0x4
+    // .. .. ==> 0XF8006078[25:20] = 0x00000004U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00400000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U),
+    // .. .. reg_ddrc_t_ckpde = 0x2
+    // .. .. ==> 0XF800607C[3:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_ckpdx = 0x2
+    // .. .. ==> 0XF800607C[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. reg_ddrc_t_ckdpde = 0x2
+    // .. .. ==> 0XF800607C[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_ckdpdx = 0x2
+    // .. .. ==> 0XF800607C[15:12] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00002000U
+    // .. .. reg_ddrc_t_ckcsx = 0x3
+    // .. .. ==> 0XF800607C[19:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00030000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U),
+    // .. .. refresh_timer0_start_value_x32 = 0x0
+    // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U
+    // .. .. refresh_timer1_start_value_x32 = 0x8
+    // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_2t_delay = 0x0
+    // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. .. reg_ddrc_dis_pre_bypass = 0x0
+    // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. START: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+    // .. .. FINISH: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF800612C[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xa1
+    // .. .. ==> 0XF800612C[19:10] = 0x000000A1U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00028400U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00028400U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006130[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xa0
+    // .. .. ==> 0XF8006130[19:10] = 0x000000A0U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00028000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00028000U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x7
+    // .. .. ==> 0XF8006134[9:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000007U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xad
+    // .. .. ==> 0XF8006134[19:10] = 0x000000ADU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002B400U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002B407U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x7
+    // .. .. ==> 0XF8006138[9:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000007U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xad
+    // .. .. ==> 0XF8006138[19:10] = 0x000000ADU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002B400U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0002B407U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c
+    // .. .. ==> 0XF8006154[9:0] = 0x0000007CU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000007CU
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000007CU),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c
+    // .. .. ==> 0XF8006158[9:0] = 0x0000007CU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000007CU
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x0000007CU),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x87
+    // .. .. ==> 0XF800615C[9:0] = 0x00000087U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000087U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000087U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x87
+    // .. .. ==> 0XF8006160[9:0] = 0x00000087U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000087U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000087U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xf6
+    // .. .. ==> 0XF8006168[10:0] = 0x000000F6U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F6U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F6U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xf5
+    // .. .. ==> 0XF800616C[10:0] = 0x000000F5U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F5U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F5U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x102
+    // .. .. ==> 0XF8006170[10:0] = 0x00000102U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000102U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000102U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x102
+    // .. .. ==> 0XF8006174[10:0] = 0x00000102U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000102U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000102U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xbc
+    // .. .. ==> 0XF800617C[9:0] = 0x000000BCU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000BCU
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000BCU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xbc
+    // .. .. ==> 0XF8006180[9:0] = 0x000000BCU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000BCU
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000BCU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc7
+    // .. .. ==> 0XF8006184[9:0] = 0x000000C7U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C7U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C7U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc7
+    // .. .. ==> 0XF8006188[9:0] = 0x000000C7U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C7U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C7U),
+    // .. .. reg_phy_loopback = 0x0
+    // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+    // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_rank0_delays = 0x1
+    // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_phy_int_lpbk = 0x0
+    // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_per_bank_refresh = 0x0
+    // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. .. 
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. .. 
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x1
+    // .. ==> 0XF8000B6C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_SEL = 0x4
+    // .. ==> 0XF8000B6C[4:1] = 0x00000004U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000008U
+    // .. VREF_EXT_EN = 0x0
+    // .. ==> 0XF8000B6C[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. REFIO_TEST = 0x0
+    // .. ==> 0XF8000B6C[11:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000C00U    VAL : 0x00000000U
+    // .. REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000209U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000700[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000700[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000700[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000700[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000700[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000700[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000700[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000704[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000704[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000704[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000704[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000708[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000708[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000708[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800070C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800070C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800070C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000710[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000710[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000710[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000714[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000714[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000714[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000718[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000718[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000718[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800071C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000720[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000720[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000720[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000720[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000724[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000724[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000724[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000724[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000724[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000728[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000728[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF8000728[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000728[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000728[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000680U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800072C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF800072C[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800072C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800072C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000680U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000730[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000730[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF8000730[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000730[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000730[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000680U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000734[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000734[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF8000734[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000734[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000734[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000680U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000738[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000738[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000738[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000738[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF8000738[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000738[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000738[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000680U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800073C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800073C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800073C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800073C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF800073C[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800073C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800073C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000680U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000740[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000740[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000740[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000740[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000744[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000744[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000744[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000744[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000748[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000748[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000748[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000748[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800074C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800074C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800074C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800074C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000750[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000750[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000750[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000750[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000754[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000754[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000754[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000754[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000758[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000758[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000758[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800075C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800075C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800075C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000760[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000760[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000760[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000764[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000764[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000764[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000768[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000768[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000768[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800076C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800076C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800076C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000770[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000770[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000770[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000774[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000774[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000774[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000774[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000778[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000778[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000778[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800077C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800077C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800077C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800077C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000780[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000780[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000780[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000784[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000784[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000784[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000788[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000788[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000788[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800078C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800078C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800078C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000790[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000790[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000790[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000790[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000794[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000794[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000794[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000798[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000798[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000798[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800079C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800079C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800079C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007A0[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007A0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007A4[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007A4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007A8[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007A8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007AC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007AC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007AC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007B0[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007B0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007B4[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007B4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007B8[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007BC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007BC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007BC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007BC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007BC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007BC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C0[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C4[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007C8[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007CC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007CC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007CC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+    // .. SDIO1_CD_SEL = 58
+    // .. ==> 0XF8000834[21:16] = 0x0000003AU
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x003A0000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000834, 0x003F0000U ,0x003A0000U),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: UART REGISTERS
+    // .. BDIV = 0x6
+    // .. ==> 0XE0001034[7:0] = 0x00000006U
+    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
+    // .. 
+    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+    // .. CD = 0x3e
+    // .. ==> 0XE0001018[15:0] = 0x0000003EU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
+    // .. 
+    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
+    // .. STPBRK = 0x0
+    // .. ==> 0XE0001000[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. STTBRK = 0x0
+    // .. ==> 0XE0001000[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. RSTTO = 0x0
+    // .. ==> 0XE0001000[6:6] = 0x00000000U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. TXDIS = 0x0
+    // .. ==> 0XE0001000[5:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. TXEN = 0x1
+    // .. ==> 0XE0001000[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. RXDIS = 0x0
+    // .. ==> 0XE0001000[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. RXEN = 0x1
+    // .. ==> 0XE0001000[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. TXRES = 0x1
+    // .. ==> 0XE0001000[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. RXRES = 0x1
+    // .. ==> 0XE0001000[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. 
+    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+    // .. IRMODE = 0x0
+    // .. ==> 0XE0001004[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. UCLKEN = 0x0
+    // .. ==> 0XE0001004[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. CHMODE = 0x0
+    // .. ==> 0XE0001004[9:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
+    // .. NBSTOP = 0x0
+    // .. ==> 0XE0001004[7:6] = 0x00000000U
+    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. PAR = 0x4
+    // .. ==> 0XE0001004[5:3] = 0x00000004U
+    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
+    // .. CHRL = 0x0
+    // .. ==> 0XE0001004[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. CLKS = 0x0
+    // .. ==> 0XE0001004[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
+    // .. FINISH: UART REGISTERS
+    // .. START: TPIU WIDTH IN CASE OF EMIO
+    // .. .. START: TRACE LOCK ACCESS REGISTER
+    // .. .. a = 0XC5ACCE55
+    // .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. FINISH: TRACE LOCK ACCESS REGISTER
+    // .. .. START: TRACE CURRENT PORT SIZE
+    // .. .. a = 2
+    // .. .. ==> 0XF8803004[31:0] = 0x00000002U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000002U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U),
+    // .. .. FINISH: TRACE CURRENT PORT SIZE
+    // .. .. START: TRACE LOCK ACCESS REGISTER
+    // .. .. a = 0X0
+    // .. .. ==> 0XF8803FB0[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. FINISH: TRACE LOCK ACCESS REGISTER
+    // .. FINISH: TPIU WIDTH IN CASE OF EMIO
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. 
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x80
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x80
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_2_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_INP_ICT_EN_0 = 3
+    // .. ==> 0XF8000900[1:0] = 0x00000003U
+    // ..     ==> MASK : 0x00000003U    VAL : 0x00000003U
+    // .. USER_INP_ICT_EN_1 = 3
+    // .. ==> 0XF8000900[3:2] = 0x00000003U
+    // ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU
+    // .. 
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: TPIU WIDTH IN CASE OF EMIO
+    // .. .. START: TRACE LOCK ACCESS REGISTER
+    // .. .. a = 0XC5ACCE55
+    // .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. FINISH: TRACE LOCK ACCESS REGISTER
+    // .. .. START: TRACE CURRENT PORT SIZE
+    // .. .. a = 2
+    // .. .. ==> 0XF8803004[31:0] = 0x00000002U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000002U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U),
+    // .. .. FINISH: TRACE CURRENT PORT SIZE
+    // .. .. START: TRACE LOCK ACCESS REGISTER
+    // .. .. a = 0X0
+    // .. .. ==> 0XF8803FB0[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. FINISH: TRACE LOCK ACCESS REGISTER
+    // .. FINISH: TPIU WIDTH IN CASE OF EMIO
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_debug_2_0[] = {
+    // START: top
+    // .. START: CROSS TRIGGER CONFIGURATIONS
+    // .. .. START: UNLOCKING CTI REGISTERS
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. FINISH: UNLOCKING CTI REGISTERS
+    // .. .. START: ENABLING CTI MODULES AND CHANNELS
+    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_pll_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: PLL SLCR REGISTERS
+    // .. .. START: ARM PLL INIT
+    // .. .. PLL_RES = 0x4
+    // .. .. ==> 0XF8000110[7:4] = 0x00000004U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000040U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000110[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000110[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA240U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x3c
+    // .. .. .. ==> 0XF8000100[18:12] = 0x0000003CU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0003C000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0003C000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. ARM_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. SRCSEL = 0x0
+    // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. .. DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000120[13:8] = 0x00000003U
+    // .. .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000300U
+    // .. .. .. CPU_6OR4XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. .. CPU_3OR2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x02000000U    VAL : 0x02000000U
+    // .. .. .. CPU_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. .. CPU_1XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. .. CPU_PERI_CLKACT = 0x1
+    // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000300U),
+    // .. .. FINISH: ARM PLL INIT
+    // .. .. START: DDR PLL INIT
+    // .. .. PLL_RES = 0x2
+    // .. .. ==> 0XF8000114[7:4] = 0x00000002U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000020U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000114[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0x12c
+    // .. .. ==> 0XF8000114[21:12] = 0x0000012CU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x0012C000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x20
+    // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x00020000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. DDR_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. .. DDR_3XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. DDR_2XCLKACT = 0x1
+    // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. .. DDR_3XCLK_DIVISOR = 0x2
+    // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U
+    // .. .. ..     ==> MASK : 0x03F00000U    VAL : 0x00200000U
+    // .. .. .. DDR_2XCLK_DIVISOR = 0x3
+    // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U
+    // .. .. ..     ==> MASK : 0xFC000000U    VAL : 0x0C000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
+    // .. .. FINISH: DDR PLL INIT
+    // .. .. START: IO PLL INIT
+    // .. .. PLL_RES = 0x4
+    // .. .. ==> 0XF8000118[7:4] = 0x00000004U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000040U
+    // .. .. PLL_CP = 0x2
+    // .. .. ==> 0XF8000118[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. LOCK_CNT = 0xfa
+    // .. .. ==> 0XF8000118[21:12] = 0x000000FAU
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x000FA000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U),
+    // .. .. .. START: UPDATE FB_DIV
+    // .. .. .. PLL_FDIV = 0x3c
+    // .. .. .. ==> 0XF8000108[18:12] = 0x0000003CU
+    // .. .. ..     ==> MASK : 0x0007F000U    VAL : 0x0003C000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0003C000U),
+    // .. .. .. FINISH: UPDATE FB_DIV
+    // .. .. .. START: BY PASS PLL
+    // .. .. .. PLL_BYPASS_FORCE = 1
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
+    // .. .. .. FINISH: BY PASS PLL
+    // .. .. .. START: ASSERT RESET
+    // .. .. .. PLL_RESET = 1
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
+    // .. .. .. FINISH: ASSERT RESET
+    // .. .. .. START: DEASSERT RESET
+    // .. .. .. PLL_RESET = 0
+    // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
+    // .. .. .. FINISH: DEASSERT RESET
+    // .. .. .. START: CHECK PLL STATUS
+    // .. .. .. IO_PLL_LOCK = 1
+    // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U
+    // .. .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. .. 
+    EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+    // .. .. .. FINISH: CHECK PLL STATUS
+    // .. .. .. START: REMOVE PLL BY PASS
+    // .. .. .. PLL_BYPASS_FORCE = 0
+    // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U
+    // .. .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. .. 
+    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
+    // .. .. .. FINISH: REMOVE PLL BY PASS
+    // .. .. FINISH: IO PLL INIT
+    // .. FINISH: PLL SLCR REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_clock_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: CLOCK CONTROL SLCR REGISTERS
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000128[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. DIVISOR0 = 0x23
+    // .. ==> 0XF8000128[13:8] = 0x00000023U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002300U
+    // .. DIVISOR1 = 0x3
+    // .. ==> 0XF8000128[25:20] = 0x00000003U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00300000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000138[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000138[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF8000140[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000140[6:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. DIVISOR = 0x10
+    // .. ==> 0XF8000140[13:8] = 0x00000010U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00001000U
+    // .. DIVISOR1 = 0x1
+    // .. ==> 0XF8000140[25:20] = 0x00000001U
+    // ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00101001U),
+    // .. CLKACT = 0x1
+    // .. ==> 0XF800014C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF800014C[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0xa
+    // .. ==> 0XF800014C[13:8] = 0x0000000AU
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. 
+    EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000A01U),
+    // .. CLKACT0 = 0x0
+    // .. ==> 0XF8000150[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000150[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000150[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x28
+    // .. ==> 0XF8000150[13:8] = 0x00000028U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002800U
+    // .. 
+    EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00002802U),
+    // .. CLKACT0 = 0x0
+    // .. ==> 0XF8000154[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. CLKACT1 = 0x1
+    // .. ==> 0XF8000154[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. SRCSEL = 0x0
+    // .. ==> 0XF8000154[5:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. DIVISOR = 0x28
+    // .. ==> 0XF8000154[13:8] = 0x00000028U
+    // ..     ==> MASK : 0x00003F00U    VAL : 0x00002800U
+    // .. 
+    EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00002802U),
+    // .. .. START: TRACE CLOCK
+    // .. .. FINISH: TRACE CLOCK
+    // .. .. CLKACT = 0x1
+    // .. .. ==> 0XF8000168[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000168[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR = 0xa
+    // .. .. ==> 0XF8000168[13:8] = 0x0000000AU
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00000A00U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000A01U),
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000170[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF8000170[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000170[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U),
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000180[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x14
+    // .. .. ==> 0XF8000180[13:8] = 0x00000014U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00001400U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000180[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U),
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF8000190[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x3c
+    // .. .. ==> 0XF8000190[13:8] = 0x0000003CU
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00003C00U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF8000190[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00103C00U),
+    // .. .. SRCSEL = 0x0
+    // .. .. ==> 0XF80001A0[5:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000030U    VAL : 0x00000000U
+    // .. .. DIVISOR0 = 0x28
+    // .. .. ==> 0XF80001A0[13:8] = 0x00000028U
+    // .. ..     ==> MASK : 0x00003F00U    VAL : 0x00002800U
+    // .. .. DIVISOR1 = 0x1
+    // .. .. ==> 0XF80001A0[25:20] = 0x00000001U
+    // .. ..     ==> MASK : 0x03F00000U    VAL : 0x00100000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00102800U),
+    // .. .. CLK_621_TRUE = 0x1
+    // .. .. ==> 0XF80001C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U),
+    // .. .. DMA_CPU_2XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. USB0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[2:2] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. .. USB1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. GEM0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[6:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000040U
+    // .. .. GEM1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. SDI0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. SDI1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[11:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000800U
+    // .. .. SPI0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. SPI1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. CAN0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. CAN1_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. I2C0_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[18:18] = 0x00000001U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00040000U
+    // .. .. I2C1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. UART0_CPU_1XCLKACT = 0x0
+    // .. .. ==> 0XF800012C[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. UART1_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. GPIO_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[22:22] = 0x00000001U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00400000U
+    // .. .. LQSPI_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[23:23] = 0x00000001U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00800000U
+    // .. .. SMC_CPU_1XCLKACT = 0x1
+    // .. .. ==> 0XF800012C[24:24] = 0x00000001U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x01000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC084DU),
+    // .. FINISH: CLOCK CONTROL SLCR REGISTERS
+    // .. START: THIS SHOULD BE BLANK
+    // .. FINISH: THIS SHOULD BE BLANK
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_ddr_init_data_1_0[] = {
+    // START: top
+    // .. START: DDR INITIALIZATION
+    // .. .. START: LOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0
+    // .. .. ==> 0XF8006000[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 0x1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U),
+    // .. .. FINISH: LOCK DDR
+    // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81
+    // .. .. ==> 0XF8006004[11:0] = 0x00000081U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000081U
+    // .. .. reg_ddrc_active_ranks = 0x1
+    // .. .. ==> 0XF8006004[13:12] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00001000U
+    // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0
+    // .. .. ==> 0XF8006004[18:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0007C000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_block = 0x1
+    // .. .. ==> 0XF8006004[20:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00180000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0
+    // .. .. ==> 0XF8006004[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0
+    // .. .. ==> 0XF8006004[26:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_open_bank = 0x0
+    // .. .. ==> 0XF8006004[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_4bank_ram = 0x0
+    // .. .. ==> 0XF8006004[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U),
+    // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf
+    // .. .. ==> 0XF8006008[10:0] = 0x0000000FU
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x0000000FU
+    // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf
+    // .. .. ==> 0XF8006008[21:11] = 0x0000000FU
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00007800U
+    // .. .. reg_ddrc_hpr_xact_run_length = 0xf
+    // .. .. ==> 0XF8006008[25:22] = 0x0000000FU
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x03C00000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU),
+    // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF800600C[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2
+    // .. .. ==> 0XF800600C[21:11] = 0x00000002U
+    // .. ..     ==> MASK : 0x003FF800U    VAL : 0x00001000U
+    // .. .. reg_ddrc_lpr_xact_run_length = 0x8
+    // .. .. ==> 0XF800600C[25:22] = 0x00000008U
+    // .. ..     ==> MASK : 0x03C00000U    VAL : 0x02000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U),
+    // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1
+    // .. .. ==> 0XF8006010[10:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_w_xact_run_length = 0x8
+    // .. .. ==> 0XF8006010[14:11] = 0x00000008U
+    // .. ..     ==> MASK : 0x00007800U    VAL : 0x00004000U
+    // .. .. reg_ddrc_w_max_starve_x32 = 0x2
+    // .. .. ==> 0XF8006010[25:15] = 0x00000002U
+    // .. ..     ==> MASK : 0x03FF8000U    VAL : 0x00010000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U),
+    // .. .. reg_ddrc_t_rc = 0x1a
+    // .. .. ==> 0XF8006014[5:0] = 0x0000001AU
+    // .. ..     ==> MASK : 0x0000003FU    VAL : 0x0000001AU
+    // .. .. reg_ddrc_t_rfc_min = 0xa0
+    // .. .. ==> 0XF8006014[13:6] = 0x000000A0U
+    // .. ..     ==> MASK : 0x00003FC0U    VAL : 0x00002800U
+    // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10
+    // .. .. ==> 0XF8006014[20:14] = 0x00000010U
+    // .. ..     ==> MASK : 0x001FC000U    VAL : 0x00040000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281AU),
+    // .. .. reg_ddrc_wr2pre = 0x12
+    // .. .. ==> 0XF8006018[4:0] = 0x00000012U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000012U
+    // .. .. reg_ddrc_powerdown_to_x32 = 0x6
+    // .. .. ==> 0XF8006018[9:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_t_faw = 0x16
+    // .. .. ==> 0XF8006018[15:10] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FC00U    VAL : 0x00005800U
+    // .. .. reg_ddrc_t_ras_max = 0x24
+    // .. .. ==> 0XF8006018[21:16] = 0x00000024U
+    // .. ..     ==> MASK : 0x003F0000U    VAL : 0x00240000U
+    // .. .. reg_ddrc_t_ras_min = 0x13
+    // .. .. ==> 0XF8006018[26:22] = 0x00000013U
+    // .. ..     ==> MASK : 0x07C00000U    VAL : 0x04C00000U
+    // .. .. reg_ddrc_t_cke = 0x4
+    // .. .. ==> 0XF8006018[31:28] = 0x00000004U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U),
+    // .. .. reg_ddrc_write_latency = 0x5
+    // .. .. ==> 0XF800601C[4:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_rd2wr = 0x7
+    // .. .. ==> 0XF800601C[9:5] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x000000E0U
+    // .. .. reg_ddrc_wr2rd = 0xe
+    // .. .. ==> 0XF800601C[14:10] = 0x0000000EU
+    // .. ..     ==> MASK : 0x00007C00U    VAL : 0x00003800U
+    // .. .. reg_ddrc_t_xp = 0x4
+    // .. .. ==> 0XF800601C[19:15] = 0x00000004U
+    // .. ..     ==> MASK : 0x000F8000U    VAL : 0x00020000U
+    // .. .. reg_ddrc_pad_pd = 0x0
+    // .. .. ==> 0XF800601C[22:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00700000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd2pre = 0x4
+    // .. .. ==> 0XF800601C[27:23] = 0x00000004U
+    // .. ..     ==> MASK : 0x0F800000U    VAL : 0x02000000U
+    // .. .. reg_ddrc_t_rcd = 0x7
+    // .. .. ==> 0XF800601C[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U),
+    // .. .. reg_ddrc_t_ccd = 0x4
+    // .. .. ==> 0XF8006020[4:2] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000001CU    VAL : 0x00000010U
+    // .. .. reg_ddrc_t_rrd = 0x6
+    // .. .. ==> 0XF8006020[7:5] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000E0U    VAL : 0x000000C0U
+    // .. .. reg_ddrc_refresh_margin = 0x2
+    // .. .. ==> 0XF8006020[11:8] = 0x00000002U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000200U
+    // .. .. reg_ddrc_t_rp = 0x7
+    // .. .. ==> 0XF8006020[15:12] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00007000U
+    // .. .. reg_ddrc_refresh_to_x32 = 0x8
+    // .. .. ==> 0XF8006020[20:16] = 0x00000008U
+    // .. ..     ==> MASK : 0x001F0000U    VAL : 0x00080000U
+    // .. .. reg_ddrc_sdram = 0x1
+    // .. .. ==> 0XF8006020[21:21] = 0x00000001U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_mobile = 0x0
+    // .. .. ==> 0XF8006020[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_clock_stop_en = 0x0
+    // .. .. ==> 0XF8006020[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_read_latency = 0x7
+    // .. .. ==> 0XF8006020[28:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x1F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_mode_ddr1_ddr2 = 0x1
+    // .. .. ==> 0XF8006020[29:29] = 0x00000001U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x20000000U
+    // .. .. reg_ddrc_dis_pad_pd = 0x0
+    // .. .. ==> 0XF8006020[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_loopback = 0x0
+    // .. .. ==> 0XF8006020[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U),
+    // .. .. reg_ddrc_en_2t_timing_mode = 0x0
+    // .. .. ==> 0XF8006024[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_prefer_write = 0x0
+    // .. .. ==> 0XF8006024[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_max_rank_rd = 0xf
+    // .. .. ==> 0XF8006024[5:2] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0000003CU    VAL : 0x0000003CU
+    // .. .. reg_ddrc_mr_wr = 0x0
+    // .. .. ==> 0XF8006024[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_addr = 0x0
+    // .. .. ==> 0XF8006024[8:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_data = 0x0
+    // .. .. ==> 0XF8006024[24:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x01FFFE00U    VAL : 0x00000000U
+    // .. .. ddrc_reg_mr_wr_busy = 0x0
+    // .. .. ==> 0XF8006024[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_type = 0x0
+    // .. .. ==> 0XF8006024[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr_rdata_valid = 0x0
+    // .. .. ==> 0XF8006024[27:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU),
+    // .. .. reg_ddrc_final_wait_x32 = 0x7
+    // .. .. ==> 0XF8006028[6:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000007FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_pre_ocd_x32 = 0x0
+    // .. .. ==> 0XF8006028[10:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000780U    VAL : 0x00000000U
+    // .. .. reg_ddrc_t_mrd = 0x4
+    // .. .. ==> 0XF8006028[13:11] = 0x00000004U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00002000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U),
+    // .. .. reg_ddrc_emr2 = 0x8
+    // .. .. ==> 0XF800602C[15:0] = 0x00000008U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000008U
+    // .. .. reg_ddrc_emr3 = 0x0
+    // .. .. ==> 0XF800602C[31:16] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U),
+    // .. .. reg_ddrc_mr = 0x930
+    // .. .. ==> 0XF8006030[15:0] = 0x00000930U
+    // .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000930U
+    // .. .. reg_ddrc_emr = 0x4
+    // .. .. ==> 0XF8006030[31:16] = 0x00000004U
+    // .. ..     ==> MASK : 0xFFFF0000U    VAL : 0x00040000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U),
+    // .. .. reg_ddrc_burst_rdwr = 0x4
+    // .. .. ==> 0XF8006034[3:0] = 0x00000004U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000004U
+    // .. .. reg_ddrc_pre_cke_x1024 = 0x105
+    // .. .. ==> 0XF8006034[13:4] = 0x00000105U
+    // .. ..     ==> MASK : 0x00003FF0U    VAL : 0x00001050U
+    // .. .. reg_ddrc_post_cke_x1024 = 0x1
+    // .. .. ==> 0XF8006034[25:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00010000U
+    // .. .. reg_ddrc_burstchop = 0x0
+    // .. .. ==> 0XF8006034[28:28] = 0x00000000U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U),
+    // .. .. reg_ddrc_force_low_pri_n = 0x0
+    // .. .. ==> 0XF8006038[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_dq = 0x0
+    // .. .. ==> 0XF8006038[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_debug_mode = 0x0
+    // .. .. ==> 0XF8006038[6:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_level_start = 0x0
+    // .. .. ==> 0XF8006038[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_level_start = 0x0
+    // .. .. ==> 0XF8006038[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_dq0_wait_t = 0x0
+    // .. .. ==> 0XF8006038[12:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001E00U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U),
+    // .. .. reg_ddrc_addrmap_bank_b0 = 0x7
+    // .. .. ==> 0XF800603C[3:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000007U
+    // .. .. reg_ddrc_addrmap_bank_b1 = 0x7
+    // .. .. ==> 0XF800603C[7:4] = 0x00000007U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000070U
+    // .. .. reg_ddrc_addrmap_bank_b2 = 0x7
+    // .. .. ==> 0XF800603C[11:8] = 0x00000007U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000700U
+    // .. .. reg_ddrc_addrmap_col_b5 = 0x0
+    // .. .. ==> 0XF800603C[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b6 = 0x0
+    // .. .. ==> 0XF800603C[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U),
+    // .. .. reg_ddrc_addrmap_col_b2 = 0x0
+    // .. .. ==> 0XF8006040[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b3 = 0x0
+    // .. .. ==> 0XF8006040[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b4 = 0x0
+    // .. .. ==> 0XF8006040[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b7 = 0x0
+    // .. .. ==> 0XF8006040[15:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b8 = 0x0
+    // .. .. ==> 0XF8006040[19:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_addrmap_col_b9 = 0xf
+    // .. .. ==> 0XF8006040[23:20] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00F00000U
+    // .. .. reg_ddrc_addrmap_col_b10 = 0xf
+    // .. .. ==> 0XF8006040[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. reg_ddrc_addrmap_col_b11 = 0xf
+    // .. .. ==> 0XF8006040[31:28] = 0x0000000FU
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0xF0000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U),
+    // .. .. reg_ddrc_addrmap_row_b0 = 0x6
+    // .. .. ==> 0XF8006044[3:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_addrmap_row_b1 = 0x6
+    // .. .. ==> 0XF8006044[7:4] = 0x00000006U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6
+    // .. .. ==> 0XF8006044[11:8] = 0x00000006U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000600U
+    // .. .. reg_ddrc_addrmap_row_b12 = 0x6
+    // .. .. ==> 0XF8006044[15:12] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00006000U
+    // .. .. reg_ddrc_addrmap_row_b13 = 0x6
+    // .. .. ==> 0XF8006044[19:16] = 0x00000006U
+    // .. ..     ==> MASK : 0x000F0000U    VAL : 0x00060000U
+    // .. .. reg_ddrc_addrmap_row_b14 = 0x6
+    // .. .. ==> 0XF8006044[23:20] = 0x00000006U
+    // .. ..     ==> MASK : 0x00F00000U    VAL : 0x00600000U
+    // .. .. reg_ddrc_addrmap_row_b15 = 0xf
+    // .. .. ==> 0XF8006044[27:24] = 0x0000000FU
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x0F000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U),
+    // .. .. reg_ddrc_rank0_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank0_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[5:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000038U    VAL : 0x00000008U
+    // .. .. reg_ddrc_rank1_rd_odt = 0x1
+    // .. .. ==> 0XF8006048[8:6] = 0x00000001U
+    // .. ..     ==> MASK : 0x000001C0U    VAL : 0x00000040U
+    // .. .. reg_ddrc_rank1_wr_odt = 0x1
+    // .. .. ==> 0XF8006048[11:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. .. reg_phy_rd_local_odt = 0x0
+    // .. .. ==> 0XF8006048[13:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00003000U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_local_odt = 0x3
+    // .. .. ==> 0XF8006048[15:14] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000C000U    VAL : 0x0000C000U
+    // .. .. reg_phy_idle_local_odt = 0x3
+    // .. .. ==> 0XF8006048[17:16] = 0x00000003U
+    // .. ..     ==> MASK : 0x00030000U    VAL : 0x00030000U
+    // .. .. reg_ddrc_rank2_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[20:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x001C0000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank2_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[23:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00E00000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_rd_odt = 0x0
+    // .. .. ==> 0XF8006048[26:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rank3_wr_odt = 0x0
+    // .. .. ==> 0XF8006048[29:27] = 0x00000000U
+    // .. ..     ==> MASK : 0x38000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U),
+    // .. .. reg_phy_rd_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_wr_cmd_to_data = 0x0
+    // .. .. ==> 0XF8006050[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_phy_rdc_we_to_re_delay = 0x8
+    // .. .. ==> 0XF8006050[11:8] = 0x00000008U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000800U
+    // .. .. reg_phy_rdc_fifo_rst_disable = 0x0
+    // .. .. ==> 0XF8006050[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_fixed_re = 0x1
+    // .. .. ==> 0XF8006050[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0
+    // .. .. ==> 0XF8006050[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0
+    // .. .. ==> 0XF8006050[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_phy_clk_stall_level = 0x0
+    // .. .. ==> 0XF8006050[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[27:24] = 0x00000007U
+    // .. ..     ==> MASK : 0x0F000000U    VAL : 0x07000000U
+    // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7
+    // .. .. ==> 0XF8006050[31:28] = 0x00000007U
+    // .. ..     ==> MASK : 0xF0000000U    VAL : 0x70000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U),
+    // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1
+    // .. .. ==> 0XF8006058[7:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000001U
+    // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1
+    // .. .. ==> 0XF8006058[15:8] = 0x00000001U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000100U
+    // .. .. reg_ddrc_dis_dll_calib = 0x0
+    // .. .. ==> 0XF8006058[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U),
+    // .. .. reg_ddrc_rd_odt_delay = 0x3
+    // .. .. ==> 0XF800605C[3:0] = 0x00000003U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000003U
+    // .. .. reg_ddrc_wr_odt_delay = 0x0
+    // .. .. ==> 0XF800605C[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rd_odt_hold = 0x0
+    // .. .. ==> 0XF800605C[11:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000F00U    VAL : 0x00000000U
+    // .. .. reg_ddrc_wr_odt_hold = 0x5
+    // .. .. ==> 0XF800605C[15:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000F000U    VAL : 0x00005000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U),
+    // .. .. reg_ddrc_pageclose = 0x0
+    // .. .. ==> 0XF8006060[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_lpr_num_entries = 0x1f
+    // .. .. ==> 0XF8006060[6:1] = 0x0000001FU
+    // .. ..     ==> MASK : 0x0000007EU    VAL : 0x0000003EU
+    // .. .. reg_ddrc_auto_pre_en = 0x0
+    // .. .. ==> 0XF8006060[7:7] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. .. reg_ddrc_refresh_update_level = 0x0
+    // .. .. ==> 0XF8006060[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_wc = 0x0
+    // .. .. ==> 0XF8006060[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_collision_page_opt = 0x0
+    // .. .. ==> 0XF8006060[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_ddrc_selfref_en = 0x0
+    // .. .. ==> 0XF8006060[12:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU),
+    // .. .. reg_ddrc_go2critical_hysteresis = 0x0
+    // .. .. ==> 0XF8006064[12:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00001FE0U    VAL : 0x00000000U
+    // .. .. reg_arb_go2critical_en = 0x1
+    // .. .. ==> 0XF8006064[17:17] = 0x00000001U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00020000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U),
+    // .. .. reg_ddrc_wrlvl_ww = 0x41
+    // .. .. ==> 0XF8006068[7:0] = 0x00000041U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000041U
+    // .. .. reg_ddrc_rdlvl_rr = 0x41
+    // .. .. ==> 0XF8006068[15:8] = 0x00000041U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00004100U
+    // .. .. reg_ddrc_dfi_t_wlmrd = 0x28
+    // .. .. ==> 0XF8006068[25:16] = 0x00000028U
+    // .. ..     ==> MASK : 0x03FF0000U    VAL : 0x00280000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U),
+    // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10
+    // .. .. ==> 0XF800606C[7:0] = 0x00000010U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000010U
+    // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16
+    // .. .. ==> 0XF800606C[15:8] = 0x00000016U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00001600U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U),
+    // .. .. refresh_timer0_start_value_x32 = 0x0
+    // .. .. ==> 0XF80060A0[11:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000000U
+    // .. .. refresh_timer1_start_value_x32 = 0x8
+    // .. .. ==> 0XF80060A0[23:12] = 0x00000008U
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00008000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U),
+    // .. .. reg_ddrc_dis_auto_zq = 0x0
+    // .. .. ==> 0XF80060A4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_ddr3 = 0x1
+    // .. .. ==> 0XF80060A4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. reg_ddrc_t_mod = 0x200
+    // .. .. ==> 0XF80060A4[11:2] = 0x00000200U
+    // .. ..     ==> MASK : 0x00000FFCU    VAL : 0x00000800U
+    // .. .. reg_ddrc_t_zq_long_nop = 0x200
+    // .. .. ==> 0XF80060A4[21:12] = 0x00000200U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00200000U
+    // .. .. reg_ddrc_t_zq_short_nop = 0x40
+    // .. .. ==> 0XF80060A4[31:22] = 0x00000040U
+    // .. ..     ==> MASK : 0xFFC00000U    VAL : 0x10000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U),
+    // .. .. t_zq_short_interval_x1024 = 0xcb73
+    // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U
+    // .. ..     ==> MASK : 0x000FFFFFU    VAL : 0x0000CB73U
+    // .. .. dram_rstn_x1024 = 0x69
+    // .. .. ==> 0XF80060A8[27:20] = 0x00000069U
+    // .. ..     ==> MASK : 0x0FF00000U    VAL : 0x06900000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U),
+    // .. .. deeppowerdown_en = 0x0
+    // .. .. ==> 0XF80060AC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. deeppowerdown_to_x1024 = 0xff
+    // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU
+    // .. ..     ==> MASK : 0x000001FEU    VAL : 0x000001FEU
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU),
+    // .. .. dfi_wrlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00000FFFU    VAL : 0x00000FFFU
+    // .. .. dfi_rdlvl_max_x1024 = 0xfff
+    // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU
+    // .. ..     ==> MASK : 0x00FFF000U    VAL : 0x00FFF000U
+    // .. .. ddrc_reg_twrlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. ddrc_reg_trdlvl_max_error = 0x0
+    // .. .. ==> 0XF80060B0[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dfi_wr_level_en = 0x1
+    // .. .. ==> 0XF80060B0[26:26] = 0x00000001U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x04000000U
+    // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF80060B0[27:27] = 0x00000001U
+    // .. ..     ==> MASK : 0x08000000U    VAL : 0x08000000U
+    // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1
+    // .. .. ==> 0XF80060B0[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU),
+    // .. .. reg_ddrc_2t_delay = 0x0
+    // .. .. ==> 0XF80060B4[8:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000001FFU    VAL : 0x00000000U
+    // .. .. reg_ddrc_skip_ocd = 0x1
+    // .. .. ==> 0XF80060B4[9:9] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. .. reg_ddrc_dis_pre_bypass = 0x0
+    // .. .. ==> 0XF80060B4[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U),
+    // .. .. reg_ddrc_dfi_t_rddata_en = 0x6
+    // .. .. ==> 0XF80060B8[4:0] = 0x00000006U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000006U
+    // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3
+    // .. .. ==> 0XF80060B8[14:5] = 0x00000003U
+    // .. ..     ==> MASK : 0x00007FE0U    VAL : 0x00000060U
+    // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40
+    // .. .. ==> 0XF80060B8[24:15] = 0x00000040U
+    // .. ..     ==> MASK : 0x01FF8000U    VAL : 0x00200000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U),
+    // .. .. START: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 1
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U),
+    // .. .. FINISH: RESET ECC ERROR
+    // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. Clear_Correctable_DRAM_ECC_error = 0x0
+    // .. .. ==> 0XF80060C4[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U),
+    // .. .. CORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060C8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. ECC_CORRECTED_BIT_NUM = 0x0
+    // .. .. ==> 0XF80060C8[7:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FEU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U),
+    // .. .. UNCORR_ECC_LOG_VALID = 0x0
+    // .. .. ==> 0XF80060DC[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U),
+    // .. .. STAT_NUM_CORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[15:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000FF00U    VAL : 0x00000000U
+    // .. .. STAT_NUM_UNCORR_ERR = 0x0
+    // .. .. ==> 0XF80060F0[7:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U),
+    // .. .. reg_ddrc_ecc_mode = 0x0
+    // .. .. ==> 0XF80060F4[2:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_scrub = 0x1
+    // .. .. ==> 0XF80060F4[3:3] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000008U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U),
+    // .. .. reg_phy_dif_on = 0x0
+    // .. .. ==> 0XF8006114[3:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000000U
+    // .. .. reg_phy_dif_off = 0x0
+    // .. .. ==> 0XF8006114[7:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006118[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006118[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006118[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006118[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006118[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006118[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006118[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF800611C[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF800611C[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF800611C[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF800611C[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF800611C[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF800611C[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF800611C[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006120[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006120[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006120[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006120[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006120[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006120[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006120[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_data_slice_in_use = 0x1
+    // .. .. ==> 0XF8006124[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_phy_rdlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_wrlvl_inc_mode = 0x0
+    // .. .. ==> 0XF8006124[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_tx = 0x0
+    // .. .. ==> 0XF8006124[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_board_lpbk_rx = 0x0
+    // .. .. ==> 0XF8006124[5:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_shift_dq = 0x0
+    // .. .. ==> 0XF8006124[14:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x00007FC0U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_err_clr = 0x0
+    // .. .. ==> 0XF8006124[23:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00FF8000U    VAL : 0x00000000U
+    // .. .. reg_phy_dq_offset = 0x40
+    // .. .. ==> 0XF8006124[30:24] = 0x00000040U
+    // .. ..     ==> MASK : 0x7F000000U    VAL : 0x40000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF800612C[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xa1
+    // .. .. ==> 0XF800612C[19:10] = 0x000000A1U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00028400U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00028400U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x0
+    // .. .. ==> 0XF8006130[9:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000000U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xa0
+    // .. .. ==> 0XF8006130[19:10] = 0x000000A0U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00028000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00028000U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x7
+    // .. .. ==> 0XF8006134[9:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000007U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xad
+    // .. .. ==> 0XF8006134[19:10] = 0x000000ADU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002B400U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0002B407U),
+    // .. .. reg_phy_wrlvl_init_ratio = 0x7
+    // .. .. ==> 0XF8006138[9:0] = 0x00000007U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000007U
+    // .. .. reg_phy_gatelvl_init_ratio = 0xad
+    // .. .. ==> 0XF8006138[19:10] = 0x000000ADU
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x0002B400U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0002B407U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006140[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006140[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006140[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006144[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006144[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006144[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF8006148[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006148[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006148[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_rd_dqs_slave_ratio = 0x35
+    // .. .. ==> 0XF800614C[9:0] = 0x00000035U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000035U
+    // .. .. reg_phy_rd_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800614C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_rd_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800614C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c
+    // .. .. ==> 0XF8006154[9:0] = 0x0000007CU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000007CU
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006154[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006154[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000007CU),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x7c
+    // .. .. ==> 0XF8006158[9:0] = 0x0000007CU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x0000007CU
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006158[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006158[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x0000007CU),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x87
+    // .. .. ==> 0XF800615C[9:0] = 0x00000087U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000087U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF800615C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF800615C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000087U),
+    // .. .. reg_phy_wr_dqs_slave_ratio = 0x87
+    // .. .. ==> 0XF8006160[9:0] = 0x00000087U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x00000087U
+    // .. .. reg_phy_wr_dqs_slave_force = 0x0
+    // .. .. ==> 0XF8006160[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_dqs_slave_delay = 0x0
+    // .. .. ==> 0XF8006160[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000087U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xf6
+    // .. .. ==> 0XF8006168[10:0] = 0x000000F6U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F6U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006168[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006168[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F6U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0xf5
+    // .. .. ==> 0XF800616C[10:0] = 0x000000F5U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x000000F5U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF800616C[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF800616C[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F5U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x102
+    // .. .. ==> 0XF8006170[10:0] = 0x00000102U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000102U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006170[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006170[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000102U),
+    // .. .. reg_phy_fifo_we_slave_ratio = 0x102
+    // .. .. ==> 0XF8006174[10:0] = 0x00000102U
+    // .. ..     ==> MASK : 0x000007FFU    VAL : 0x00000102U
+    // .. .. reg_phy_fifo_we_in_force = 0x0
+    // .. .. ==> 0XF8006174[11:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. .. reg_phy_fifo_we_in_delay = 0x0
+    // .. .. ==> 0XF8006174[20:12] = 0x00000000U
+    // .. ..     ==> MASK : 0x001FF000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000102U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xbc
+    // .. .. ==> 0XF800617C[9:0] = 0x000000BCU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000BCU
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF800617C[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF800617C[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000BCU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xbc
+    // .. .. ==> 0XF8006180[9:0] = 0x000000BCU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000BCU
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006180[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006180[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000BCU),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc7
+    // .. .. ==> 0XF8006184[9:0] = 0x000000C7U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C7U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006184[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006184[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C7U),
+    // .. .. reg_phy_wr_data_slave_ratio = 0xc7
+    // .. .. ==> 0XF8006188[9:0] = 0x000000C7U
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000000C7U
+    // .. .. reg_phy_wr_data_slave_force = 0x0
+    // .. .. ==> 0XF8006188[10:10] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. .. reg_phy_wr_data_slave_delay = 0x0
+    // .. .. ==> 0XF8006188[19:11] = 0x00000000U
+    // .. ..     ==> MASK : 0x000FF800U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C7U),
+    // .. .. reg_phy_loopback = 0x0
+    // .. .. ==> 0XF8006190[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_phy_bl2 = 0x0
+    // .. .. ==> 0XF8006190[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_phy_at_spd_atpg = 0x0
+    // .. .. ==> 0XF8006190[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_enable = 0x0
+    // .. .. ==> 0XF8006190[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_force_err = 0x0
+    // .. .. ==> 0XF8006190[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. reg_phy_bist_mode = 0x0
+    // .. .. ==> 0XF8006190[6:5] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. .. reg_phy_invert_clkout = 0x1
+    // .. .. ==> 0XF8006190[7:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0
+    // .. .. ==> 0XF8006190[8:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. .. reg_phy_sel_logic = 0x0
+    // .. .. ==> 0XF8006190[9:9] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_ratio = 0x100
+    // .. .. ==> 0XF8006190[19:10] = 0x00000100U
+    // .. ..     ==> MASK : 0x000FFC00U    VAL : 0x00040000U
+    // .. .. reg_phy_ctrl_slave_force = 0x0
+    // .. .. ==> 0XF8006190[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006190[27:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x0FE00000U    VAL : 0x00000000U
+    // .. .. reg_phy_use_rank0_delays = 0x1
+    // .. .. ==> 0XF8006190[28:28] = 0x00000001U
+    // .. ..     ==> MASK : 0x10000000U    VAL : 0x10000000U
+    // .. .. reg_phy_lpddr = 0x0
+    // .. .. ==> 0XF8006190[29:29] = 0x00000000U
+    // .. ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. .. reg_phy_cmd_latency = 0x0
+    // .. .. ==> 0XF8006190[30:30] = 0x00000000U
+    // .. ..     ==> MASK : 0x40000000U    VAL : 0x00000000U
+    // .. .. reg_phy_int_lpbk = 0x0
+    // .. .. ==> 0XF8006190[31:31] = 0x00000000U
+    // .. ..     ==> MASK : 0x80000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U),
+    // .. .. reg_phy_wr_rl_delay = 0x2
+    // .. .. ==> 0XF8006194[4:0] = 0x00000002U
+    // .. ..     ==> MASK : 0x0000001FU    VAL : 0x00000002U
+    // .. .. reg_phy_rd_rl_delay = 0x4
+    // .. .. ==> 0XF8006194[9:5] = 0x00000004U
+    // .. ..     ==> MASK : 0x000003E0U    VAL : 0x00000080U
+    // .. .. reg_phy_dll_lock_diff = 0xf
+    // .. .. ==> 0XF8006194[13:10] = 0x0000000FU
+    // .. ..     ==> MASK : 0x00003C00U    VAL : 0x00003C00U
+    // .. .. reg_phy_use_wr_level = 0x1
+    // .. .. ==> 0XF8006194[14:14] = 0x00000001U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00004000U
+    // .. .. reg_phy_use_rd_dqs_gate_level = 0x1
+    // .. .. ==> 0XF8006194[15:15] = 0x00000001U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00008000U
+    // .. .. reg_phy_use_rd_data_eye_level = 0x1
+    // .. .. ==> 0XF8006194[16:16] = 0x00000001U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00010000U
+    // .. .. reg_phy_dis_calib_rst = 0x0
+    // .. .. ==> 0XF8006194[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_phy_ctrl_slave_delay = 0x0
+    // .. .. ==> 0XF8006194[19:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U),
+    // .. .. reg_arb_page_addr_mask = 0x0
+    // .. .. ==> 0XF8006204[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006208[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006208[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006208[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF800620C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF800620C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF800620C[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006210[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006210[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006210[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_wr_portn = 0x3ff
+    // .. .. ==> 0XF8006214[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_wr_portn = 0x0
+    // .. .. ==> 0XF8006214[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_rmw_portn = 0x1
+    // .. .. ==> 0XF8006214[19:19] = 0x00000001U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006218[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006218[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF800621C[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF800621C[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006220[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006220[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_arb_pri_rd_portn = 0x3ff
+    // .. .. ==> 0XF8006224[9:0] = 0x000003FFU
+    // .. ..     ==> MASK : 0x000003FFU    VAL : 0x000003FFU
+    // .. .. reg_arb_disable_aging_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. reg_arb_disable_urgent_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[17:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. .. reg_arb_dis_page_match_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[18:18] = 0x00000000U
+    // .. ..     ==> MASK : 0x00040000U    VAL : 0x00000000U
+    // .. .. reg_arb_set_hpr_rd_portn = 0x0
+    // .. .. ==> 0XF8006224[19:19] = 0x00000000U
+    // .. ..     ==> MASK : 0x00080000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU),
+    // .. .. reg_ddrc_lpddr2 = 0x0
+    // .. .. ==> 0XF80062A8[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. reg_ddrc_per_bank_refresh = 0x0
+    // .. .. ==> 0XF80062A8[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_derate_enable = 0x0
+    // .. .. ==> 0XF80062A8[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. reg_ddrc_mr4_margin = 0x0
+    // .. .. ==> 0XF80062A8[11:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U),
+    // .. .. reg_ddrc_mr4_read_interval = 0x0
+    // .. .. ==> 0XF80062AC[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. reg_ddrc_min_stable_clock_x1 = 0x5
+    // .. .. ==> 0XF80062B0[3:0] = 0x00000005U
+    // .. ..     ==> MASK : 0x0000000FU    VAL : 0x00000005U
+    // .. .. reg_ddrc_idle_after_reset_x32 = 0x12
+    // .. .. ==> 0XF80062B0[11:4] = 0x00000012U
+    // .. ..     ==> MASK : 0x00000FF0U    VAL : 0x00000120U
+    // .. .. reg_ddrc_t_mrw = 0x5
+    // .. .. ==> 0XF80062B0[21:12] = 0x00000005U
+    // .. ..     ==> MASK : 0x003FF000U    VAL : 0x00005000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U),
+    // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8
+    // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U
+    // .. ..     ==> MASK : 0x000000FFU    VAL : 0x000000A8U
+    // .. .. reg_ddrc_dev_zqinit_x32 = 0x12
+    // .. .. ==> 0XF80062B4[17:8] = 0x00000012U
+    // .. ..     ==> MASK : 0x0003FF00U    VAL : 0x00001200U
+    // .. .. 
+    EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U),
+    // .. .. START: POLL ON DCI STATUS
+    // .. .. DONE = 1
+    // .. .. ==> 0XF8000B74[13:13] = 0x00000001U
+    // .. ..     ==> MASK : 0x00002000U    VAL : 0x00002000U
+    // .. .. 
+    EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+    // .. .. FINISH: POLL ON DCI STATUS
+    // .. .. START: UNLOCK DDR
+    // .. .. reg_ddrc_soft_rstb = 0x1
+    // .. .. ==> 0XF8006000[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. reg_ddrc_powerdown_en = 0x0
+    // .. .. ==> 0XF8006000[1:1] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. .. reg_ddrc_data_bus_width = 0x0
+    // .. .. ==> 0XF8006000[3:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x0000000CU    VAL : 0x00000000U
+    // .. .. reg_ddrc_burst8_refresh = 0x0
+    // .. .. ==> 0XF8006000[6:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000070U    VAL : 0x00000000U
+    // .. .. reg_ddrc_rdwr_idle_gap = 1
+    // .. .. ==> 0XF8006000[13:7] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003F80U    VAL : 0x00000080U
+    // .. .. reg_ddrc_dis_rd_bypass = 0x0
+    // .. .. ==> 0XF8006000[14:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_act_bypass = 0x0
+    // .. .. ==> 0XF8006000[15:15] = 0x00000000U
+    // .. ..     ==> MASK : 0x00008000U    VAL : 0x00000000U
+    // .. .. reg_ddrc_dis_auto_refresh = 0x0
+    // .. .. ==> 0XF8006000[16:16] = 0x00000000U
+    // .. ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U),
+    // .. .. FINISH: UNLOCK DDR
+    // .. .. START: CHECK DDR STATUS
+    // .. .. ddrc_reg_operating_mode = 1
+    // .. .. ==> 0XF8006054[2:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000007U    VAL : 0x00000001U
+    // .. .. 
+    EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+    // .. .. FINISH: CHECK DDR STATUS
+    // .. FINISH: DDR INITIALIZATION
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_mio_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: OCM REMAPPING
+    // .. FINISH: OCM REMAPPING
+    // .. START: DDRIOB SETTINGS
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B40[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B40[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B40[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B40[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B40[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B40[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B40[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B40[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B44[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B44[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B44[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B44[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B44[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B44[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B44[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B44[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B48[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B48[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B48[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B48[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B48[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B48[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B48[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B48[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B4C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x1
+    // .. ==> 0XF8000B4C[2:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000002U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B4C[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B4C[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B4C[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B4C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B4C[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B4C[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B50[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B50[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B50[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B50[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B50[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B50[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B50[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B50[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B54[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x2
+    // .. ==> 0XF8000B54[2:1] = 0x00000002U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000004U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B54[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x1
+    // .. ==> 0XF8000B54[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. DCR_TYPE = 0x3
+    // .. ==> 0XF8000B54[6:5] = 0x00000003U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000060U
+    // .. IBUF_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0
+    // .. ==> 0XF8000B54[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B54[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B54[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U),
+    // .. INP_POWER = 0x0
+    // .. ==> 0XF8000B58[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. INP_TYPE = 0x0
+    // .. ==> 0XF8000B58[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. DCI_UPDATE = 0x0
+    // .. ==> 0XF8000B58[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. TERM_EN = 0x0
+    // .. ==> 0XF8000B58[4:4] = 0x00000000U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. DCR_TYPE = 0x0
+    // .. ==> 0XF8000B58[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. IBUF_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. TERM_DISABLE_MODE = 0x0
+    // .. ==> 0XF8000B58[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. OUTPUT_EN = 0x3
+    // .. ==> 0XF8000B58[10:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000600U    VAL : 0x00000600U
+    // .. PULLUP_EN = 0x0
+    // .. ==> 0XF8000B58[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B5C[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B5C[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x3
+    // .. ==> 0XF8000B5C[18:14] = 0x00000003U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x0000C000U
+    // .. SLEW_N = 0x3
+    // .. ==> 0XF8000B5C[23:19] = 0x00000003U
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00180000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B5C[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B5C[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B60[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B60[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B60[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B60[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B60[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B60[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B64[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B64[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B64[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B64[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B64[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B64[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. DRIVE_P = 0x1c
+    // .. ==> 0XF8000B68[6:0] = 0x0000001CU
+    // ..     ==> MASK : 0x0000007FU    VAL : 0x0000001CU
+    // .. DRIVE_N = 0xc
+    // .. ==> 0XF8000B68[13:7] = 0x0000000CU
+    // ..     ==> MASK : 0x00003F80U    VAL : 0x00000600U
+    // .. SLEW_P = 0x6
+    // .. ==> 0XF8000B68[18:14] = 0x00000006U
+    // ..     ==> MASK : 0x0007C000U    VAL : 0x00018000U
+    // .. SLEW_N = 0x1f
+    // .. ==> 0XF8000B68[23:19] = 0x0000001FU
+    // ..     ==> MASK : 0x00F80000U    VAL : 0x00F80000U
+    // .. GTL = 0x0
+    // .. ==> 0XF8000B68[26:24] = 0x00000000U
+    // ..     ==> MASK : 0x07000000U    VAL : 0x00000000U
+    // .. RTERM = 0x0
+    // .. ==> 0XF8000B68[31:27] = 0x00000000U
+    // ..     ==> MASK : 0xF8000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU),
+    // .. VREF_INT_EN = 0x1
+    // .. ==> 0XF8000B6C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. VREF_SEL = 0x4
+    // .. ==> 0XF8000B6C[4:1] = 0x00000004U
+    // ..     ==> MASK : 0x0000001EU    VAL : 0x00000008U
+    // .. VREF_EXT_EN = 0x0
+    // .. ==> 0XF8000B6C[6:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000060U    VAL : 0x00000000U
+    // .. VREF_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[8:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000180U    VAL : 0x00000000U
+    // .. REFIO_EN = 0x1
+    // .. ==> 0XF8000B6C[9:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000200U
+    // .. REFIO_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DRST_B_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. CKE_PULLUP_EN = 0x0
+    // .. ==> 0XF8000B6C[14:14] = 0x00000000U
+    // ..     ==> MASK : 0x00004000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000209U),
+    // .. .. START: ASSERT RESET
+    // .. .. RESET = 1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U),
+    // .. .. FINISH: ASSERT RESET
+    // .. .. START: DEASSERT RESET
+    // .. .. RESET = 0
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U),
+    // .. .. FINISH: DEASSERT RESET
+    // .. .. RESET = 0x1
+    // .. .. ==> 0XF8000B70[0:0] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. .. ENABLE = 0x1
+    // .. .. ==> 0XF8000B70[1:1] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. .. VRP_TRI = 0x0
+    // .. .. ==> 0XF8000B70[2:2] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. .. VRN_TRI = 0x0
+    // .. .. ==> 0XF8000B70[3:3] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. .. VRP_OUT = 0x0
+    // .. .. ==> 0XF8000B70[4:4] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000010U    VAL : 0x00000000U
+    // .. .. VRN_OUT = 0x1
+    // .. .. ==> 0XF8000B70[5:5] = 0x00000001U
+    // .. ..     ==> MASK : 0x00000020U    VAL : 0x00000020U
+    // .. .. NREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[7:6] = 0x00000000U
+    // .. ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. .. NREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[10:8] = 0x00000000U
+    // .. ..     ==> MASK : 0x00000700U    VAL : 0x00000000U
+    // .. .. NREF_OPT4 = 0x1
+    // .. .. ==> 0XF8000B70[13:11] = 0x00000001U
+    // .. ..     ==> MASK : 0x00003800U    VAL : 0x00000800U
+    // .. .. PREF_OPT1 = 0x0
+    // .. .. ==> 0XF8000B70[16:14] = 0x00000000U
+    // .. ..     ==> MASK : 0x0001C000U    VAL : 0x00000000U
+    // .. .. PREF_OPT2 = 0x0
+    // .. .. ==> 0XF8000B70[19:17] = 0x00000000U
+    // .. ..     ==> MASK : 0x000E0000U    VAL : 0x00000000U
+    // .. .. UPDATE_CONTROL = 0x0
+    // .. .. ==> 0XF8000B70[20:20] = 0x00000000U
+    // .. ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. .. INIT_COMPLETE = 0x0
+    // .. .. ==> 0XF8000B70[21:21] = 0x00000000U
+    // .. ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. .. TST_CLK = 0x0
+    // .. .. ==> 0XF8000B70[22:22] = 0x00000000U
+    // .. ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. .. TST_HLN = 0x0
+    // .. .. ==> 0XF8000B70[23:23] = 0x00000000U
+    // .. ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. .. TST_HLP = 0x0
+    // .. .. ==> 0XF8000B70[24:24] = 0x00000000U
+    // .. ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. .. TST_RST = 0x0
+    // .. .. ==> 0XF8000B70[25:25] = 0x00000000U
+    // .. ..     ==> MASK : 0x02000000U    VAL : 0x00000000U
+    // .. .. INT_DCI_EN = 0x0
+    // .. .. ==> 0XF8000B70[26:26] = 0x00000000U
+    // .. ..     ==> MASK : 0x04000000U    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U),
+    // .. FINISH: DDRIOB SETTINGS
+    // .. START: MIO PROGRAMMING
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000700[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000700[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000700[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000700[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000700[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000700[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000700[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000700[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000700[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000700, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000704[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000704[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000704[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000704[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000704[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000704[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000704[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000704[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000704[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000708[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000708[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000708[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000708[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000708[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000708[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000708[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000708[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000708[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800070C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800070C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800070C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800070C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800070C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800070C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800070C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800070C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800070C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000710[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000710[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000710[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000710[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000710[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000710[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000710[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000710[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000710[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000714[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000714[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000714[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000714[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000714[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000714[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000714[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000714[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000714[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000718[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000718[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000718[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000718[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000718[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000718[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000718[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000718[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000718[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800071C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800071C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800071C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800071C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800071C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800071C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800071C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800071C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800071C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000720[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000720[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000720[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000720[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000720[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000720[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000720[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000720[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000720[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000602U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000724[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000724[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000724[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000724[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000724[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000724[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000724[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000724[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000724[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00000600U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000728[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000728[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000728[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000728[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF8000728[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF8000728[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000728[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000728[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000728[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000680U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800072C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800072C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800072C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800072C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF800072C[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF800072C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800072C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800072C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800072C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000680U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000730[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000730[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000730[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000730[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF8000730[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF8000730[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000730[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000730[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000730[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000680U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000734[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000734[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000734[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000734[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF8000734[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF8000734[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000734[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000734[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000734[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000680U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000738[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000738[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000738[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000738[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF8000738[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF8000738[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF8000738[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000738[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000738[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000680U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800073C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800073C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800073C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800073C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF800073C[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF800073C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 3
+    // .. ==> 0XF800073C[11:9] = 0x00000003U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000600U
+    // .. PULLUP = 0
+    // .. ==> 0XF800073C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800073C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000680U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000740[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000740[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000740[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000740[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000740[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000740[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000740[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000740[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000740[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000744[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000744[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000744[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000744[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000744[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000744[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000744[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000744[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000744[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000748[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000748[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000748[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000748[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000748[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000748[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000748[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000748[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000748[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800074C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800074C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800074C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800074C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800074C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800074C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800074C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800074C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800074C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000750[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000750[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000750[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000750[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000750[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000750[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000750[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000750[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000750[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000754[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000754[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000754[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000754[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000754[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000754[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000754[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000754[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000754[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00000202U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000758[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000758[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000758[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000758[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000758[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000758[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000758[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000758[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000758[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800075C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800075C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800075C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800075C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800075C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800075C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800075C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800075C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800075C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000760[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000760[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000760[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000760[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000760[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000760[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000760[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000760[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000760[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000764[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000764[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000764[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000764[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000764[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000764[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000764[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000764[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000764[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000768[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF8000768[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF8000768[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000768[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000768[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000768[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000768[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000768[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000768[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800076C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 1
+    // .. ==> 0XF800076C[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. L1_SEL = 0
+    // .. ==> 0XF800076C[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800076C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800076C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800076C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800076C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800076C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800076C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000203U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000770[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000770[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000770[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000770[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000770[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000770[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000770[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000770[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000770[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000774[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000774[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000774[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000774[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000774[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000774[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000774[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000774[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000774[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000778[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000778[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000778[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000778[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000778[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000778[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000778[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000778[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000778[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF800077C[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800077C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800077C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800077C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800077C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800077C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800077C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800077C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800077C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000780[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000780[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000780[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000780[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000780[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000780[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000780[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000780[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000780[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000784[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000784[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000784[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000784[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000784[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000784[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000784[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000784[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000784[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000788[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000788[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000788[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000788[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000788[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000788[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000788[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000788[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000788[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800078C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800078C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800078C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800078C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800078C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800078C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800078C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800078C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800078C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF8000790[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000790[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000790[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000790[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000790[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000790[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000790[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000790[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000790[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000794[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000794[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000794[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000794[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000794[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000794[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000794[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000794[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000794[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF8000798[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF8000798[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF8000798[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF8000798[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF8000798[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF8000798[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF8000798[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF8000798[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF8000798[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF800079C[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF800079C[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 1
+    // .. ==> 0XF800079C[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. L2_SEL = 0
+    // .. ==> 0XF800079C[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF800079C[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF800079C[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF800079C[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF800079C[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF800079C[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007A0[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007A0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007A4[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007A4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007A8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007A8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007A8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007A8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007A8[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007A8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007A8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007A8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007A8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007AC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007AC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007AC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007AC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007AC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007AC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007AC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007AC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007AC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007B0[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007B0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007B4[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007B4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007B8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007B8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007B8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007B8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007B8[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007B8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007B8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007B8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007B8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007BC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007BC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007BC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007BC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007BC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007BC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007BC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007BC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007BC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C0[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U),
+    // .. TRI_ENABLE = 1
+    // .. ==> 0XF80007C4[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 7
+    // .. ==> 0XF80007C4[7:5] = 0x00000007U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x000000E0U
+    // .. Speed = 0
+    // .. ==> 0XF80007C4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007C8[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007C8[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007C8[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007C8[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007C8[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007C8[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007C8[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007C8[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007C8[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007CC[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007CC[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007CC[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007CC[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 0
+    // .. ==> 0XF80007CC[7:5] = 0x00000000U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000000U
+    // .. Speed = 0
+    // .. ==> 0XF80007CC[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007CC[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007CC[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007CC[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00000200U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D0[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D0[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D0[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D0[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D0[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D0[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D0[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D0[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D0[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U),
+    // .. TRI_ENABLE = 0
+    // .. ==> 0XF80007D4[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. L0_SEL = 0
+    // .. ==> 0XF80007D4[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. L1_SEL = 0
+    // .. ==> 0XF80007D4[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. L2_SEL = 0
+    // .. ==> 0XF80007D4[4:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000018U    VAL : 0x00000000U
+    // .. L3_SEL = 4
+    // .. ==> 0XF80007D4[7:5] = 0x00000004U
+    // ..     ==> MASK : 0x000000E0U    VAL : 0x00000080U
+    // .. Speed = 0
+    // .. ==> 0XF80007D4[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. IO_Type = 1
+    // .. ==> 0XF80007D4[11:9] = 0x00000001U
+    // ..     ==> MASK : 0x00000E00U    VAL : 0x00000200U
+    // .. PULLUP = 0
+    // .. ==> 0XF80007D4[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. DisableRcvr = 0
+    // .. ==> 0XF80007D4[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U),
+    // .. SDIO1_CD_SEL = 58
+    // .. ==> 0XF8000834[21:16] = 0x0000003AU
+    // ..     ==> MASK : 0x003F0000U    VAL : 0x003A0000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000834, 0x003F0000U ,0x003A0000U),
+    // .. FINISH: MIO PROGRAMMING
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_peripherals_init_data_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B48[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B4C[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B50[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U),
+    // .. IBUF_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[7:7] = 0x00000001U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000080U
+    // .. TERM_DISABLE_MODE = 0x1
+    // .. ==> 0XF8000B54[8:8] = 0x00000001U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000100U
+    // .. 
+    EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U),
+    // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // .. START: SRAM/NOR SET OPMODE
+    // .. FINISH: SRAM/NOR SET OPMODE
+    // .. START: UART REGISTERS
+    // .. BDIV = 0x6
+    // .. ==> 0XE0001034[7:0] = 0x00000006U
+    // ..     ==> MASK : 0x000000FFU    VAL : 0x00000006U
+    // .. 
+    EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U),
+    // .. CD = 0x3e
+    // .. ==> 0XE0001018[15:0] = 0x0000003EU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000003EU
+    // .. 
+    EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU),
+    // .. STPBRK = 0x0
+    // .. ==> 0XE0001000[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. STTBRK = 0x0
+    // .. ==> 0XE0001000[7:7] = 0x00000000U
+    // ..     ==> MASK : 0x00000080U    VAL : 0x00000000U
+    // .. RSTTO = 0x0
+    // .. ==> 0XE0001000[6:6] = 0x00000000U
+    // ..     ==> MASK : 0x00000040U    VAL : 0x00000000U
+    // .. TXDIS = 0x0
+    // .. ==> 0XE0001000[5:5] = 0x00000000U
+    // ..     ==> MASK : 0x00000020U    VAL : 0x00000000U
+    // .. TXEN = 0x1
+    // .. ==> 0XE0001000[4:4] = 0x00000001U
+    // ..     ==> MASK : 0x00000010U    VAL : 0x00000010U
+    // .. RXDIS = 0x0
+    // .. ==> 0XE0001000[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. RXEN = 0x1
+    // .. ==> 0XE0001000[2:2] = 0x00000001U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000004U
+    // .. TXRES = 0x1
+    // .. ==> 0XE0001000[1:1] = 0x00000001U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000002U
+    // .. RXRES = 0x1
+    // .. ==> 0XE0001000[0:0] = 0x00000001U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000001U
+    // .. 
+    EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U),
+    // .. IRMODE = 0x0
+    // .. ==> 0XE0001004[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. UCLKEN = 0x0
+    // .. ==> 0XE0001004[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. CHMODE = 0x0
+    // .. ==> 0XE0001004[9:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000300U    VAL : 0x00000000U
+    // .. NBSTOP = 0x0
+    // .. ==> 0XE0001004[7:6] = 0x00000000U
+    // ..     ==> MASK : 0x000000C0U    VAL : 0x00000000U
+    // .. PAR = 0x4
+    // .. ==> 0XE0001004[5:3] = 0x00000004U
+    // ..     ==> MASK : 0x00000038U    VAL : 0x00000020U
+    // .. CHRL = 0x0
+    // .. ==> 0XE0001004[2:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000006U    VAL : 0x00000000U
+    // .. CLKS = 0x0
+    // .. ==> 0XE0001004[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U),
+    // .. FINISH: UART REGISTERS
+    // .. START: TPIU WIDTH IN CASE OF EMIO
+    // .. .. START: TRACE LOCK ACCESS REGISTER
+    // .. .. a = 0XC5ACCE55
+    // .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. FINISH: TRACE LOCK ACCESS REGISTER
+    // .. .. START: TRACE CURRENT PORT SIZE
+    // .. .. a = 2
+    // .. .. ==> 0XF8803004[31:0] = 0x00000002U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000002U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U),
+    // .. .. FINISH: TRACE CURRENT PORT SIZE
+    // .. .. START: TRACE LOCK ACCESS REGISTER
+    // .. .. a = 0X0
+    // .. .. ==> 0XF8803FB0[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. FINISH: TRACE LOCK ACCESS REGISTER
+    // .. FINISH: TPIU WIDTH IN CASE OF EMIO
+    // .. START: QSPI REGISTERS
+    // .. Holdb_dr = 1
+    // .. ==> 0XE000D000[19:19] = 0x00000001U
+    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
+    // .. 
+    EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U),
+    // .. FINISH: QSPI REGISTERS
+    // .. START: PL POWER ON RESET REGISTERS
+    // .. PCFG_POR_CNT_4K = 0
+    // .. ==> 0XF8007000[29:29] = 0x00000000U
+    // ..     ==> MASK : 0x20000000U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U),
+    // .. FINISH: PL POWER ON RESET REGISTERS
+    // .. START: SMC TIMING CALCULATION REGISTER UPDATE
+    // .. .. START: NAND SET CYCLE
+    // .. .. FINISH: NAND SET CYCLE
+    // .. .. START: OPMODE
+    // .. .. FINISH: OPMODE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: SRAM/NOR CS0 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS0 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS0 BASE ADDRESS
+    // .. .. FINISH: NOR CS0 BASE ADDRESS
+    // .. .. START: SRAM/NOR CS1 SET CYCLE
+    // .. .. FINISH: SRAM/NOR CS1 SET CYCLE
+    // .. .. START: DIRECT COMMAND
+    // .. .. FINISH: DIRECT COMMAND
+    // .. .. START: NOR CS1 BASE ADDRESS
+    // .. .. FINISH: NOR CS1 BASE ADDRESS
+    // .. .. START: USB RESET
+    // .. .. .. START: USB0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. DIRECTION_0 = 0x80
+    // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. OP_ENABLE_0 = 0x80
+    // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000080U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U),
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x0
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000000U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. MASK_0_LSW = 0xff7f
+    // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU
+    // .. .. .. ..     ==> MASK : 0xFFFF0000U    VAL : 0xFF7F0000U
+    // .. .. .. .. DATA_0_LSW = 0x80
+    // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U
+    // .. .. .. ..     ==> MASK : 0x0000FFFFU    VAL : 0x00000080U
+    // .. .. .. .. 
+    EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U),
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB0 RESET
+    // .. .. .. START: USB1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: USB1 RESET
+    // .. .. FINISH: USB RESET
+    // .. .. START: ENET RESET
+    // .. .. .. START: ENET0 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET0 RESET
+    // .. .. .. START: ENET1 RESET
+    // .. .. .. .. START: DIR MODE BANK 0
+    // .. .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. .. START: DIR MODE BANK 1
+    // .. .. .. .. FINISH: DIR MODE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. .. .. START: OUTPUT ENABLE BANK 1
+    // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: ENET1 RESET
+    // .. .. FINISH: ENET RESET
+    // .. .. START: I2C RESET
+    // .. .. .. START: I2C0 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C0 RESET
+    // .. .. .. START: I2C1 RESET
+    // .. .. .. .. START: DIR MODE GPIO BANK0
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK0
+    // .. .. .. .. START: DIR MODE GPIO BANK1
+    // .. .. .. .. FINISH: DIR MODE GPIO BANK1
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: OUTPUT ENABLE
+    // .. .. .. .. FINISH: OUTPUT ENABLE
+    // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48]
+    // .. .. .. .. START: ADD 1 MS DELAY
+    // .. .. .. .. 
+    EMIT_MASKDELAY(0XF8F00200, 1),
+    // .. .. .. .. FINISH: ADD 1 MS DELAY
+    // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16]
+    // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32]
+    // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48]
+    // .. .. .. FINISH: I2C1 RESET
+    // .. .. FINISH: I2C RESET
+    // .. .. START: NOR CHIP SELECT
+    // .. .. .. START: DIR MODE BANK 0
+    // .. .. .. FINISH: DIR MODE BANK 0
+    // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
+    // .. .. .. START: OUTPUT ENABLE BANK 0
+    // .. .. .. FINISH: OUTPUT ENABLE BANK 0
+    // .. .. FINISH: NOR CHIP SELECT
+    // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_post_config_1_0[] = {
+    // START: top
+    // .. START: SLCR SETTINGS
+    // .. UNLOCK_KEY = 0XDF0D
+    // .. ==> 0XF8000008[15:0] = 0x0000DF0DU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000DF0DU
+    // .. 
+    EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
+    // .. FINISH: SLCR SETTINGS
+    // .. START: ENABLING LEVEL SHIFTER
+    // .. USER_INP_ICT_EN_0 = 3
+    // .. ==> 0XF8000900[1:0] = 0x00000003U
+    // ..     ==> MASK : 0x00000003U    VAL : 0x00000003U
+    // .. USER_INP_ICT_EN_1 = 3
+    // .. ==> 0XF8000900[3:2] = 0x00000003U
+    // ..     ==> MASK : 0x0000000CU    VAL : 0x0000000CU
+    // .. 
+    EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU),
+    // .. FINISH: ENABLING LEVEL SHIFTER
+    // .. START: TPIU WIDTH IN CASE OF EMIO
+    // .. .. START: TRACE LOCK ACCESS REGISTER
+    // .. .. a = 0XC5ACCE55
+    // .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. FINISH: TRACE LOCK ACCESS REGISTER
+    // .. .. START: TRACE CURRENT PORT SIZE
+    // .. .. a = 2
+    // .. .. ==> 0XF8803004[31:0] = 0x00000002U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000002U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U),
+    // .. .. FINISH: TRACE CURRENT PORT SIZE
+    // .. .. START: TRACE LOCK ACCESS REGISTER
+    // .. .. a = 0X0
+    // .. .. ==> 0XF8803FB0[31:0] = 0x00000000U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U),
+    // .. .. FINISH: TRACE LOCK ACCESS REGISTER
+    // .. FINISH: TPIU WIDTH IN CASE OF EMIO
+    // .. START: FPGA RESETS TO 0
+    // .. reserved_3 = 0
+    // .. ==> 0XF8000240[31:25] = 0x00000000U
+    // ..     ==> MASK : 0xFE000000U    VAL : 0x00000000U
+    // .. FPGA_ACP_RST = 0
+    // .. ==> 0XF8000240[24:24] = 0x00000000U
+    // ..     ==> MASK : 0x01000000U    VAL : 0x00000000U
+    // .. FPGA_AXDS3_RST = 0
+    // .. ==> 0XF8000240[23:23] = 0x00000000U
+    // ..     ==> MASK : 0x00800000U    VAL : 0x00000000U
+    // .. FPGA_AXDS2_RST = 0
+    // .. ==> 0XF8000240[22:22] = 0x00000000U
+    // ..     ==> MASK : 0x00400000U    VAL : 0x00000000U
+    // .. FPGA_AXDS1_RST = 0
+    // .. ==> 0XF8000240[21:21] = 0x00000000U
+    // ..     ==> MASK : 0x00200000U    VAL : 0x00000000U
+    // .. FPGA_AXDS0_RST = 0
+    // .. ==> 0XF8000240[20:20] = 0x00000000U
+    // ..     ==> MASK : 0x00100000U    VAL : 0x00000000U
+    // .. reserved_2 = 0
+    // .. ==> 0XF8000240[19:18] = 0x00000000U
+    // ..     ==> MASK : 0x000C0000U    VAL : 0x00000000U
+    // .. FSSW1_FPGA_RST = 0
+    // .. ==> 0XF8000240[17:17] = 0x00000000U
+    // ..     ==> MASK : 0x00020000U    VAL : 0x00000000U
+    // .. FSSW0_FPGA_RST = 0
+    // .. ==> 0XF8000240[16:16] = 0x00000000U
+    // ..     ==> MASK : 0x00010000U    VAL : 0x00000000U
+    // .. reserved_1 = 0
+    // .. ==> 0XF8000240[15:14] = 0x00000000U
+    // ..     ==> MASK : 0x0000C000U    VAL : 0x00000000U
+    // .. FPGA_FMSW1_RST = 0
+    // .. ==> 0XF8000240[13:13] = 0x00000000U
+    // ..     ==> MASK : 0x00002000U    VAL : 0x00000000U
+    // .. FPGA_FMSW0_RST = 0
+    // .. ==> 0XF8000240[12:12] = 0x00000000U
+    // ..     ==> MASK : 0x00001000U    VAL : 0x00000000U
+    // .. FPGA_DMA3_RST = 0
+    // .. ==> 0XF8000240[11:11] = 0x00000000U
+    // ..     ==> MASK : 0x00000800U    VAL : 0x00000000U
+    // .. FPGA_DMA2_RST = 0
+    // .. ==> 0XF8000240[10:10] = 0x00000000U
+    // ..     ==> MASK : 0x00000400U    VAL : 0x00000000U
+    // .. FPGA_DMA1_RST = 0
+    // .. ==> 0XF8000240[9:9] = 0x00000000U
+    // ..     ==> MASK : 0x00000200U    VAL : 0x00000000U
+    // .. FPGA_DMA0_RST = 0
+    // .. ==> 0XF8000240[8:8] = 0x00000000U
+    // ..     ==> MASK : 0x00000100U    VAL : 0x00000000U
+    // .. reserved = 0
+    // .. ==> 0XF8000240[7:4] = 0x00000000U
+    // ..     ==> MASK : 0x000000F0U    VAL : 0x00000000U
+    // .. FPGA3_OUT_RST = 0
+    // .. ==> 0XF8000240[3:3] = 0x00000000U
+    // ..     ==> MASK : 0x00000008U    VAL : 0x00000000U
+    // .. FPGA2_OUT_RST = 0
+    // .. ==> 0XF8000240[2:2] = 0x00000000U
+    // ..     ==> MASK : 0x00000004U    VAL : 0x00000000U
+    // .. FPGA1_OUT_RST = 0
+    // .. ==> 0XF8000240[1:1] = 0x00000000U
+    // ..     ==> MASK : 0x00000002U    VAL : 0x00000000U
+    // .. FPGA0_OUT_RST = 0
+    // .. ==> 0XF8000240[0:0] = 0x00000000U
+    // ..     ==> MASK : 0x00000001U    VAL : 0x00000000U
+    // .. 
+    EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U),
+    // .. FINISH: FPGA RESETS TO 0
+    // .. START: AFI REGISTERS
+    // .. .. START: AFI0 REGISTERS
+    // .. .. FINISH: AFI0 REGISTERS
+    // .. .. START: AFI1 REGISTERS
+    // .. .. FINISH: AFI1 REGISTERS
+    // .. .. START: AFI2 REGISTERS
+    // .. .. FINISH: AFI2 REGISTERS
+    // .. .. START: AFI3 REGISTERS
+    // .. .. FINISH: AFI3 REGISTERS
+    // .. FINISH: AFI REGISTERS
+    // .. START: LOCK IT BACK
+    // .. LOCK_KEY = 0X767B
+    // .. ==> 0XF8000004[15:0] = 0x0000767BU
+    // ..     ==> MASK : 0x0000FFFFU    VAL : 0x0000767BU
+    // .. 
+    EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
+    // .. FINISH: LOCK IT BACK
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+unsigned long ps7_debug_1_0[] = {
+    // START: top
+    // .. START: CROSS TRIGGER CONFIGURATIONS
+    // .. .. START: UNLOCKING CTI REGISTERS
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. KEY = 0XC5ACCE55
+    // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U
+    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0xC5ACCE55U
+    // .. .. 
+    EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
+    // .. .. FINISH: UNLOCKING CTI REGISTERS
+    // .. .. START: ENABLING CTI MODULES AND CHANNELS
+    // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS
+    // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS
+    // .. FINISH: CROSS TRIGGER CONFIGURATIONS
+    // FINISH: top
+    //
+    EMIT_EXIT(),
+
+    //
+};
+
+
+#include "xil_io.h"
+#define PS7_MASK_POLL_TIME 100000000
+
+char*
+getPS7MessageInfo(unsigned key) {
+
+  char* err_msg = "";
+  switch (key) {
+    case PS7_INIT_SUCCESS:                  err_msg = "PS7 initialization successful"; break;
+    case PS7_INIT_CORRUPT:                  err_msg = "PS7 init Data Corrupted"; break;
+    case PS7_INIT_TIMEOUT:                  err_msg = "PS7 init mask poll timeout"; break;
+    case PS7_POLL_FAILED_DDR_INIT:          err_msg = "Mask Poll failed for DDR Init"; break;
+    case PS7_POLL_FAILED_DMA:               err_msg = "Mask Poll failed for PLL Init"; break;
+    case PS7_POLL_FAILED_PLL:               err_msg = "Mask Poll failed for DMA done bit"; break;
+    default:                                err_msg = "Undefined error status"; break;
+  }
+  
+  return err_msg;  
+}
+
+unsigned long
+ps7GetSiliconVersion () {
+  // Read PS version from MCTRL register [31:28]
+  unsigned long mask = 0xF0000000;
+  unsigned long *addr = (unsigned long*) 0XF8007080;    
+  unsigned long ps_version = (*addr & mask) >> 28;
+  return ps_version;
+}
+
+void mask_write (unsigned long add , unsigned long  mask, unsigned long val ) {
+        unsigned long *addr = (unsigned long*) add;
+        *addr = ( val & mask ) | ( *addr & ~mask);
+        //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr);
+}
+
+
+int mask_poll(unsigned long add , unsigned long mask ) {
+        volatile unsigned long *addr = (volatile unsigned long*) add;
+        int i = 0;
+        while (!(*addr & mask)) {
+          if (i == PS7_MASK_POLL_TIME) {
+            return -1;
+          }
+          i++;
+        }
+     return 1;   
+        //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
+}
+
+unsigned long mask_read(unsigned long add , unsigned long mask ) {
+        unsigned long *addr = (unsigned long*) add;
+        unsigned long val = (*addr & mask);
+        //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
+        return val;
+}
+
+
+
+int
+ps7_config(unsigned long * ps7_config_init) 
+{
+    unsigned long *ptr = ps7_config_init;
+
+    unsigned long  opcode;            // current instruction ..
+    unsigned long  args[16];           // no opcode has so many args ...
+    int  numargs;           // number of arguments of this instruction
+    int  j;                 // general purpose index
+
+    volatile unsigned long *addr;         // some variable to make code readable
+    unsigned long  val,mask;              // some variable to make code readable
+
+    int finish = -1 ;           // loop while this is negative !
+    int i = 0;                  // Timeout variable
+    
+    while( finish < 0 ) {
+        numargs = ptr[0] & 0xF;
+        opcode = ptr[0] >> 4;
+
+        for( j = 0 ; j < numargs ; j ++ ) 
+            args[j] = ptr[j+1];
+        ptr += numargs + 1;
+        
+        
+        switch ( opcode ) {
+            
+        case OPCODE_EXIT:
+            finish = PS7_INIT_SUCCESS;
+            break;
+            
+        case OPCODE_CLEAR:
+            addr = (unsigned long*) args[0];
+            *addr = 0;
+            break;
+
+        case OPCODE_WRITE:
+            addr = (unsigned long*) args[0];
+            val = args[1];
+            *addr = val;
+            break;
+
+        case OPCODE_MASKWRITE:
+            addr = (unsigned long*) args[0];
+            mask = args[1];
+            val = args[2];
+            *addr = ( val & mask ) | ( *addr & ~mask);
+            break;
+
+        case OPCODE_MASKPOLL:
+            addr = (unsigned long*) args[0];
+            mask = args[1];
+            i = 0;
+            while (!(*addr & mask)) {
+                if (i == PS7_MASK_POLL_TIME) {
+                    finish = PS7_INIT_TIMEOUT;
+                    break;
+                }
+                i++;
+            }
+            break;
+        case OPCODE_MASKDELAY:
+            addr = (unsigned long*) args[0];
+            mask = args[1];
+            int delay = get_number_of_cycles_for_delay(mask);
+            perf_reset_and_start_timer(); 
+            while ((*addr < delay)) {
+            }
+            break;
+        default:
+            finish = PS7_INIT_CORRUPT;
+            break;
+        }
+    }
+    return finish;
+}
+
+unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
+unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
+unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
+unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+
+int
+ps7_post_config() 
+{
+  // Get the PS_VERSION on run time
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret = -1;
+  if (si_ver == PCW_SILICON_VERSION_1) {
+      ret = ps7_config (ps7_post_config_1_0);   
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+      ret = ps7_config (ps7_post_config_2_0);   
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else {
+      ret = ps7_config (ps7_post_config_3_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  }
+  return PS7_INIT_SUCCESS;
+}
+
+int
+ps7_debug() 
+{
+  // Get the PS_VERSION on run time
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret = -1;
+  if (si_ver == PCW_SILICON_VERSION_1) {
+      ret = ps7_config (ps7_debug_1_0);   
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+      ret = ps7_config (ps7_debug_2_0);   
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  } else {
+      ret = ps7_config (ps7_debug_3_0);
+      if (ret != PS7_INIT_SUCCESS) return ret;
+  }
+  return PS7_INIT_SUCCESS;
+}
+
+int
+ps7_init() 
+{
+  // Get the PS_VERSION on run time
+  unsigned long si_ver = ps7GetSiliconVersion ();
+  int ret;
+  //int pcw_ver = 0;
+
+  if (si_ver == PCW_SILICON_VERSION_1) {
+    ps7_mio_init_data = ps7_mio_init_data_1_0;
+    ps7_pll_init_data = ps7_pll_init_data_1_0;
+    ps7_clock_init_data = ps7_clock_init_data_1_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_1_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
+    //pcw_ver = 1;
+
+  } else if (si_ver == PCW_SILICON_VERSION_2) {
+    ps7_mio_init_data = ps7_mio_init_data_2_0;
+    ps7_pll_init_data = ps7_pll_init_data_2_0;
+    ps7_clock_init_data = ps7_clock_init_data_2_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_2_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
+    //pcw_ver = 2;
+
+  } else {
+    ps7_mio_init_data = ps7_mio_init_data_3_0;
+    ps7_pll_init_data = ps7_pll_init_data_3_0;
+    ps7_clock_init_data = ps7_clock_init_data_3_0;
+    ps7_ddr_init_data = ps7_ddr_init_data_3_0;
+    ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
+    //pcw_ver = 3;
+  }
+
+  // MIO init
+  ret = ps7_config (ps7_mio_init_data);  
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // PLL init
+  ret = ps7_config (ps7_pll_init_data); 
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // Clock init
+  ret = ps7_config (ps7_clock_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+  // DDR init
+  ret = ps7_config (ps7_ddr_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+
+
+
+  // Peripherals init
+  ret = ps7_config (ps7_peripherals_init_data);
+  if (ret != PS7_INIT_SUCCESS) return ret;
+  //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver);
+  return PS7_INIT_SUCCESS;
+}
+
+
+
+
+/* For delay calculation using global timer */
+
+/* start timer */
+ void perf_start_clock(void)
+{
+        *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable
+                                                      (1 << 3) | // Auto-increment
+                                                      (0 << 8) // Pre-scale
+        ); 
+}
+
+/* stop timer and reset timer count regs */
+ void perf_reset_clock(void)
+{
+        perf_disable_clock();
+        *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0;
+        *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0;
+}
+
+/* Compute mask for given delay in miliseconds*/
+int get_number_of_cycles_for_delay(unsigned int delay) 
+{
+  // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
+  return (APU_FREQ*delay/(2*1000));
+   
+}
+
+/* stop timer */
+ void perf_disable_clock(void)
+{
+        *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0;
+}
+
+void perf_reset_and_start_timer() 
+{
+            perf_reset_clock();
+            perf_start_clock();
+}
+
+
+
+
diff --git a/meta-xilinx-core/recipes-bsp/platform-init/platform-init/picozed-zynq7/ps7_init_gpl.h b/meta-xilinx-core/recipes-bsp/platform-init/platform-init/picozed-zynq7/ps7_init_gpl.h
new file mode 100644
index 00000000..df5205e8
--- /dev/null
+++ b/meta-xilinx-core/recipes-bsp/platform-init/platform-init/picozed-zynq7/ps7_init_gpl.h
@@ -0,0 +1,130 @@
+
+/******************************************************************************
+*
+* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+*
+*  This program is free software; you can redistribute it and/or modify
+*  it under the terms of the GNU General Public License as published by
+*  the Free Software Foundation; either version 2 of the License, or
+*  (at your option) any later version.
+*
+*  This program is distributed in the hope that it will be useful,
+*  but WITHOUT ANY WARRANTY; without even the implied warranty of
+*  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+*  GNU General Public License for more details.
+*  
+*  You should have received a copy of the GNU General Public License along
+*  with this program; if not, see <http://www.gnu.org/licenses/>
+*                                                                                                                                                                                          
+* 
+*******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file ps7_init.h
+*
+* This file can be included in FSBL code
+* to get prototype of ps7_init() function
+* and error codes
+*
+*****************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+//typedef unsigned int  u32;
+
+
+/** do we need to make this name more unique ? **/
+//extern u32 ps7_init_data[];
+extern unsigned long  * ps7_ddr_init_data;
+extern unsigned long  * ps7_mio_init_data;
+extern unsigned long  * ps7_pll_init_data;
+extern unsigned long  * ps7_clock_init_data;
+extern unsigned long  * ps7_peripherals_init_data;
+
+
+
+#define OPCODE_EXIT       0U
+#define OPCODE_CLEAR      1U
+#define OPCODE_WRITE      2U
+#define OPCODE_MASKWRITE  3U
+#define OPCODE_MASKPOLL   4U
+#define OPCODE_MASKDELAY  5U
+#define NEW_PS7_ERR_CODE 1
+
+/* Encode number of arguments in last nibble */
+#define EMIT_EXIT()                   ( (OPCODE_EXIT      << 4 ) | 0 )
+#define EMIT_CLEAR(addr)              ( (OPCODE_CLEAR     << 4 ) | 1 ) , addr
+#define EMIT_WRITE(addr,val)          ( (OPCODE_WRITE     << 4 ) | 2 ) , addr, val
+#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
+#define EMIT_MASKPOLL(addr,mask)      ( (OPCODE_MASKPOLL  << 4 ) | 2 ) , addr, mask
+#define EMIT_MASKDELAY(addr,mask)      ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
+
+/* Returns codes  of PS7_Init */
+#define PS7_INIT_SUCCESS   (0)    // 0 is success in good old C
+#define PS7_INIT_CORRUPT   (1)    // 1 the data is corrupted, and slcr reg are in corrupted state now
+#define PS7_INIT_TIMEOUT   (2)    // 2 when a poll operation timed out
+#define PS7_POLL_FAILED_DDR_INIT (3)    // 3 when a poll operation timed out for ddr init
+#define PS7_POLL_FAILED_DMA      (4)    // 4 when a poll operation timed out for dma done bit
+#define PS7_POLL_FAILED_PLL      (5)    // 5 when a poll operation timed out for pll sequence init
+
+
+/* Silicon Versions */
+#define PCW_SILICON_VERSION_1 0
+#define PCW_SILICON_VERSION_2 1
+#define PCW_SILICON_VERSION_3 2
+
+/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
+#define PS7_POST_CONFIG
+
+/* Freq of all peripherals */
+
+#define APU_FREQ  666666687
+#define DDR_FREQ  533333374
+#define DCI_FREQ  10158731
+#define QSPI_FREQ  200000000
+#define SMC_FREQ  10000000
+#define ENET0_FREQ  125000000
+#define ENET1_FREQ  10000000
+#define USB0_FREQ  60000000
+#define USB1_FREQ  60000000
+#define SDIO_FREQ  50000000
+#define UART_FREQ  50000000
+#define SPI_FREQ  10000000
+#define I2C_FREQ  111111115
+#define WDT_FREQ  111111115
+#define TTC_FREQ  50000000
+#define CAN_FREQ  10000000
+#define PCAP_FREQ  200000000
+#define TPIU_FREQ  200000000
+#define FPGA0_FREQ  100000000
+#define FPGA1_FREQ  100000000
+#define FPGA2_FREQ  33333336
+#define FPGA3_FREQ  50000000
+
+
+/* For delay calculation using global registers*/
+#define SCU_GLOBAL_TIMER_COUNT_L32      0xF8F00200
+#define SCU_GLOBAL_TIMER_COUNT_U32      0xF8F00204
+#define SCU_GLOBAL_TIMER_CONTROL        0xF8F00208
+#define SCU_GLOBAL_TIMER_AUTO_INC       0xF8F00218
+
+int ps7_config( unsigned long*);
+int ps7_init();
+int ps7_post_config();
+int ps7_debug();
+char* getPS7MessageInfo(unsigned key);
+
+void perf_start_clock(void);
+void perf_disable_clock(void);
+void perf_reset_clock(void);
+void perf_reset_and_start_timer(); 
+int get_number_of_cycles_for_delay(unsigned int delay); 
+#ifdef __cplusplus
+}
+#endif
+
+
diff --git a/meta-xilinx-core/recipes-bsp/pmu-firmware/pmu-rom_2018.1.bb b/meta-xilinx-core/recipes-bsp/pmu-firmware/pmu-rom_2018.1.bb
new file mode 100644
index 00000000..195c6309
--- /dev/null
+++ b/meta-xilinx-core/recipes-bsp/pmu-firmware/pmu-rom_2018.1.bb
@@ -0,0 +1,41 @@
+SUMMARY = "PMU ROM for QEMU"
+DESCRIPTION = "The ZynqMP PMU ROM for QEMU emulation"
+HOMEPAGE = "http://www.xilinx.com"
+SECTION = "bsp"
+
+# The BSP package does not include any license information.
+LICENSE = "Proprietary"
+LICENSE_FLAGS = "xilinx"
+LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/Proprietary;md5=0557f9d92cf58f2ccdd50f62f8ac0b28"
+
+COMPATIBLE_MACHINE = "zcu102-zynqmp"
+
+inherit deploy
+inherit xilinx-fetch-restricted
+
+BSP_NAME = "xilinx-zcu102"
+BSP_FILE = "${BSP_NAME}-v${PV}-final.bsp"
+SRC_URI = "https://www.xilinx.com/member/forms/download/xef.html?filename=${BSP_FILE};downloadfilename=${BSP_FILE}"
+SRC_URI[md5sum] = "cea5f11761e7f38cbfcf0a07a19094e0"
+SRC_URI[sha256sum] = "7ac0ac3a5fb7dd162c0a922c66edb33b5737955ef6570a1a1d3b15b4344f7cc1"
+
+INHIBIT_DEFAULT_DEPS = "1"
+PACKAGE_ARCH = "${MACHINE_ARCH}"
+
+do_compile() {
+        # Extract the rom into workdir
+        tar -xf ${WORKDIR}/${BSP_FILE} ${BSP_NAME}-${PV}/pre-built/linux/images/pmu_rom_qemu_sha3.elf -C ${S}
+        # tar preserves the tree, so use find to get the full path and move to to the root
+        for i in $(find ${S} -type f -name *.elf); do mv $i ${S}/pmu-rom.elf; done
+}
+
+do_install() {
+        :
+}
+
+do_deploy () {
+        install -D ${S}/pmu-rom.elf ${DEPLOYDIR}/pmu-rom.elf
+}
+
+addtask deploy before do_build after do_install
+
diff --git a/meta-xilinx-core/recipes-bsp/reference-design/kc705-bitstream_2021.2.bb b/meta-xilinx-core/recipes-bsp/reference-design/kc705-bitstream_2021.2.bb
new file mode 100644
index 00000000..e512777c
--- /dev/null
+++ b/meta-xilinx-core/recipes-bsp/reference-design/kc705-bitstream_2021.2.bb
@@ -0,0 +1,48 @@
+SUMMARY = "KC705 Pre-built Bitstream"
+DESCRIPTION = "A Pre-built bitstream for the KC705, which is capable of booting a Linux system."
+HOMEPAGE = "http://www.xilinx.com"
+SECTION = "bsp"
+
+# The BSP package does not include any license information.
+LICENSE = "Proprietary"
+LICENSE_FLAGS = "xilinx"
+LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/Proprietary;md5=0557f9d92cf58f2ccdd50f62f8ac0b28"
+
+COMPATIBLE_MACHINE = "kc705-microblazeel"
+
+inherit deploy
+inherit xilinx-fetch-restricted
+
+BSP_NAME = "xilinx-kc705"
+BSP_FILE = "${BSP_NAME}-v${PV}-final.bsp"
+SRC_URI = "https://www.xilinx.com/member/forms/download/xef.html?filename=${BSP_FILE};downloadfilename=${BSP_FILE}"
+SRC_URI[md5sum] = "5c0365a8a26cc27b4419aa1d7dd82351"
+SRC_URI[sha256sum] = "a909a91a37a9925ee2f972ccb10f986a26ff9785c1a71a483545a192783bf773"
+
+PROVIDES = "virtual/bitstream"
+
+FILES:${PN} += "/boot/download.bit"
+
+INHIBIT_DEFAULT_DEPS = "1"
+PACKAGE_ARCH = "${MACHINE_ARCH}"
+
+# deps needed to extract content from the .bsp file
+DEPENDS += "tar-native gzip-native"
+
+do_compile() {
+        # Extract the bitstream into workdir
+        tar -xf ${WORKDIR}/${BSP_FILE} ${BSP_NAME}-axi-full-${PV}/pre-built/linux/images/download.bit -C ${S}
+        # move the bit file to ${S}/ as it is in a subdir in the tar file
+        for i in $(find -type f -name download.bit); do mv $i ${S}; done
+}
+
+do_install() {
+        install -D ${S}/download.bit ${D}/boot/download.bit
+}
+
+do_deploy () {
+        install -D ${S}/download.bit ${DEPLOYDIR}/download.bit
+}
+
+addtask deploy before do_build after do_install
+
diff --git a/meta-xilinx-core/recipes-bsp/u-boot/files/0001-Remove-redundant-YYLOC-global-declaration.patch b/meta-xilinx-core/recipes-bsp/u-boot/files/0001-Remove-redundant-YYLOC-global-declaration.patch
new file mode 100644
index 00000000..7091098c
--- /dev/null
+++ b/meta-xilinx-core/recipes-bsp/u-boot/files/0001-Remove-redundant-YYLOC-global-declaration.patch
@@ -0,0 +1,28 @@
+From 8127b19aa42ccfb3faae1173a12b3eb0cebf8941 Mon Sep 17 00:00:00 2001
+From: Peter Robinson <pbrobinson@gmail.com>
+Date: Thu, 30 Jan 2020 09:37:15 +0000
+Subject: [PATCH] Remove redundant YYLOC global declaration
+
+Same as the upstream fix for building dtc with gcc 10.
+
+Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
+State: upstream (e33a814e772cdc36436c8c188d8c42d019fda639)
+---
+ scripts/dtc/dtc-lexer.l | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/scripts/dtc/dtc-lexer.l b/scripts/dtc/dtc-lexer.l
+index fd825ebba6..24af549977 100644
+--- a/scripts/dtc/dtc-lexer.l
++++ b/scripts/dtc/dtc-lexer.l
+@@ -38,7 +38,6 @@ LINECOMMENT   "//".*\n
+ #include "srcpos.h"
+ #include "dtc-parser.tab.h"
+ 
+-YYLTYPE yylloc;
+ extern bool treesource_error;
+ 
+ /* CAUTION: this will stop working if we ever use yyless() or yyunput() */
+-- 
+2.29.2
+
diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-spl-zynq-init.inc b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-spl-zynq-init.inc
new file mode 100644
index 00000000..6638c9e5
--- /dev/null
+++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-spl-zynq-init.inc
@@ -0,0 +1,70 @@
+inherit xilinx-platform-init
+
+FORCE_PLATFORM_INIT[doc] = "This variable is used to force the overriding of all platform init files in u-boot source."
+
+PLATFORM_BOARD_DIR ?= ""
+PLATFORM_BOARD_DIR:zynq = "board/xilinx/zynq"
+PLATFORM_BOARD_DIR:zynqmp = "board/xilinx/zynqmp"
+
+do_zynq_platform_init() {
+        for f in ${PLATFORM_INIT_FILES}; do
+                if [ -d "${S}/${PLATFORM_BOARD_DIR}/custom_hw_platform" ]; then
+                        cp ${PLATFORM_INIT_STAGE_DIR}/$f ${S}/${PLATFORM_BOARD_DIR}/custom_hw_platform/
+                else
+                        cp ${PLATFORM_INIT_STAGE_DIR}/$f ${S}/${PLATFORM_BOARD_DIR}/
+                fi
+                # Newer u-boot sources use the init files in a sub directory named
+                # based on the name of the device tree. This is not straight forward to
+                # detect. Instead of detecting just overwrite all the platform init
+                # files so that the correct one is always used. This shotgun approach
+                # only works due to this recipe being machine arch specific. Do this
+                # overwrite un-conditionally as there is no guarantees that the chosen
+                # board config does not have the device tree config set.
+                for i in ${S}/${PLATFORM_BOARD_DIR}/*/; do
+                        [ -d $i ] && cp ${PLATFORM_INIT_STAGE_DIR}/$f $i
+                done
+        done
+}
+
+python () {
+    # strip the tail _config/_defconfig for better comparison
+    def strip_config_name(c):
+        for i in ["_config", "_defconfig"]:
+            if c.endswith(i):
+                return c[0:len(c) - len(i)]
+        return c
+
+    if d.getVar("SOC_FAMILY") not in ["zynq", "zynqmp"]:
+        # continue on this is not a zynq/zynqmp target
+        return
+
+    # Determine if target machine needs to provide a custom platform init files
+    if d.getVar("SPL_BINARY"):
+        hasconfigs = [strip_config_name(c) for c in (d.getVar("HAS_PLATFORM_INIT") or "").split()]
+        currentconfig = strip_config_name(d.getVar("UBOOT_MACHINE"))
+
+        # only add the dependency if u-boot doesn't already provide the platform init files
+        if (currentconfig not in hasconfigs) or (d.getVar("FORCE_PLATFORM_INIT") == "1"):
+            # force the dependency on a recipe that provides the platform init files
+            d.appendVar("DEPENDS", " virtual/xilinx-platform-init")
+            # setup task to modify platform init after unpack and prepare_recipe_sysroot, and before configure
+            bb.build.addtask("do_zynq_platform_init", "do_configure", "do_unpack do_prepare_recipe_sysroot", d)
+
+    if "boot.bin" not in d.getVar("SPL_BINARY"):
+        # not deploying the boot.bin, just building SPL
+        return
+
+    # assume that U-Boot is to provide the boot.bin if no other provides are selected or U-Boot is selected
+    providesbin = not(d.getVar("PREFERRED_PROVIDER_virtual/boot-bin")) or d.getVar("PREFERRED_PROVIDER_virtual/boot-bin") == d.getVar("PN")
+    if providesbin:
+        # add provides, if U-Boot is set to provide boot.bin
+        d.appendVar("PROVIDES", " virtual/boot-bin")
+    else:
+        # prevent U-Boot from deploying the boot.bin
+        d.setVar("SPL_BINARY", "")
+
+    if providesbin and d.getVar("SOC_FAMILY") in ["zynqmp"]:
+        # setup PMU Firmware path via MAKEFLAGS
+        d.appendVar("EXTRA_OEMAKE", " CONFIG_PMUFW_INIT_FILE=\"{0}\"".format("${PMU_FIRMWARE_DEPLOY_DIR}/${PMU_FIRMWARE_IMAGE_NAME}.bin"))
+}
+
diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx-dev.bb b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx-dev.bb
new file mode 100644
index 00000000..3e40bfa1
--- /dev/null
+++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx-dev.bb
@@ -0,0 +1,28 @@
+# This recipe allows for a 'bleeding edge' u-boot-xlnx build.
+# Since this tree is frequently updated, AUTOREV is used to track its contents.
+#
+# To enable this recipe, set the following in your machine or local.conf
+#   PREFERRED_PROVIDER_virtual/bootloader ?= "u-boot-xlnx-dev"
+
+UBRANCH ?= "master"
+
+include u-boot-xlnx.inc
+include u-boot-spl-zynq-init.inc
+
+LICENSE = "GPLv2+"
+LIC_FILES_CHKSUM = "file://README;beginline=1;endline=6;md5=157ab8408beab40cd8ce1dc69f702a6c"
+
+SRCREV_DEFAULT = "aebea9d20a5aa32857f320c07ca8f9fd1b3dec1f"
+SRCREV ?= "${@oe.utils.conditional("PREFERRED_PROVIDER_virtual/bootloader", "u-boot-xlnx-dev", "${AUTOREV}", "${SRCREV_DEFAULT}", d)}"
+
+PV = "${UBRANCH}-xilinx-dev+git${SRCPV}"
+
+# Newer versions of u-boot have support for these
+HAS_PLATFORM_INIT ?= " \
+                zynq_microzed_config \
+                zynq_zed_config \
+                zynq_zc702_config \
+                zynq_zc706_config \
+                zynq_zybo_config \
+                "
+
diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx.inc b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx.inc
new file mode 100644
index 00000000..893b8f6c
--- /dev/null
+++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx.inc
@@ -0,0 +1,24 @@
+require recipes-bsp/u-boot/u-boot.inc
+
+DEPENDS += "bc-native dtc-native bison-native"
+
+XILINX_RELEASE_VERSION ?= ""
+UBOOT_VERSION_EXTENSION ?= "-xilinx-${XILINX_RELEASE_VERSION}"
+PV = "${UBOOT_VERSION}${UBOOT_VERSION_EXTENSION}+git${SRCPV}"
+
+UBOOTURI ?= "git://github.com/Xilinx/u-boot-xlnx.git;protocol=https"
+UBRANCH ?= ""
+UBRANCHARG = "${@['nobranch=1', 'branch=${UBRANCH}'][d.getVar('UBRANCH', True) != '']}"
+
+SRC_URI = "${UBOOTURI};${UBRANCHARG}"
+
+S = "${WORKDIR}/git"
+B = "${WORKDIR}/build"
+
+FILESEXTRAPATHS:prepend := "${THISDIR}/u-boot:"
+
+SYSROOT_DIRS += "/boot"
+
+# Specify a default in case boardvariant isn't available
+BOARDVARIANT_ARCH ??= "${MACHINE_ARCH}"
+PACKAGE_ARCH = "${BOARDVARIANT_ARCH}"
diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2021.2.bb b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2021.2.bb
new file mode 100644
index 00000000..a4fedbe2
--- /dev/null
+++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2021.2.bb
@@ -0,0 +1,19 @@
+UBOOT_VERSION = "v2021.01"
+
+UBRANCH ?= "xlnx_rebase_v2021.01"
+
+SRCREV = "63b6d260dbe64a005407439e2caeb32da9025954"
+
+include u-boot-xlnx.inc
+include u-boot-spl-zynq-init.inc
+
+LICENSE = "GPLv2+"
+LIC_FILES_CHKSUM = "file://README;beginline=1;endline=4;md5=744e7e3bb0c94b4b9f6b3db3bf893897"
+
+# u-boot-xlnx has support for these
+HAS_PLATFORM_INIT ?= " \
+                xilinx_zynqmp_virt_config \
+                xilinx_zynq_virt_defconfig \
+                xilinx_versal_vc_p_a2197_revA_x_prc_01_revA \
+                "
+
diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr.bb b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr.bb
new file mode 100644
index 00000000..a75484a8
--- /dev/null
+++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr.bb
@@ -0,0 +1,238 @@
+SUMMARY = "U-boot boot scripts for Xilinx devices"
+LICENSE = "MIT"
+LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/MIT;md5=0835ade698e0bcf8506ecda2f7b4f302"
+
+DEPENDS = "u-boot-mkimage-native"
+
+inherit deploy nopackages image-wic-utils
+
+INHIBIT_DEFAULT_DEPS = "1"
+
+COMPATIBLE_MACHINE ?= "^$"
+COMPATIBLE_MACHINE:zynqmp = "zynqmp"
+COMPATIBLE_MACHINE:zynq = "zynq"
+COMPATIBLE_MACHINE:versal = "versal"
+COMPATIBLE_MACHINE:microblaze = "microblaze"
+
+KERNELDT = "${@os.path.basename(d.getVar('KERNEL_DEVICETREE').split(' ')[0]) if d.getVar('KERNEL_DEVICETREE') else ''}"
+DEVICE_TREE_NAME ?= "${@bb.utils.contains('PREFERRED_PROVIDER_virtual/dtb', 'device-tree', 'system.dtb', d.getVar('KERNELDT'), d)}"
+#Need to copy a rootfs.cpio.gz.u-boot as uramdisk.image.gz into boot partition
+RAMDISK_IMAGE ?= ""
+RAMDISK_IMAGE:zynq ?= "uramdisk.image.gz"
+
+PXERAMDISK_IMAGE ?= "${@'ramdisk.cpio.gz.u-boot' if d.getVar('INITRAMFS_IMAGE') and d.getVar('INITRAMFS_IMAGE').find('initramfs') > 0 else '${RAMDISK_IMAGE}'}"
+
+KERNEL_BOOTCMD:zynqmp ?= "booti"
+KERNEL_BOOTCMD:zynq ?= "bootm"
+KERNEL_BOOTCMD:versal ?= "booti"
+KERNEL_BOOTCMD:microblaze ?= "bootm"
+
+BOOTMODE ?= "sd"
+BOOTFILE_EXT ?= ".${SOC_FAMILY}"
+
+#Make this value to "1" to skip appending base address to ddr offsets.
+SKIP_APPEND_BASEADDR ?= "0"
+
+DDR_BASEADDR ?= "0x0"
+DDR_BASEADDR:microblaze ?= "0x80000000"
+PRE_BOOTENV ?= ""
+
+SRC_URI = " \
+            file://boot.cmd.sd.zynq \
+            file://boot.cmd.sd.zynqmp \
+            file://boot.cmd.sd.versal \
+            file://boot.cmd.qspi.versal \
+            file://boot.cmd.generic \
+            file://boot.cmd.ubifs \
+            file://pxeboot.pxe \
+            "
+
+# Specify a default in case boardvariant isn't available
+BOARDVARIANT_ARCH ??= "${MACHINE_ARCH}"
+PACKAGE_ARCH = "${BOARDVARIANT_ARCH}"
+
+# On zynqmp-dr, we know we're different so if BOARD is not defined, fall back
+# to the SOC_VARIANT_ARCH instead
+SOC_VARIANT_ARCH ??= "${MACHINE_ARCH}"
+PACKAGE_ARCH:zynqmp-dr = "${@['${BOARDVARIANT_ARCH}', '${SOC_VARIANT_ARCH}'][d.getVar('BOARDVARIANT_ARCH')==d.getVar('MACHINE_ARCH')]}"
+
+inherit image-artifact-names
+UENV_TEXTFILE ?= "uEnv.txt"
+UENV_MMC_OFFSET:zynqmp ?= "0x200000"
+UENV_MMC_OFFSET:zynq ?= "0x2080000"
+UENV_MMC_OFFSET:versal ?= "0x200000"
+UENV_MMC_OFFSET:microblaze ?= "0x0"
+
+UENV_MMC_LOAD_ADDRESS ?= "${@append_baseaddr(d,d.getVar('UENV_MMC_OFFSET'))}"
+
+UBOOTSCR_BASE_NAME ?= "${PN}-${PKGE}-${PKGV}-${PKGR}${IMAGE_VERSION_SUFFIX}"
+UBOOTPXE_CONFIG ?= "pxelinux.cfg"
+UBOOTPXE_CONFIG_NAME = "${UBOOTPXE_CONFIG}${IMAGE_VERSION_SUFFIX}"
+
+DEVICETREE_ADDRESS ?= "${@append_baseaddr(d,d.getVar('DEVICETREE_OFFSET'))}"
+
+DEVICETREE_OFFSET:microblaze ?= "0x1e00000"
+DEVICETREE_OFFSET:zynqmp ?= "0x100000"
+DEVICETREE_OFFSET:zynq ?= "0x2000000"
+DEVICETREE_OFFSET:versal ?= "0x1000"
+
+KERNEL_LOAD_ADDRESS ?= "${@append_baseaddr(d,d.getVar('KERNEL_OFFSET'))}"
+
+KERNEL_OFFSET:microblaze ?= "0x0"
+KERNEL_OFFSET:zynqmp ?= "0x200000"
+KERNEL_OFFSET:zynq ?= "0x2080000"
+KERNEL_OFFSET:versal ?= "0x200000"
+
+KERNEL_IMAGE ?= "${KERNEL_IMAGETYPE}"
+
+RAMDISK_IMAGE_ADDRESS ?= "${@append_baseaddr(d,d.getVar('RAMDISK_OFFSET'))}"
+
+RAMDISK_OFFSET:microblaze ?= "0x2e00000"
+RAMDISK_OFFSET:zynq ?= "0x4000000"
+RAMDISK_OFFSET:zynqmp ?= "0x4000000"
+RAMDISK_OFFSET:versal ?= "0x6000000"
+
+FIT_IMAGE_LOAD_ADDRESS ?= "${@append_baseaddr(d,d.getVar('FIT_IMAGE_OFFSET'))}"
+FIT_IMAGE_OFFSET ?= "0x10000000"
+FIT_IMAGE ?= "image.ub"
+
+## Below offsets and sizes are based on 32MB QSPI Memory for zynq
+## For MB
+## Load boot.scr at 0xFC0000 -> 15MB of QSPI/NAND Memory
+QSPI_KERNEL_OFFSET:microblaze ?= "0xBC0000"
+QSPI_KERNEL_SIZE:microblaze ?= "0x500000"
+QSPI_RAMDISK_SIZE:microblaze ?= "0xA00000"
+
+## For zynq
+## Load boot.scr at 0xFC0000 -> 15MB of QSPI/NAND Memory
+QSPI_KERNEL_OFFSET:zynq ?= "0x1000000"
+QSPI_RAMDISK_OFFSET:zynq ?= "0x1580000"
+
+NAND_KERNEL_OFFSET:zynq ?= "0x1000000"
+NAND_RAMDISK_OFFSET:zynq ?= "0x4600000"
+
+QSPI_KERNEL_SIZE:zynq ?= "0x500000"
+QSPI_RAMDISK_SIZE:zynq ?= "0xA00000"
+
+NAND_KERNEL_SIZE ?= "0x3200000"
+NAND_RAMDISK_SIZE ?= "0x3200000"
+
+## Below offsets and sizes are based on 128MB QSPI Memory for zynqmp/versal
+## For zynqMP
+## Load boot.scr at 0x3E80000 -> 62MB of QSPI/NAND Memory
+QSPI_KERNEL_OFFSET ?= "0xF00000"
+QSPI_KERNEL_OFFSET:zynqmpdr ?= "0x3F00000"
+QSPI_RAMDISK_OFFSET ?= "0x4000000"
+QSPI_RAMDISK_OFFSET:zynqmpdr ?= "0x5D00000"
+
+NAND_KERNEL_OFFSET:zynqmp ?= "0x4100000"
+NAND_RAMDISK_OFFSET:zynqmp ?= "0x7800000"
+
+QSPI_KERNEL_SIZE:zynqmp ?= "0x1D00000"
+QSPI_RAMDISK_SIZE ?= "0x4000000"
+QSPI_RAMDISK_SIZE:zynqmpdr ?= "0x1D00000"
+
+## For versal
+## Load boot.scr at 0x7F80000 -> 127MB of QSPI/NAND Memory
+QSPI_KERNEL_OFFSET:versal ?= "0xF00000"
+QSPI_RAMDISK_OFFSET:versal ?= "0x2E00000"
+
+NAND_KERNEL_OFFSET:versal ?= "0x4100000"
+NAND_RAMDISK_OFFSET:versal ?= "0x8200000"
+
+QSPI_KERNEL_SIZE:versal ?= "0x1D00000"
+QSPI_RAMDISK_SIZE:versal ?= "0x4000000"
+
+QSPI_KERNEL_IMAGE:microblaze ?= "image.ub"
+QSPI_KERNEL_IMAGE:zynq ?= "image.ub"
+QSPI_KERNEL_IMAGE:zynqmp ?= "image.ub"
+QSPI_KERNEL_IMAGE:versal ?= "image.ub"
+
+NAND_KERNEL_IMAGE ?= "image.ub"
+
+QSPI_FIT_IMAGE_OFFSET ?= "0x1080000"
+QSPI_FIT_IMAGE_SIZE ?= "0x6400000"
+QSPI_FIT_IMAGE_SIZE:zynqmpdr ?= "0x3F00000"
+QSPI_FIT_IMAGE_SIZE:zynq ?= "0xF00000"
+QSPI_FIT_IMAGE_SIZE:microblaze ?= "0xF00000"
+
+NAND_FIT_IMAGE_OFFSET ?= "0x1080000"
+NAND_FIT_IMAGE_SIZE ?= "0x6400000"
+
+SDBOOTDEV ?= "0"
+
+BITSTREAM_LOAD_ADDRESS ?= "0x100000"
+
+do_configure[noexec] = "1"
+do_install[noexec] = "1"
+
+def append_baseaddr(d,offset):
+    skip_append = d.getVar('SKIP_APPEND_BASEADDR') or ""
+    if skip_append == "1":
+        return offset
+    import subprocess
+    baseaddr = d.getVar('DDR_BASEADDR') or "0x0"
+    subcmd = "$((%s+%s));" % (baseaddr,offset)
+    cmd = "printf '0x%08x' " + str(subcmd)
+    output = subprocess.check_output(cmd, shell=True).decode("utf-8")
+    return output
+
+def get_bitstream_load_type(d):
+    if boot_files_bitstream(d)[1] :
+        return "loadb"
+    else:
+        return "load"
+
+do_compile() {
+    sed -e 's/@@KERNEL_IMAGETYPE@@/${KERNEL_IMAGETYPE}/' \
+        -e 's/@@KERNEL_LOAD_ADDRESS@@/${KERNEL_LOAD_ADDRESS}/' \
+        -e 's/@@DEVICE_TREE_NAME@@/${DEVICE_TREE_NAME}/' \
+        -e 's/@@DEVICETREE_ADDRESS@@/${DEVICETREE_ADDRESS}/' \
+        -e 's/@@RAMDISK_IMAGE@@/${RAMDISK_IMAGE}/' \
+        -e 's/@@RAMDISK_IMAGE_ADDRESS@@/${RAMDISK_IMAGE_ADDRESS}/' \
+        -e 's/@@KERNEL_BOOTCMD@@/${KERNEL_BOOTCMD}/' \
+        -e 's/@@SDBOOTDEV@@/${SDBOOTDEV}/' \    
+        -e 's/@@BITSTREAM@@/${@boot_files_bitstream(d)[0]}/g' \ 
+        -e 's/@@BITSTREAM_LOAD_ADDRESS@@/${BITSTREAM_LOAD_ADDRESS}/g' \ 
+        -e 's/@@BITSTREAM_IMAGE@@/${@boot_files_bitstream(d)[0]}/g' \   
+        -e 's/@@BITSTREAM_LOAD_TYPE@@/${@get_bitstream_load_type(d)}/g' \       
+        -e 's/@@QSPI_KERNEL_OFFSET@@/${QSPI_KERNEL_OFFSET}/' \
+        -e 's/@@NAND_KERNEL_OFFSET@@/${NAND_KERNEL_OFFSET}/' \
+        -e 's/@@QSPI_KERNEL_SIZE@@/${QSPI_KERNEL_SIZE}/' \
+        -e 's/@@NAND_KERNEL_SIZE@@/${NAND_KERNEL_SIZE}/' \
+        -e 's/@@QSPI_RAMDISK_OFFSET@@/${QSPI_RAMDISK_OFFSET}/' \
+        -e 's/@@NAND_RAMDISK_OFFSET@@/${NAND_RAMDISK_OFFSET}/' \
+        -e 's/@@QSPI_RAMDISK_SIZE@@/${QSPI_RAMDISK_SIZE}/' \
+        -e 's/@@NAND_RAMDISK_SIZE@@/${NAND_RAMDISK_SIZE}/' \
+        -e 's/@@KERNEL_IMAGE@@/${KERNEL_IMAGE}/' \
+        -e 's/@@QSPI_KERNEL_IMAGE@@/${QSPI_KERNEL_IMAGE}/' \
+        -e 's/@@NAND_KERNEL_IMAGE@@/${NAND_KERNEL_IMAGE}/' \
+        -e 's/@@FIT_IMAGE_LOAD_ADDRESS@@/${FIT_IMAGE_LOAD_ADDRESS}/' \
+        -e 's/@@QSPI_FIT_IMAGE_OFFSET@@/${QSPI_FIT_IMAGE_OFFSET}/' \
+        -e 's/@@QSPI_FIT_IMAGE_SIZE@@/${QSPI_FIT_IMAGE_SIZE}/' \
+        -e 's/@@NAND_FIT_IMAGE_OFFSET@@/${NAND_FIT_IMAGE_OFFSET}/' \
+        -e 's/@@NAND_FIT_IMAGE_SIZE@@/${NAND_FIT_IMAGE_SIZE}/' \
+        -e 's/@@FIT_IMAGE@@/${FIT_IMAGE}/' \
+        -e 's/@@PRE_BOOTENV@@/${PRE_BOOTENV}/' \
+        -e 's/@@UENV_MMC_LOAD_ADDRESS@@/${UENV_MMC_LOAD_ADDRESS}/' \
+        -e 's/@@UENV_TEXTFILE@@/${UENV_TEXTFILE}/' \
+        -e 's/@@RAMDISK_IMAGE1@@/${RAMDISK_IMAGE1}/' \
+        "${WORKDIR}/boot.cmd.${BOOTMODE}${BOOTFILE_EXT}" > "${WORKDIR}/boot.cmd"
+    mkimage -A arm -T script -C none -n "Boot script" -d "${WORKDIR}/boot.cmd" boot.scr
+    sed -e 's/@@KERNEL_IMAGETYPE@@/${KERNEL_IMAGETYPE}/' \
+        -e 's/@@DEVICE_TREE_NAME@@/${DEVICE_TREE_NAME}/' \
+        -e 's/@@RAMDISK_IMAGE@@/${PXERAMDISK_IMAGE}/' \
+        "${WORKDIR}/pxeboot.pxe" > "pxeboot.pxe"
+}
+
+
+do_deploy() {
+    install -d ${DEPLOYDIR}
+    install -m 0644 boot.scr ${DEPLOYDIR}/${UBOOTSCR_BASE_NAME}.scr
+    ln -sf ${UBOOTSCR_BASE_NAME}.scr ${DEPLOYDIR}/boot.scr
+    install -d ${DEPLOYDIR}/pxeboot/${UBOOTPXE_CONFIG_NAME}
+    install -m 0644 pxeboot.pxe ${DEPLOYDIR}/pxeboot/${UBOOTPXE_CONFIG_NAME}/default
+    ln -sf pxeboot/${UBOOTPXE_CONFIG_NAME} ${DEPLOYDIR}/${UBOOTPXE_CONFIG}
+}
+
+addtask do_deploy after do_compile before do_build
diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.generic b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.generic
new file mode 100644
index 00000000..0249a8a0
--- /dev/null
+++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.generic
@@ -0,0 +1,70 @@
+# This is a boot script for U-Boot
+# Generate boot.scr:
+# mkimage -c none -A arm -T script -d boot.cmd.default boot.scr
+#
+################
+fitimage_name=@@FIT_IMAGE@@
+kernel_name=@@KERNEL_IMAGE@@
+ramdisk_name=@@RAMDISK_IMAGE1@@
+rootfs_name=@@RAMDISK_IMAGE@@
+@@PRE_BOOTENV@@
+
+for boot_target in ${boot_targets};
+do
+        echo "Trying to load boot images from ${boot_target}"
+        if test "${boot_target}" = "jtag" ; then
+                @@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ @@RAMDISK_IMAGE_ADDRESS@@ @@DEVICETREE_ADDRESS@@
+        fi
+        if test "${boot_target}" = "mmc0" || test "${boot_target}" = "mmc1" ; then
+                if test -e ${devtype} ${devnum}:${distro_bootpart} /@@UENV_TEXTFILE@@; then
+                        fatload ${devtype} ${devnum}:${distro_bootpart} @@UENV_MMC_LOAD_ADDRESS@@ @@UENV_TEXTFILE@@;
+                        echo "Importing environment(@@UENV_TEXTFILE@@) from ${boot_target}..."
+                        env import -t @@UENV_MMC_LOAD_ADDRESS@@ $filesize
+                        if test -n $uenvcmd; then
+                                echo "Running uenvcmd ...";
+                                run uenvcmd;
+                        fi
+                fi
+                if test -e ${devtype} ${devnum}:${distro_bootpart} /${fitimage_name}; then
+                        fatload ${devtype} ${devnum}:${distro_bootpart} @@FIT_IMAGE_LOAD_ADDRESS@@ ${fitimage_name};
+                        bootm @@FIT_IMAGE_LOAD_ADDRESS@@;
+                fi
+                if test -e ${devtype} ${devnum}:${distro_bootpart} /${kernel_name}; then
+                        fatload ${devtype} ${devnum}:${distro_bootpart} @@KERNEL_LOAD_ADDRESS@@ ${kernel_name};
+                fi
+                if test -e ${devtype} ${devnum}:${distro_bootpart} /system.dtb; then
+                        fatload ${devtype} ${devnum}:${distro_bootpart} @@DEVICETREE_ADDRESS@@ system.dtb;
+                fi
+                if test -e ${devtype} ${devnum}:${distro_bootpart} /${ramdisk_name} && test "${skip_tinyramdisk}" != "yes"; then
+                        fatload ${devtype} ${devnum}:${distro_bootpart} @@RAMDISK_IMAGE_ADDRESS@@ ${ramdisk_name};
+                        @@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ @@RAMDISK_IMAGE_ADDRESS@@ @@DEVICETREE_ADDRESS@@
+                fi
+                if test -e ${devtype} ${devnum}:${distro_bootpart} /${rootfs_name} && test "${skip_ramdisk}" != "yes"; then
+                        fatload ${devtype} ${devnum}:${distro_bootpart} @@RAMDISK_IMAGE_ADDRESS@@ ${rootfs_name};
+                        @@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ @@RAMDISK_IMAGE_ADDRESS@@ @@DEVICETREE_ADDRESS@@
+                fi
+                @@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ - @@DEVICETREE_ADDRESS@@
+        fi
+        if test "${boot_target}" = "xspi0" || test "${boot_target}" = "qspi" || test "${boot_target}" = "qspi0"; then
+                sf probe 0 0 0;
+                sf read @@FIT_IMAGE_LOAD_ADDRESS@@ @@QSPI_FIT_IMAGE_OFFSET@@ @@QSPI_FIT_IMAGE_SIZE@@
+                bootm @@FIT_IMAGE_LOAD_ADDRESS@@;
+                echo "Booting using Fit image failed"
+
+                sf read @@KERNEL_LOAD_ADDRESS@@ @@QSPI_KERNEL_OFFSET@@ @@QSPI_KERNEL_SIZE@@
+                sf read @@RAMDISK_IMAGE_ADDRESS@@ @@QSPI_RAMDISK_OFFSET@@ @@QSPI_RAMDISK_SIZE@@
+                @@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ @@RAMDISK_IMAGE_ADDRESS@@ @@DEVICETREE_ADDRESS@@;
+                echo "Booting using Separate images failed"
+        fi
+        if test "${boot_target}" = "nand" || test "${boot_target}" = "nand0"; then
+                nand info;
+                nand read @@FIT_IMAGE_LOAD_ADDRESS@@ @@NAND_FIT_IMAGE_OFFSET@@ @@NAND_FIT_IMAGE_SIZE@@
+                bootm @@FIT_IMAGE_LOAD_ADDRESS@@;
+                echo "Booting using Fit image failed"
+
+                nand read @@KERNEL_LOAD_ADDRESS@@ @@NAND_KERNEL_OFFSET@@ @@NAND_KERNEL_SIZE@@
+                nand read @@RAMDISK_IMAGE_ADDRESS@@ @@NAND_RAMDISK_OFFSET@@ @@NAND_RAMDISK_SIZE@@
+                @@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ @@RAMDISK_IMAGE_ADDRESS@@ @@DEVICETREE_ADDRESS@@;
+                echo "Booting using Separate images failed"
+        fi
+done
diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.qspi.versal b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.qspi.versal
new file mode 100644
index 00000000..d56b7c8c
--- /dev/null
+++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.qspi.versal
@@ -0,0 +1 @@
+@@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ @@RAMDISK_IMAGE_ADDRESS@@ @@DEVICETREE_ADDRESS@@
diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.sd.versal b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.sd.versal
new file mode 100644
index 00000000..10e83cd0
--- /dev/null
+++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.sd.versal
@@ -0,0 +1,3 @@
+setenv bootargs $bootargs root=/dev/mmcblk0p2 rw rootwait clk_ignore_unused
+fatload mmc $sdbootdev:$partid @@KERNEL_LOAD_ADDRESS@@ @@KERNEL_IMAGETYPE@@
+@@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ - @@DEVICETREE_ADDRESS@@
diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.sd.zynq b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.sd.zynq
new file mode 100644
index 00000000..bbd2e01e
--- /dev/null
+++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.sd.zynq
@@ -0,0 +1,7 @@
+if test -n "@@BITSTREAM@@"; then
+   fatload mmc $sdbootdev @@BITSTREAM_LOAD_ADDRESS@@ @@BITSTREAM_IMAGE@@ && fpga @@BITSTREAM_LOAD_TYPE@@ 0 @@BITSTREAM_LOAD_ADDRESS@@ ${filesize}
+fi
+fatload mmc 0 @@DEVICETREE_ADDRESS@@ @@DEVICE_TREE_NAME@@
+fatload mmc 0 @@KERNEL_LOAD_ADDRESS@@ @@KERNEL_IMAGETYPE@@
+fatload mmc 0 @@RAMDISK_IMAGE_ADDRESS@@ @@RAMDISK_IMAGE@@
+@@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ @@RAMDISK_IMAGE_ADDRESS@@ @@DEVICETREE_ADDRESS@@
diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.sd.zynqmp b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.sd.zynqmp
new file mode 100644
index 00000000..b234a8df
--- /dev/null
+++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.sd.zynqmp
@@ -0,0 +1,8 @@
+setenv sdbootdev @@SDBOOTDEV@@
+setenv bootargs $bootargs root=/dev/mmcblk${sdbootdev}p2 rw rootwait earlycon clk_ignore_unused
+if test -n "@@BITSTREAM@@"; then
+   fatload mmc $sdbootdev @@BITSTREAM_LOAD_ADDRESS@@ @@BITSTREAM_IMAGE@@ && fpga @@BITSTREAM_LOAD_TYPE@@ 0 @@BITSTREAM_LOAD_ADDRESS@@ ${filesize}
+fi
+fatload mmc $sdbootdev @@DEVICETREE_ADDRESS@@ @@DEVICE_TREE_NAME@@
+fatload mmc $sdbootdev:$partid @@KERNEL_LOAD_ADDRESS@@ @@KERNEL_IMAGETYPE@@
+@@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ - @@DEVICETREE_ADDRESS@@
diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.ubifs b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.ubifs
new file mode 100644
index 00000000..60c48eda
--- /dev/null
+++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr/boot.cmd.ubifs
@@ -0,0 +1,54 @@
+# This is a boot script for U-Boot
+# Generate boot.scr:
+# mkimage -c none -A arm -T script -d boot.cmd.default boot.scr
+#
+################
+@@PRE_BOOTENV@@
+
+for boot_target in ${boot_targets};
+do
+        if test "${boot_target}" = "xspi0" || test "${boot_target}" = "qspi" || test "${boot_target}" = "qspi0"; then
+                ubifsls @@FIT_IMAGE@@
+                if test $? = 0; then
+                        ubifsload @@FIT_IMAGE_LOAD_ADDRESS@@ @@FIT_IMAGE@@;
+                        bootm @@FIT_IMAGE_LOAD_ADDRESS@@;
+                fi
+                ubifsls @@KERNEL_IMAGE@@
+                if test $? = 0; then
+                        ubifsload @@KERNEL_LOAD_ADDRESS@@ @@KERNEL_IMAGE@@;
+                fi
+                ubifsls system.dtb
+                if test $? = 0; then
+                        ubifsload @@DEVICETREE_ADDRESS@@ system.dtb
+                fi
+                ubifsls @@RAMDISK_IMAGE@@
+                if test $? = 0; then
+                        ubifsload @@RAMDISK_IMAGE_ADDRESS@@ @@RAMDISK_IMAGE@@
+                        @@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ @@RAMDISK_IMAGE_ADDRESS@@ @@DEVICETREE_ADDRESS@@
+                        exit;
+                fi
+                @@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ - @@DEVICETREE_ADDRESS@@
+                exit;
+        fi
+        if test "${boot_target}" = "mmc0" || test "${boot_target}" = "mmc1" ; then
+                run bootcmd_${boot_target};
+                if test -e ${devtype} ${devnum}:${distro_bootpart} /@@FIT_IMAGE@@; then
+                        ext4load ${devtype} ${devnum}:${distro_bootpart} @@FIT_IMAGE_LOAD_ADDRESS@@ @@FIT_IMAGE@@;
+                        bootm @@FIT_IMAGE_LOAD_ADDRESS@@;
+                        exit;
+                fi
+                if test -e ${devtype} ${devnum}:${distro_bootpart} /@@KERNEL_IMAGE@@; then
+                        ext4load ${devtype} ${devnum}:${distro_bootpart} @@KERNEL_LOAD_ADDRESS@@ @@KERNEL_IMAGE@@;
+                fi
+                if test -e ${devtype} ${devnum}:${distro_bootpart} /system.dtb; then
+                        ext4load ${devtype} ${devnum}:${distro_bootpart} @@DEVICETREE_ADDRESS@@ system.dtb;
+                fi
+                if test -e ${devtype} ${devnum}:${distro_bootpart} /@@RAMDISK_IMAGE@@; then
+                        ext4load ${devtype} ${devnum}:${distro_bootpart} @@RAMDISK_IMAGE_ADDRESS@@ @@RAMDISK_IMAGE@@;
+                        @@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ @@RAMDISK_IMAGE_ADDRESS@@ @@DEVICETREE_ADDRESS@@
+                        exit;
+                fi
+                @@KERNEL_BOOTCMD@@ @@KERNEL_LOAD_ADDRESS@@ - @@DEVICETREE_ADDRESS@@
+                exit;
+        fi
+done
diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr/pxeboot.pxe b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr/pxeboot.pxe
new file mode 100644
index 00000000..40796545
--- /dev/null
+++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-scr/pxeboot.pxe
@@ -0,0 +1,4 @@
+LABEL Linux
+KERNEL @@KERNEL_IMAGETYPE@@
+FDT @@DEVICE_TREE_NAME@@
+INITRD @@RAMDISK_IMAGE@@
diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-uenv.bb b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-uenv.bb
new file mode 100644
index 00000000..52ae09f0
--- /dev/null
+++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-zynq-uenv.bb
@@ -0,0 +1,109 @@
+SUMMARY = "U-Boot uEnv.txt SD boot environment generation for Zynq targets"
+LICENSE = "MIT"
+LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/MIT;md5=0835ade698e0bcf8506ecda2f7b4f302"
+
+INHIBIT_DEFAULT_DEPS = "1"
+
+BOARDVARIANT_ARCH ??= "${MACHINE_ARCH}"
+PACKAGE_ARCH = "${BOARDVARIANT_ARCH}"
+
+python () {
+    # The device trees must be populated in the deploy directory to correctly
+    # detect them and their names. This means that this recipe needs to depend
+    # on those deployables just like the image recipe does.
+    deploydeps = ["virtual/kernel"]
+    for i in (d.getVar("EXTRA_IMAGEDEPENDS") or "").split():
+        if i != d.getVar("BPN"):
+            deploydeps.append(i)
+
+    # add as DEPENDS since the targets might not have do_deploy tasks
+    if len(deploydeps) != 0:
+        d.appendVar("DEPENDS", " " + " ".join(deploydeps))
+}
+
+COMPATIBLE_MACHINE = "^$"
+COMPATIBLE_MACHINE:zynq = ".*"
+COMPATIBLE_MACHINE:zynqmp = ".*"
+
+inherit deploy image-wic-utils
+
+def uboot_boot_cmd(d):
+    if d.getVar("KERNEL_IMAGETYPE") in ["uImage", "fitImage"]:
+        return "bootm"
+    if d.getVar("KERNEL_IMAGETYPE") in ["zImage"]:
+        return "bootz"
+    if d.getVar("KERNEL_IMAGETYPE") in ["Image"]:
+        return "booti"
+    raise bb.parse.SkipRecipe("Unsupport kernel image type")
+
+def get_sdbootdev(d):
+    if d.getVar("SOC_FAMILY") in ["zynqmp"]:
+        return "${sdbootdev}"
+    else:
+        return "0"
+
+def uenv_populate(d):
+    # populate the environment values
+    env = {}
+
+    env["machine_name"] = d.getVar("MACHINE")
+
+    env["kernel_image"] = d.getVar("KERNEL_IMAGETYPE")
+    env["kernel_load_address"] = d.getVar("KERNEL_LOAD_ADDRESS")
+
+    env["devicetree_image"] = boot_files_dtb_filepath(d)
+    env["devicetree_load_address"] = d.getVar("DEVICETREE_LOAD_ADDRESS")
+
+    env["bootargs"] = d.getVar("KERNEL_BOOTARGS")
+
+    env["loadkernel"] = "fatload mmc " + get_sdbootdev(d) + " ${kernel_load_address} ${kernel_image}"
+    env["loaddtb"] = "fatload mmc  " + get_sdbootdev(d) + " ${devicetree_load_address} ${devicetree_image}"
+    env["bootkernel"] = "run loadkernel && run loaddtb && " + uboot_boot_cmd(d) + " ${kernel_load_address} - ${devicetree_load_address}"
+
+    if d.getVar("SOC_FAMILY") in ["zynqmp"]:
+        env["bootkernel"] = "setenv bootargs " +  d.getVar("KERNEL_BOOTARGS") + " ; " + env["bootkernel"]
+
+    # default uenvcmd does not load bitstream
+    env["uenvcmd"] = "run bootkernel"
+
+    bitstream, bitstreamtype = boot_files_bitstream(d)
+    if bitstream:
+        env["bitstream_image"] = bitstream
+        env["bitstream_load_address"] = "0x100000"
+
+        # if bitstream is "bit" format use loadb, otherwise use load
+        env["bitstream_type"] = "loadb" if bitstreamtype else "load"
+
+        # load bitstream first with loadfpa
+        env["loadfpga"] = "fatload mmc " + get_sdbootdev(d) + " ${bitstream_load_address} ${bitstream_image} && fpga ${bitstream_type} 0 ${bitstream_load_address} ${filesize}"
+        env["uenvcmd"] = "run loadfpga && run bootkernel"
+
+    return env
+
+# bootargs, default to booting with the rootfs device being partition 2
+KERNEL_BOOTARGS:zynq = "earlyprintk console=ttyPS0,115200 root=/dev/mmcblk0p2 rw rootwait"
+KERNEL_BOOTARGS:zynqmp = "earlycon clk_ignore_unused root=/dev/mmcblk${sdbootdev}p2 rw rootwait"
+
+KERNEL_LOAD_ADDRESS:zynq = "0x2080000"
+KERNEL_LOAD_ADDRESS:zynqmp = "0x200000"
+DEVICETREE_LOAD_ADDRESS:zynq = "0x2000000"
+DEVICETREE_LOAD_ADDRESS:zynqmp = "0x4000000"
+
+python do_compile() {
+    env = uenv_populate(d)
+    with open(d.expand("${WORKDIR}/uEnv.txt"), "w") as f:
+        for k, v in env.items():
+            f.write("{0}={1}\n".format(k, v))
+}
+
+FILES:${PN} += "/boot/uEnv.txt"
+
+do_install() {
+        install -Dm 0644 ${WORKDIR}/uEnv.txt ${D}/boot/uEnv.txt
+}
+
+do_deploy() {
+        install -Dm 0644 ${WORKDIR}/uEnv.txt ${DEPLOYDIR}/uEnv.txt
+}
+addtask do_deploy after do_compile before do_build
+
diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot_%.bbappend b/meta-xilinx-core/recipes-bsp/u-boot/u-boot_%.bbappend
new file mode 100644
index 00000000..b8522369
--- /dev/null
+++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot_%.bbappend
@@ -0,0 +1,11 @@
+include u-boot-spl-zynq-init.inc
+
+# u-boot 2016.11 has support for these
+HAS_PLATFORM_INIT ??= " \
+                zynq_microzed_config \
+                zynq_zed_config \
+                zynq_zc702_config \
+                zynq_zc706_config \
+                zynq_zybo_config \
+                "
+
diff --git a/meta-xilinx-core/recipes-core/glibc/glibc-locale_%.bbappend b/meta-xilinx-core/recipes-core/glibc/glibc-locale_%.bbappend
new file mode 100644
index 00000000..1702b75d
--- /dev/null
+++ b/meta-xilinx-core/recipes-core/glibc/glibc-locale_%.bbappend
@@ -0,0 +1,4 @@
+do_install:append() {
+    # Remove the libdir if it is empty when gconv is not copied
+    find ${D}${libdir} -type d -empty -delete
+}
diff --git a/meta-xilinx-core/recipes-devtools/python/python3-anytree_2.8.0.bb b/meta-xilinx-core/recipes-devtools/python/python3-anytree_2.8.0.bb
new file mode 100644
index 00000000..f5070be7
--- /dev/null
+++ b/meta-xilinx-core/recipes-devtools/python/python3-anytree_2.8.0.bb
@@ -0,0 +1,22 @@
+SUMMARY = "Powerful and Lightweight Python Tree Data Structure"
+
+HOMEPAGE = "https://github.com/c0fec0de/anytree"
+LICENSE = "Apache-2.0"
+
+LIC_FILES_CHKSUM = "file://LICENSE;md5=e3fc50a88d0a364313df4b21ef20c29e"
+
+DEPENDS += "python3-six"
+
+SRC_URI = "git://github.com/c0fec0de/anytree.git;protocol=https"
+SRCREV = "75c0198636f8997967ba00df5077cd21350f68ce"
+
+S = "${WORKDIR}/git"
+
+inherit setuptools3
+
+do_install:append() {
+        rm -f ${D}/${datadir}/LICENSE
+        rmdir ${D}/${datadir} || :
+}
+
+BBCLASSEXTEND = "native nativesdk"
diff --git a/meta-xilinx-core/recipes-devtools/python/python3-flask-restful_%.bbappend b/meta-xilinx-core/recipes-devtools/python/python3-flask-restful_%.bbappend
new file mode 100644
index 00000000..608377e3
--- /dev/null
+++ b/meta-xilinx-core/recipes-devtools/python/python3-flask-restful_%.bbappend
@@ -0,0 +1 @@
+BBCLASSEXTEND = "native nativesdk"
diff --git a/meta-xilinx-core/recipes-devtools/python/python3-flask_%.bbappend b/meta-xilinx-core/recipes-devtools/python/python3-flask_%.bbappend
new file mode 100644
index 00000000..608377e3
--- /dev/null
+++ b/meta-xilinx-core/recipes-devtools/python/python3-flask_%.bbappend
@@ -0,0 +1 @@
+BBCLASSEXTEND = "native nativesdk"
diff --git a/meta-xilinx-core/recipes-devtools/python/python3-itsdangerous_%.bbappend b/meta-xilinx-core/recipes-devtools/python/python3-itsdangerous_%.bbappend
new file mode 100644
index 00000000..608377e3
--- /dev/null
+++ b/meta-xilinx-core/recipes-devtools/python/python3-itsdangerous_%.bbappend
@@ -0,0 +1 @@
+BBCLASSEXTEND = "native nativesdk"
diff --git a/meta-xilinx-core/recipes-devtools/python/python3-pandas_%.bbappend b/meta-xilinx-core/recipes-devtools/python/python3-pandas_%.bbappend
new file mode 100644
index 00000000..608377e3
--- /dev/null
+++ b/meta-xilinx-core/recipes-devtools/python/python3-pandas_%.bbappend
@@ -0,0 +1 @@
+BBCLASSEXTEND = "native nativesdk"
diff --git a/meta-xilinx-core/recipes-devtools/python/python3-werkzeug_%.bbappend b/meta-xilinx-core/recipes-devtools/python/python3-werkzeug_%.bbappend
new file mode 100644
index 00000000..608377e3
--- /dev/null
+++ b/meta-xilinx-core/recipes-devtools/python/python3-werkzeug_%.bbappend
@@ -0,0 +1 @@
+BBCLASSEXTEND = "native nativesdk"
diff --git a/meta-xilinx-core/recipes-devtools/qemu/files/0001-Add-enable-disable-udev.patch b/meta-xilinx-core/recipes-devtools/qemu/files/0001-Add-enable-disable-udev.patch
new file mode 100644
index 00000000..32c33385
--- /dev/null
+++ b/meta-xilinx-core/recipes-devtools/qemu/files/0001-Add-enable-disable-udev.patch
@@ -0,0 +1,30 @@
+From 4ebe009d505bf10b0d90bad081d3fe5bd1cf7441 Mon Sep 17 00:00:00 2001
+From: Sai Hari Chandana Kalluri <chandana.kalluri@xilinx.com>
+Date: Thu, 6 May 2021 14:33:42 -0700
+Subject: [PATCH] Add enable/disable libudev
+
+Upstream-Status: Pending
+Signed-off-by: Jeremy Puhlman <jpuhlman@mvista.com>
+Signed-off-by: Sai Hari Chandana Kalluri <chandana.kalluri@xilinx.com>
+---
+ configure | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/configure b/configure
+index c2ef164..612f987 100755
+--- a/configure
++++ b/configure
+@@ -1633,6 +1633,10 @@ for opt do
+   ;;
+   --gdb=*) gdb_bin="$optarg"
+   ;;
++  --enable-libudev) libudev="yes"
++  ;;
++  --disable-libudev) libudev="no"
++  ;;
+   --enable-rng-none) rng_none=yes
+   ;;
+   --disable-rng-none) rng_none=no
+-- 
+2.7.4
+
diff --git a/meta-xilinx-core/recipes-devtools/qemu/files/0010-configure-Add-pkg-config-handling-for-libgcrypt.patch b/meta-xilinx-core/recipes-devtools/qemu/files/0010-configure-Add-pkg-config-handling-for-libgcrypt.patch
new file mode 100644
index 00000000..a8ab7daa
--- /dev/null
+++ b/meta-xilinx-core/recipes-devtools/qemu/files/0010-configure-Add-pkg-config-handling-for-libgcrypt.patch
@@ -0,0 +1,93 @@
+From 5214dd4461f2090ef0965b4d2518f49927d61cbc Mon Sep 17 00:00:00 2001
+From: He Zhe <zhe.he@windriver.com>
+Date: Wed, 28 Aug 2019 19:56:28 +0800
+Subject: [Qemu-devel] [PATCH] configure: Add pkg-config handling for libgcrypt
+
+libgcrypt may also be controlled by pkg-config, this patch adds pkg-config
+handling for libgcrypt.
+
+Upstream-Status: Denied [https://lists.nongnu.org/archive/html/qemu-devel/2019-08/msg06333.html]
+
+Signed-off-by: He Zhe <zhe.he@windriver.com>
+---
+ configure | 48 ++++++++++++++++++++++++++++++++++++++++--------
+ 1 file changed, 40 insertions(+), 8 deletions(-)
+
+diff --git a/configure b/configure
+index e44e454..0f362a7 100755
+--- a/configure
++++ b/configure
+@@ -2875,6 +2875,30 @@ has_libgcrypt() {
+     return 0
+ }
+ 
++has_libgcrypt_pkgconfig() {
++    if ! has $pkg_config ; then
++        return 1
++    fi
++
++    if ! $pkg_config --list-all | grep libgcrypt > /dev/null 2>&1 ; then
++        return 1
++    fi
++
++    if test -n "$cross_prefix" ; then
++        host=$($pkg_config --variable=host libgcrypt)
++        if test "${host%-gnu}-" != "${cross_prefix%-gnu}" ; then
++            print_error "host($host) does not match cross_prefix($cross_prefix)"
++            return 1
++        fi
++    fi
++
++    if ! $pkg_config --atleast-version=1.5.0 libgcrypt ; then
++        print_error "libgcrypt version is $($pkg_config --modversion libgcrypt)"
++        return 1
++    fi
++
++    return 0
++}
+ 
+ if test "$nettle" != "no"; then
+     pass="no"
+@@ -2902,7 +2926,14 @@ fi
+ 
+ if test "$gcrypt" != "no"; then
+     pass="no"
+-    if has_libgcrypt; then
++    if has_libgcrypt_pkgconfig; then
++        gcrypt_cflags=$($pkg_config --cflags libgcrypt)
++        if test "$static" = "yes" ; then
++            gcrypt_libs=$($pkg_config --libs --static libgcrypt)
++        else
++            gcrypt_libs=$($pkg_config --libs libgcrypt)
++        fi
++    elif has_libgcrypt; then
+         gcrypt_cflags=$(libgcrypt-config --cflags)
+         gcrypt_libs=$(libgcrypt-config --libs)
+         # Debian has removed -lgpg-error from libgcrypt-config
+@@ -2912,15 +2943,16 @@ if test "$gcrypt" != "no"; then
+         then
+             gcrypt_libs="$gcrypt_libs -lgpg-error"
+         fi
++    fi
+ 
+-        # Link test to make sure the given libraries work (e.g for static).
+-        write_c_skeleton
+-        if compile_prog "" "$gcrypt_libs" ; then
+-            LIBS="$gcrypt_libs $LIBS"
+-            QEMU_CFLAGS="$QEMU_CFLAGS $gcrypt_cflags"
+-            pass="yes"
+-        fi
++    # Link test to make sure the given libraries work (e.g for static).
++    write_c_skeleton
++    if compile_prog "" "$gcrypt_libs" ; then
++           LIBS="$gcrypt_libs $LIBS"
++           QEMU_CFLAGS="$QEMU_CFLAGS $gcrypt_cflags"
++           pass="yes"
+     fi
++
+     if test "$pass" = "yes"; then
+         gcrypt="yes"
+         cat > $TMPC << EOF
+-- 
+2.7.4
+
diff --git a/meta-xilinx-core/recipes-devtools/qemu/files/flash_stripe.c b/meta-xilinx-core/recipes-devtools/qemu/files/flash_stripe.c
new file mode 100644
index 00000000..a9a6e76a
--- /dev/null
+++ b/meta-xilinx-core/recipes-devtools/qemu/files/flash_stripe.c
@@ -0,0 +1,176 @@
+/*
+ * Stripe a flash image across multiple files.
+ *
+ * Copyright (C) 2019 Xilinx, Inc.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <fcntl.h>
+#include <string.h>
+
+/* N way (num) in place bit striper. Lay out row wise bits column wise
+ * (from element 0 to N-1). num is the length of x, and dir reverses the
+ * direction of the transform. be determines the bit endianess scheme.
+ * false to lay out bits LSB to MSB (little endian) and true for big endian.
+ *
+ * Best illustrated by examples:
+ * Each digit in the below array is a single bit (num == 3, be == false):
+ *
+ * {{ 76543210, }  ----- stripe (dir == false) -----> {{ FCheb630, }
+ *  { hgfedcba, }                                      { GDAfc741, }
+ *  { HGFEDCBA, }} <---- upstripe (dir == true) -----  { HEBgda52, }}
+ *
+ * Same but with be == true:
+ *
+ * {{ 76543210, }  ----- stripe (dir == false) -----> {{ 741gdaFC, }
+ *  { hgfedcba, }                                      { 630fcHEB, }
+ *  { HGFEDCBA, }} <---- upstripe (dir == true) -----  { 52hebGDA, }}
+ */
+
+static inline void stripe8(uint8_t *x, int num, bool dir, bool be)
+{
+    uint8_t r[num];
+    memset(r, 0, sizeof(uint8_t) * num);
+    int idx[2] = {0, 0};
+    int bit[2] = {0, be ? 7 : 0};
+    int d = dir;
+
+    for (idx[0] = 0; idx[0] < num; ++idx[0]) {
+        for (bit[0] = be ? 7 : 0; bit[0] != (be ? -1 : 8); bit[0] += be ? -1 : 1) {
+            r[idx[!d]] |= x[idx[d]] & 1 << bit[d] ? 1 << bit[!d] : 0;
+            idx[1] = (idx[1] + 1) % num;
+            if (!idx[1]) {
+                bit[1] += be ? -1 : 1;
+            }
+        }
+    }
+    memcpy(x, r, sizeof(uint8_t) * num);
+}
+
+int main (int argc, char *argv []) {
+#ifdef UNSTRIPE
+    bool unstripe = true;
+#else
+    bool unstripe = false;
+#endif
+
+#ifdef FLASH_STRIPE_BE
+    bool be = true;
+#else
+    bool be = false;
+#endif
+
+    int i;
+
+    const char *exe_name = argv[0];
+    argc--;
+    argv++;
+
+    if (argc < 2) {
+        fprintf(stderr, "ERROR: %s requires at least two args\n", exe_name);
+        return 1;
+    }
+
+    const char *single_f = argv[0];
+    int single;
+    
+    if (unstripe) {
+        single = creat(single_f, 0644);
+    } else {
+        single = open(single_f, 0);
+    }
+    if (single == -1) {
+        perror(argv[0]);
+        return 1;
+    }
+
+    argv++;
+    argc--;
+    
+    int multiple[argc];
+    
+    for (i = 0; i < argc; ++i) {
+        if (unstripe) {
+            multiple[i] = open(argv[i], 0);
+        } else {
+            multiple[i] = creat(argv[i], 0644);
+        }
+        if (multiple[i] == -1) {
+            perror(argv[i]);
+            return 1;
+        }
+    }
+
+    while (true) {
+        uint8_t buf[argc];
+        for (i = 0; i < argc; ++i) {
+            switch (read(!unstripe ? single : multiple[
+#if defined(FLASH_STRIPE_BW) && defined (FLASH_STRIPE_BE)
+                                                       argc - 1 -
+#endif
+                                                       i], &buf[i], 1)) {
+            case 0:
+                if (i == 0) {
+                    goto done;
+                } else if (!unstripe) {
+                    fprintf(stderr, "WARNING:input file %s is not multiple of "
+                            "%d bytes, padding with garbage byte\n", single_f,
+                            argc);
+                }
+                break;
+            case -1:
+                perror(unstripe ? argv[i] : single_f);
+                return 1;
+            }
+        }
+
+#ifndef FLASH_STRIPE_BW
+        stripe8(buf, argc, unstripe, be);
+#endif
+
+        for (i = 0; i < argc; ++i) {
+            switch (write(unstripe ? single : multiple[
+#if defined(FLASH_STRIPE_BW) && defined (FLASH_STRIPE_BE)
+                                                       argc - 1 -
+#endif
+                                                       i], &buf[i], 1)) {
+            case -1:
+                perror(unstripe ? single_f : argv[i]);
+                return 1;
+            case 0:
+                i--; /* try again */
+            }
+        }
+    }
+
+done:
+    close(single);
+    for (i = 0; i < argc; ++i) {
+        close(multiple[argc]);
+    }
+    return 0;
+}
diff --git a/meta-xilinx-core/recipes-devtools/qemu/files/qemu-system-aarch64-multiarch b/meta-xilinx-core/recipes-devtools/qemu/files/qemu-system-aarch64-multiarch
new file mode 100644
index 00000000..6f7fb522
--- /dev/null
+++ b/meta-xilinx-core/recipes-devtools/qemu/files/qemu-system-aarch64-multiarch
@@ -0,0 +1,68 @@
+#!/usr/bin/env python3
+
+# Xilinx QEMU wrapper to launch both PMU and APU instances (multiarch)
+import os
+import subprocess
+import sys
+import tempfile
+import shutil
+
+binpath = os.path.dirname(os.path.abspath(__file__))
+mach_path = tempfile.mkdtemp()
+
+
+# Separate PMU and APU arguments
+APU_args = sys.argv[1:]
+mbtype=''
+
+if '-pmu-args' in APU_args:
+    MB_args = APU_args[APU_args.index('-pmu-args')+1]
+    APU_args.remove('-pmu-args')
+    APU_args.remove(MB_args)
+    MB_args = MB_args.split()
+    PMU_rom = MB_args[MB_args.index('-kernel')+1]
+    mbtype='PMU'
+elif '-plm-args' in APU_args:
+    MB_args = APU_args[APU_args.index('-plm-args')+1]
+    APU_args.remove('-plm-args')
+    APU_args.remove(MB_args)
+    MB_args = MB_args.split()
+    mbtype='PLM'
+else:
+    error_msg = '\nMultiarch not setup properly.'
+    sys.exit(error_msg)
+
+error_msg = None
+if (mbtype == 'PMU' and os.path.exists(PMU_rom)) or mbtype == 'PLM':
+
+    # We need to switch tcp serial arguments (if they exist, e.g. qemurunner) to get the output correctly
+    tcp_serial_ports = [i for i, s in enumerate(APU_args) if 'tcp:127.0.0.1:' in s]
+
+    #NEED TO FIX for next yocto release (dont need to switch ports anymore, they will be provided correctly upstream
+    # We can only switch these if there are exactly two, otherwise we can't assume what is being executed so we leave it as is
+    if len(tcp_serial_ports) == 2:
+        APU_args[tcp_serial_ports[0]],APU_args[tcp_serial_ports[1]] = APU_args[tcp_serial_ports[1]],APU_args[tcp_serial_ports[0]]
+
+    mb_cmd =  binpath + '/qemu-system-microblazeel ' + ' '.join(MB_args) + ' -machine-path ' + mach_path
+    apu_cmd =  binpath + '/qemu-system-aarch64 ' + ' '.join(APU_args) + ' -machine-path ' + mach_path
+
+    # Debug prints
+    print('\n%s instance cmd: %s\n' % (mbtype, mb_cmd))
+    print('APU instance cmd: %s\n' % apu_cmd)
+
+
+    # Invoke QEMU pmu instance
+    process_pmu = subprocess.Popen(mb_cmd, shell=True, stderr=subprocess.PIPE)
+
+    # Invoke QEMU APU instance
+    process_apu = subprocess.Popen(apu_cmd, shell=True, stderr=subprocess.PIPE)
+    if process_apu.wait():
+        error_msg = '\nQEMU APU instance failed:\n%s' % process_apu.stderr.read().decode()
+
+else:
+    if mbtype == 'PMU':
+        error_msg = '\nError: Missing PMU ROM: %s' % PMU_rom
+        error_msg += '\nSee "meta-xilinx/README.qemu.md" for more information on accquiring the PMU ROM.\n'
+
+shutil.rmtree(mach_path)
+sys.exit(error_msg)
diff --git a/meta-xilinx-core/recipes-devtools/qemu/flashstrip_1.0.bb b/meta-xilinx-core/recipes-devtools/qemu/flashstrip_1.0.bb
new file mode 100644
index 00000000..e1dcc5ae
--- /dev/null
+++ b/meta-xilinx-core/recipes-devtools/qemu/flashstrip_1.0.bb
@@ -0,0 +1,27 @@
+SUMMARY = "Building and installing flash strip utility"
+DESCRIPTION = "Building and installing flash strip utility"
+
+LICENSE = "MIT"
+LIC_FILES_CHKSUM = "file://../flash_stripe.c;beginline=1;endline=23;md5=abb859d98b7c4eede655e1b71824125a"
+
+B = "${WORKDIR}/build"
+
+SRC_URI += "file://flash_stripe.c"
+
+TARGET_CC_ARCH += "${LDFLAGS}"
+
+do_compile() {
+    ${CC} ${WORKDIR}/flash_stripe.c -o flash_strip
+    ${CC} ${WORKDIR}/flash_stripe.c -o flash_unstrip
+    ${CC} ${WORKDIR}/flash_stripe.c -o flash_strip_bw -DFLASH_STRIPE_BW
+    ${CC} ${WORKDIR}/flash_stripe.c -o flash_unstrip_bw -DUNSTRIP -DFLASH_STRIPE_BW
+}
+
+do_install() {
+    install -d ${D}${bindir}
+    install -Dm 0755 ${B}/* ${D}${bindir}/
+}
+
+FILES:${PN} = "${bindir}/*"
+
+BBCLASSEXTEND = "native nativesdk"
diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees.inc b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees.inc
new file mode 100644
index 00000000..6d834297
--- /dev/null
+++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees.inc
@@ -0,0 +1,39 @@
+SUMMARY = "Xilinx's hardware device trees required for QEMU"
+HOMEPAGE = "https://github.com/xilinx/qemu-devicetrees/"
+LICENSE = "BSD"
+DEPENDS += "dtc-native"
+
+inherit deploy
+
+LIC_FILES_CHKSUM = "file://Makefile;beginline=1;endline=27;md5=7348b6cbcae69912cb1dee68d6c68d99"
+
+PV = "xilinx-${XILINX_RELEASE_VERSION}+git${SRCPV}"
+
+FILESEXTRAPATHS:prepend := "${THISDIR}/${PN}:"
+SRC_URI:append = " file://0001-Makefile-Use-python3-instead-of-python.patch"
+
+REPO ?= "git://github.com/Xilinx/qemu-devicetrees.git;protocol=https"
+
+BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}"
+SRC_URI = "${REPO};${BRANCHARG}"
+
+S = "${WORKDIR}/git"
+
+# Don't need to do anything
+do_install() {
+        :
+}
+
+do_deploy() {
+        # single-arch dtbs
+        for DTS_FILE in ${S}/LATEST/SINGLE_ARCH/*.dtb; do
+                install -Dm 0644 $DTS_FILE ${DEPLOYDIR}/qemu-hw-devicetrees/$(basename $DTS_FILE .dtb).dtb
+        done
+
+        # multi-arch dtbs
+        for DTS_FILE in ${S}/LATEST/MULTI_ARCH/*.dtb; do
+                install -Dm 0644 $DTS_FILE ${DEPLOYDIR}/qemu-hw-devicetrees/multiarch/$(basename $DTS_FILE .dtb).dtb
+        done
+}
+
+addtask deploy after do_install
diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees/0001-Makefile-Use-python3-instead-of-python.patch b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees/0001-Makefile-Use-python3-instead-of-python.patch
new file mode 100644
index 00000000..425145d0
--- /dev/null
+++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees/0001-Makefile-Use-python3-instead-of-python.patch
@@ -0,0 +1,37 @@
+From e80324e3497e5768c9fdbde3c0660a03d0dcc3ee Mon Sep 17 00:00:00 2001
+From: Sai Hari Chandana Kalluri <chandana.kalluri@xilinx.com>
+Date: Mon, 8 Feb 2021 16:32:34 -0800
+Subject: [PATCH] Makefile:Use python3 instead of python
+
+Signed-off-by: Sai Hari Chandana Kalluri <chandana.kalluri@xilinx.com>
+---
+ Makefile | 12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+diff --git a/Makefile b/Makefile
+index a110483..fd8868c 100644
+--- a/Makefile
++++ b/Makefile
+@@ -91,13 +91,13 @@ $(LQSPI_XIP_OUTDIR)/%.dts:  %.dts $(DTSI_FILES) $(HEADER_FILES)
+ # TODO: Add support for auto-generated dependency list
+ versal-pmc-npi.dtsi: versal-pmc-npi-nxx.dtsi versal-h10-pmc-npi-nxx.dtsi
+ versal-pmc-npi-nxx.dtsi: Makefile
+-       @python -c 'for a in range(0, 54): print("\tGEN_NMU(" + str(a) + ")")' > $@
+-       @python -c 'for a in range(0, 50): print("\tGEN_NSU(" + str(a) + ")")' >> $@
+-       @python -c 'for a in range(0, 146): print("\tGEN_NPS(" + str(a) + ")")' >> $@
++       @python3 -c 'for a in range(0, 54): print("\tGEN_NMU(" + str(a) + ")")' > $@
++       @python3 -c 'for a in range(0, 50): print("\tGEN_NSU(" + str(a) + ")")' >> $@
++       @python3 -c 'for a in range(0, 146): print("\tGEN_NPS(" + str(a) + ")")' >> $@
+ versal-h10-pmc-npi-nxx.dtsi: Makefile
+-       @python -c 'for a in range(0, 37): print("\tGEN_NMU(" + str(a) + ")")' > $@
+-       @python -c 'for a in range(0, 33): print("\tGEN_NSU(" + str(a) + ")")' >> $@
+-       @python -c 'for a in range(0, 135): print("\tGEN_NPS(" + str(a) + ")")' >> $@
++       @python3 -c 'for a in range(0, 37): print("\tGEN_NMU(" + str(a) + ")")' > $@
++       @python3 -c 'for a in range(0, 33): print("\tGEN_NSU(" + str(a) + ")")' >> $@
++       @python3 -c 'for a in range(0, 135): print("\tGEN_NPS(" + str(a) + ")")' >> $@
+ 
+ clean:
+        $(RM) versal-pmc-npi-nxx.dtsi
+-- 
+2.7.4
+
diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2021.2.bb b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2021.2.bb
new file mode 100644
index 00000000..98785e7e
--- /dev/null
+++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees_2021.2.bb
@@ -0,0 +1,4 @@
+require qemu-devicetrees.inc
+
+BRANCH ?= "xlnx_rel_v2021.2"
+SRCREV ?= "0462d4d4866481c19102e05ebefe9f1691ed7ee8"
diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-helper-native_1.0.bb b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-helper-native_1.0.bb
new file mode 100644
index 00000000..efd23d50
--- /dev/null
+++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-helper-native_1.0.bb
@@ -0,0 +1,24 @@
+
+python () {
+    if d.getVar("PREFERRED_PROVIDER_qemu-helper-native") != d.getVar("PN"):
+        raise bb.parse.SkipRecipe("Set qemu-helper-native provider to use this recipe")
+}
+
+# TODO: improve this, since it is very hacky that this recipe need to build tunctl.
+# include the existing qemu-helper-native
+require recipes-devtools/qemu/qemu-helper-native_1.0.bb
+# get the path to tunctl.c (from oe-core!)
+FILESEXTRAPATHS:prepend := "${COREBASE}/meta/recipes-devtools/qemu/qemu-helper:"
+
+# provide it, to replace the existing
+PROVIDES += "qemu-helper-native"
+
+# replace qemu with qemu-xilinx
+DEPENDS:remove = "qemu-system-native"
+DEPENDS:append = " \
+                qemu-xilinx-system-native \
+                qemu-xilinx-multiarch-helper-native \
+                "
+
+RDEPENDS:${PN}:remove = "qemu-system-native"
+RDEPENDS:${PN}:append = " qemu-xilinx-system-native"
diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-multiarch-helper-native_1.0.bb b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-multiarch-helper-native_1.0.bb
new file mode 100644
index 00000000..1eec0163
--- /dev/null
+++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-multiarch-helper-native_1.0.bb
@@ -0,0 +1,20 @@
+SUMMARY = "Helper scripts for executing a multi-arch instance of Xilinx QEMU"
+LICENSE = "MIT"
+LIC_FILES_CHKSUM = "file://${COMMON_LICENSE_DIR}/MIT;md5=0835ade698e0bcf8506ecda2f7b4f302"
+RDEPENDS:${PN} = "qemu-xilinx-native"
+
+inherit native
+
+FILESEXTRAPATHS:prepend := "${THISDIR}/files:"
+
+SRC_URI = "file://qemu-system-aarch64-multiarch"
+
+do_configure[noexec] = "1"
+do_compile[noexec] = "1"
+
+SYSROOT_DIRS += "${bindir}/qemu-xilinx"
+
+do_install() {
+        install -Dm 0755 ${WORKDIR}/qemu-system-aarch64-multiarch ${D}${bindir}/qemu-system-aarch64-multiarch
+}
+
diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-native.inc b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-native.inc
new file mode 100644
index 00000000..3faabe5b
--- /dev/null
+++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-native.inc
@@ -0,0 +1,11 @@
+require recipes-devtools/qemu/qemu-native.inc
+require qemu-xilinx.inc
+
+DEPENDS = "glib-2.0-native zlib-native"
+
+SRC_URI:remove = "file://0012-fix-libcap-header-issue-on-some-distro.patch"
+SRC_URI:remove = "file://0013-cpus.c-Add-error-messages-when-qemi_cpu_kick_thread-.patch"
+
+do_install:append(){
+       rm -rf ${D}${datadir}/icons
+}
diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-native_2021.2.bb b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-native_2021.2.bb
new file mode 100644
index 00000000..f657186f
--- /dev/null
+++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-native_2021.2.bb
@@ -0,0 +1,6 @@
+require qemu-xilinx-native.inc
+BPN = "qemu-xilinx"
+
+EXTRA_OECONF:append = " --target-list=${@get_qemu_usermode_target_list(d)} --disable-tools --disable-blobs --disable-guest-agent"
+
+PROVIDES = "qemu-native"
diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-system-native_2021.2.bb b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-system-native_2021.2.bb
new file mode 100644
index 00000000..b30777d2
--- /dev/null
+++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-system-native_2021.2.bb
@@ -0,0 +1,17 @@
+require qemu-xilinx-native.inc
+
+EXTRA_OECONF:append = " --target-list=${@get_qemu_system_target_list(d)}"
+
+PACKAGECONFIG ??= "fdt alsa kvm"
+
+PACKAGECONFIG:remove = "${@'kvm' if not os.path.exists('/usr/include/linux/kvm.h') else ''}"
+
+DEPENDS += "pixman-native qemu-xilinx-native"
+
+do_install:append() {
+    # The following is also installed by qemu-native
+    rm -f ${D}${datadir}/qemu/trace-events-all
+    rm -rf ${D}${datadir}/qemu/keymaps
+    rm -rf ${D}${datadir}/icons
+}
+
diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc
new file mode 100644
index 00000000..dcdf520f
--- /dev/null
+++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx.inc
@@ -0,0 +1,50 @@
+SUMMARY = "Xilinx's fork of a fast open source processor emulator"
+HOMEPAGE = "https://github.com/xilinx/qemu/"
+
+# x86_64 is needed to build nativesdks
+QEMU_TARGETS = "aarch64 arm microblaze microblazeel x86_64"
+
+LIC_FILES_CHKSUM = " \
+                file://COPYING;md5=441c28d2cf86e15a37fa47e15a72fbac \
+                file://COPYING.LIB;endline=24;md5=8c5efda6cf1e1b03dcfd0e6c0d271c7f \
+                "
+DEPENDS = "glib-2.0 zlib pixman"
+
+XILINX_QEMU_VERSION ?= "v5.1.0"
+BRANCH ?= "xlnx_rel_v2021.2"
+SRCREV = "303b509ec23138c43be8a3712068347210df67fd"
+
+FILESEXTRAPATHS:prepend := "${THISDIR}/files:"
+
+PV = "${XILINX_QEMU_VERSION}-xilinx-${XILINX_RELEASE_VERSION}+git${SRCPV}"
+REPO ?= "gitsm://github.com/Xilinx/qemu.git;protocol=https"
+
+BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}"
+SRC_URI = "${REPO};${BRANCHARG}"
+
+SRC_URI:append = " file://0010-configure-Add-pkg-config-handling-for-libgcrypt.patch \
+                   file://0001-Add-enable-disable-udev.patch \
+"
+SRC_URI:remove:class-target = " file://cross.patch"
+SRC_URI:remove:class-nativesdk = " file://cross.patch"
+
+S = "${WORKDIR}/git"
+
+# Disable KVM completely
+PACKAGECONFIG:remove = "kvm"
+PACKAGECONFIG:append = " fdt gcrypt"
+
+DISABLE_STATIC:pn-${PN} = ""
+
+PTEST_ENABLED = ""
+
+EXTRA_OECONF:append = " --with-git=/bin/false --disable-git-update"
+EXTRA_OECONF:remove = " --with-suffix=${BPN} --with-git-submodules=ignore --meson=meson"
+
+do_install:append() {
+        # Prevent QA warnings about installed ${localstatedir}/run
+        if [ -d ${D}${localstatedir}/run ]; then rmdir ${D}${localstatedir}/run; fi
+}
+
+FILES:${PN} += "${datadir}/qemu/"
+FILES:${PN}:append:class-nativesdk:mingw32 = " ${SDKPATHNATIVE}"
diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx_2021.2.bb b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx_2021.2.bb
new file mode 100644
index 00000000..5189595a
--- /dev/null
+++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx_2021.2.bb
@@ -0,0 +1,16 @@
+require recipes-devtools/qemu/qemu.inc
+require qemu-xilinx.inc
+
+BBCLASSEXTEND = "nativesdk"
+
+RDEPENDS:${PN}:class-target += "bash"
+
+PROVIDES:class-nativesdk = "nativesdk-qemu"
+RPROVIDES:${PN}:class-nativesdk = "nativesdk-qemu"
+
+EXTRA_OECONF:append:class-target = " --target-list=${@get_qemu_target_list(d)}"
+EXTRA_OECONF:append:class-nativesdk = " --target-list=${@get_qemu_target_list(d)}"
+
+do_install:append:class-nativesdk() {
+    ${@bb.utils.contains('PACKAGECONFIG', 'gtk+', 'make_qemu_wrapper', '', d)}
+}
diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu_%.bbappend b/meta-xilinx-core/recipes-devtools/qemu/qemu_%.bbappend
new file mode 100644
index 00000000..bb792de2
--- /dev/null
+++ b/meta-xilinx-core/recipes-devtools/qemu/qemu_%.bbappend
@@ -0,0 +1,2 @@
+# Has a dependency on libmali
+PACKAGE_ARCH:mali400 = "${SOC_VARIANT_ARCH}"
diff --git a/meta-xilinx-core/recipes-devtools/run-postinsts/run-postinsts_%.bbappend b/meta-xilinx-core/recipes-devtools/run-postinsts/run-postinsts_%.bbappend
new file mode 100644
index 00000000..cb5a912b
--- /dev/null
+++ b/meta-xilinx-core/recipes-devtools/run-postinsts/run-postinsts_%.bbappend
@@ -0,0 +1,7 @@
+# Update-alternatives is not able to find stdout when using JTAG boot mode on
+# our devices, exits ungracefully without performing the required work (symbolic
+# linking), pass kmsg to it as output to achieve proper behavior.
+
+do_install:append(){
+    sed -i "s/sh -c \$i \$append_log/sh -c \$i > \/dev\/kmsg/" ${D}${sbindir}/run-postinsts
+}
diff --git a/meta-xilinx-core/recipes-gnome/gtk+/gtk+3_%.bbappend b/meta-xilinx-core/recipes-gnome/gtk+/gtk+3_%.bbappend
new file mode 100644
index 00000000..bb792de2
--- /dev/null
+++ b/meta-xilinx-core/recipes-gnome/gtk+/gtk+3_%.bbappend
@@ -0,0 +1,2 @@
+# Has a dependency on libmali
+PACKAGE_ARCH:mali400 = "${SOC_VARIANT_ARCH}"
diff --git a/meta-xilinx-core/recipes-graphics/cairo/cairo_%.bbappend b/meta-xilinx-core/recipes-graphics/cairo/cairo_%.bbappend
new file mode 100644
index 00000000..68805315
--- /dev/null
+++ b/meta-xilinx-core/recipes-graphics/cairo/cairo_%.bbappend
@@ -0,0 +1,7 @@
+PACKAGECONFIG:mali400 = "${@bb.utils.contains('DISTRO_FEATURES', 'x11', 'x11 xcb', '', d)} \
+                         egl glesv2"
+
+# OpenGL comes from libmali
+DEPENDS:append:mali400 = " libmali-xlnx"
+
+PACKAGE_ARCH:mali400 = "${SOC_VARIANT_ARCH}"
diff --git a/meta-xilinx-core/recipes-graphics/libepoxy/libepoxy_%.bbappend b/meta-xilinx-core/recipes-graphics/libepoxy/libepoxy_%.bbappend
new file mode 100644
index 00000000..bb792de2
--- /dev/null
+++ b/meta-xilinx-core/recipes-graphics/libepoxy/libepoxy_%.bbappend
@@ -0,0 +1,2 @@
+# Has a dependency on libmali
+PACKAGE_ARCH:mali400 = "${SOC_VARIANT_ARCH}"
diff --git a/meta-xilinx-core/recipes-graphics/libgles/files/egl.pc b/meta-xilinx-core/recipes-graphics/libgles/files/egl.pc
new file mode 100644
index 00000000..65c4c1f3
--- /dev/null
+++ b/meta-xilinx-core/recipes-graphics/libgles/files/egl.pc
@@ -0,0 +1,12 @@
+prefix=/usr
+exec_prefix=${prefix}
+libdir=/usr/lib
+includedir=/usr/include
+
+Name: egl
+Description: MALI EGL library
+Requires.private:
+Version: 17.3
+Libs: -L${libdir} -lEGL
+Libs.private: -lm -lpthread -ldl
+Cflags: -I${includedir}
diff --git a/meta-xilinx-core/recipes-graphics/libgles/files/gbm.pc b/meta-xilinx-core/recipes-graphics/libgles/files/gbm.pc
new file mode 100644
index 00000000..c40b5f4f
--- /dev/null
+++ b/meta-xilinx-core/recipes-graphics/libgles/files/gbm.pc
@@ -0,0 +1,12 @@
+prefix=/usr
+exec_prefix=${prefix}
+libdir=/usr/lib
+includedir=/usr/include
+
+Name: gbm
+Description: MALI gbm library
+Requires.private:
+Version: 17.3
+Libs: -L${libdir} -lgbm
+Libs.private: -lm -lpthread -ldl
+Cflags: -I${includedir}
diff --git a/meta-xilinx-core/recipes-graphics/libgles/files/glesv1.pc b/meta-xilinx-core/recipes-graphics/libgles/files/glesv1.pc
new file mode 100644
index 00000000..39467f33
--- /dev/null
+++ b/meta-xilinx-core/recipes-graphics/libgles/files/glesv1.pc
@@ -0,0 +1,12 @@
+prefix=/usr
+exec_prefix=${prefix}
+libdir=/usr/lib
+includedir=/usr/include
+
+Name: glesv1
+Description: MALI OpenGL ES 1.1 library
+Requires.private:
+Version: 17.3
+Libs: -L${libdir} -lGLESv1_CM
+Libs.private: -lm -lpthread -ldl
+Cflags: -I${includedir}
diff --git a/meta-xilinx-core/recipes-graphics/libgles/files/glesv1_cm.pc b/meta-xilinx-core/recipes-graphics/libgles/files/glesv1_cm.pc
new file mode 100644
index 00000000..1547b4c8
--- /dev/null
+++ b/meta-xilinx-core/recipes-graphics/libgles/files/glesv1_cm.pc
@@ -0,0 +1,12 @@
+prefix=/usr
+exec_prefix=${prefix}
+libdir=/usr/lib
+includedir=/usr/include
+
+Name: gles_cm
+Description: Mali OpenGL ES 1.1 CM library
+Requires.private:
+Version: 17.3
+Libs: -L${libdir} -lGLESv1_CM
+Libs.private: -lm -lpthread -ldl
+Cflags: -I${includedir}
diff --git a/meta-xilinx-core/recipes-graphics/libgles/files/glesv2.pc b/meta-xilinx-core/recipes-graphics/libgles/files/glesv2.pc
new file mode 100644
index 00000000..a0a84f23
--- /dev/null
+++ b/meta-xilinx-core/recipes-graphics/libgles/files/glesv2.pc
@@ -0,0 +1,12 @@
+prefix=/usr
+exec_prefix=${prefix}
+libdir=/usr/lib
+includedir=/usr/include
+
+Name: glesv2
+Description: MALI OpenGL ES 2.0 library
+Requires.private:
+Version: 17.3
+Libs: -L${libdir} -lGLESv2
+Libs.private: -lm -lpthread -ldl
+Cflags: -I${includedir}
diff --git a/meta-xilinx-core/recipes-graphics/libgles/libmali-xlnx.bb b/meta-xilinx-core/recipes-graphics/libgles/libmali-xlnx.bb
new file mode 100644
index 00000000..79e0d90b
--- /dev/null
+++ b/meta-xilinx-core/recipes-graphics/libgles/libmali-xlnx.bb
@@ -0,0 +1,201 @@
+DESCRIPTION = "libGLES for ZynqMP with Mali 400"
+
+LICENSE = "Proprietary"
+LIC_FILES_CHKSUM = "file://EULA;md5=82e466d0ed92c5a15f568dbe6b31089c"
+
+inherit features_check update-alternatives
+
+ANY_OF_DISTRO_FEATURES = "x11 fbdev wayland"
+
+PROVIDES += "virtual/libgles1 virtual/libgles2 virtual/egl virtual/libgbm"
+
+FILESEXTRAPATHS:prepend := "${THISDIR}/files:"
+
+REPO ?= "git://github.com/Xilinx/mali-userspace-binaries.git;protocol=https"
+BRANCH ?= "xlnx_rel_v2021.2"
+SRCREV ?= "a1a22c9f03b20d8cb70b91727fe51c1db7f4b061"
+BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}"
+
+PV = "r9p0-01rel0"
+SRC_URI = " \
+    ${REPO};${BRANCHARG} \
+    file://egl.pc \
+    file://glesv1_cm.pc \
+    file://glesv1.pc \
+    file://glesv2.pc \
+    file://gbm.pc \
+    "
+
+COMPATIBLE_MACHINE = "^$"
+COMPATIBLE_MACHINE:zynqmp-eg = "zynqmp-eg"
+COMPATIBLE_MACHINE:zynqmp-ev = "zynqmp-ev"
+
+PACKAGE_ARCH = "${SOC_VARIANT_ARCH}"
+
+
+S = "${WORKDIR}/git"
+
+# If were switching at runtime, we would need all RDEPENDS needed for all backends available
+X11RDEPENDS = "libxdamage libxext libx11 libdrm libxfixes"
+X11DEPENDS = "libxdamage libxext virtual/libx11 libdrm libxfixes"
+
+# Don't install runtime dependencies for other backends unless the DISTRO supports it
+RDEPENDS:${PN} = " \
+    kernel-module-mali \
+    ${@bb.utils.contains('DISTRO_FEATURES', 'x11', '${X11RDEPENDS}', '', d)} \
+"
+
+# We dont build anything but we want to avoid QA warning build-deps
+DEPENDS = "\
+    ${@bb.utils.contains('DISTRO_FEATURES', 'x11', '${X11DEPENDS}', '', d)} \
+    ${@bb.utils.contains('DISTRO_FEATURES', 'wayland', 'wayland libdrm', '', d)} \
+"
+
+
+# x11 is default, set to "fbdev" , "wayland", or "headless" if required
+MALI_BACKEND_DEFAULT ?= "x11"
+
+USE_X11 = "${@bb.utils.contains("DISTRO_FEATURES", "x11", "yes", "no", d)}"
+USE_FB = "${@bb.utils.contains("DISTRO_FEATURES", "fbdev", "yes", "no", d)}"
+USE_WL = "${@bb.utils.contains("DISTRO_FEATURES", "wayland", "yes", "no", d)}"
+
+MONOLITHIC_LIBMALI = "libMali.so.9.0"
+
+do_install() {
+    #Identify the ARCH type
+    ${TARGET_PREFIX}gcc --version > ARCH_PLATFORM
+    if grep -q aarch64 "ARCH_PLATFORM"; then
+        ARCH_PLATFORM_DIR=aarch64-linux-gnu
+    else
+        ARCH_PLATFORM_DIR=arm-linux-gnueabihf
+    fi
+
+    # install headers
+    install -d -m 0655 ${D}${includedir}/EGL
+    install -m 0644 ${S}/${PV}/glesHeaders/EGL/*.h ${D}${includedir}/EGL/
+    install -d -m 0655 ${D}${includedir}/GLES
+    install -m 0644 ${S}/${PV}/glesHeaders/GLES/*.h ${D}${includedir}/GLES/
+    install -d -m 0655 ${D}${includedir}/GLES2
+    install -m 0644 ${S}/${PV}/glesHeaders/GLES2/*.h ${D}${includedir}/GLES2/
+    install -d -m 0655 ${D}${includedir}/KHR
+    install -m 0644 ${S}/${PV}/glesHeaders/KHR/*.h ${D}${includedir}/KHR/
+
+    install -d ${D}${libdir}/pkgconfig
+    install -m 0644 ${WORKDIR}/egl.pc ${D}${libdir}/pkgconfig/egl.pc
+    install -m 0644 ${WORKDIR}/glesv2.pc ${D}${libdir}/pkgconfig/glesv2.pc
+    install -m 0644 ${WORKDIR}/glesv1.pc ${D}${libdir}/pkgconfig/glesv1.pc
+    install -m 0644 ${WORKDIR}/glesv1_cm.pc ${D}${libdir}/pkgconfig/glesv1_cm.pc
+
+    install -d ${D}${libdir}
+    install -d ${D}${includedir}
+
+    cp -a --no-preserve=ownership ${S}/${PV}/${ARCH_PLATFORM_DIR}/common/*.so* ${D}${libdir}
+
+    install -Dm 0644 ${S}/${PV}/${ARCH_PLATFORM_DIR}/headless/${MONOLITHIC_LIBMALI} ${D}${libdir}/headless/${MONOLITHIC_LIBMALI}
+    ln -snf headless/${MONOLITHIC_LIBMALI} ${D}${libdir}/${MONOLITHIC_LIBMALI}
+
+    if [ "${USE_FB}" = "yes" ]; then
+        install -Dm 0644 ${S}/${PV}/${ARCH_PLATFORM_DIR}/fbdev/${MONOLITHIC_LIBMALI} ${D}${libdir}/fbdev/${MONOLITHIC_LIBMALI}
+        if [ "${MALI_BACKEND_DEFAULT}" = "fbdev" ]; then
+            ln -snf fbdev/${MONOLITHIC_LIBMALI} ${D}${libdir}/${MONOLITHIC_LIBMALI}
+        fi
+    fi
+    if [ "${USE_X11}" = "yes" ]; then
+        install -Dm 0644 ${S}/${PV}/${ARCH_PLATFORM_DIR}/x11/${MONOLITHIC_LIBMALI} ${D}${libdir}/x11/${MONOLITHIC_LIBMALI}
+        if [ "${MALI_BACKEND_DEFAULT}" = "x11" ]; then
+            ln -snf x11/${MONOLITHIC_LIBMALI} ${D}${libdir}/${MONOLITHIC_LIBMALI}
+        fi
+    else
+        # We cant rely on the fact that all apps will use pkgconfig correctly
+        sed -i -e 's/^#if defined(MESA_EGL_NO_X11_HEADERS)$/#if (1)/' ${D}${includedir}/EGL/eglplatform.h
+    fi
+    if [ "${USE_WL}" = "yes" ]; then
+        install -m 0644 ${S}/${PV}/glesHeaders/GBM/gbm.h ${D}${includedir}/
+        install -m 0644 ${WORKDIR}/gbm.pc ${D}${libdir}/pkgconfig/gbm.pc
+        install -Dm 0644 ${S}/${PV}/${ARCH_PLATFORM_DIR}/wayland/${MONOLITHIC_LIBMALI} ${D}${libdir}/wayland/${MONOLITHIC_LIBMALI}
+        if [ "${MALI_BACKEND_DEFAULT}" = "wayland" ]; then
+            ln -snf wayland/${MONOLITHIC_LIBMALI} ${D}${libdir}/${MONOLITHIC_LIBMALI}
+        fi
+    fi
+}
+
+
+# We need separate packages to provide multiple alternatives, at this point we install
+# everything on the default one but that can be split if necessary
+PACKAGES += "${PN}-x11 ${PN}-fbdev ${PN}-wayland ${PN}-headless"
+
+# This is default/common for all alternatives
+ALTERNATIVE_LINK_NAME[libmali-xlnx] = "${libdir}/${MONOLITHIC_LIBMALI}"
+
+
+# Declare alternatives and corresponding library location
+ALTERNATIVE:${PN}-x11 = "libmali-xlnx"
+ALTERNATIVE_TARGET_libmali-xlnx-x11[libmali-xlnx] = "${libdir}/x11/${MONOLITHIC_LIBMALI}"
+
+ALTERNATIVE:${PN}-fbdev = "libmali-xlnx"
+ALTERNATIVE_TARGET_libmali-xlnx-fbdev[libmali-xlnx] = "${libdir}/fbdev/${MONOLITHIC_LIBMALI}"
+
+ALTERNATIVE:${PN}-wayland = "libmali-xlnx"
+ALTERNATIVE_TARGET_libmali-xlnx-wayland[libmali-xlnx] = "${libdir}/wayland/${MONOLITHIC_LIBMALI}"
+
+ALTERNATIVE:${PN}-headless = "libmali-xlnx"
+ALTERNATIVE_TARGET_libmali-xlnx-headless[libmali-xlnx] = "${libdir}/headless/${MONOLITHIC_LIBMALI}"
+
+# Set priorities according to what we prveiously defined
+ALTERNATIVE_PRIORITY_libmali-xlnx-x11[libmali-xlnx] = "${@bb.utils.contains("MALI_BACKEND_DEFAULT", "x11", "20", "10", d)}"
+ALTERNATIVE_PRIORITY_libmali-xlnx-fbdev[libmali-xlnx] = "${@bb.utils.contains("MALI_BACKEND_DEFAULT", "fbdev", "20", "10", d)}"
+ALTERNATIVE_PRIORITY_libmali-xlnx-wayland[libmali-xlnx] = "${@bb.utils.contains("MALI_BACKEND_DEFAULT", "wayland", "20", "10", d)}"
+
+# If misconfigured, fallback to headless
+ALTERNATIVE_PRIORITY_libmali-xlnx-headless[libmali-xlnx] = "${@bb.utils.contains("MALI_BACKEND_DEFAULT", "headless", "20", "15", d)}"
+
+
+# Package gets renamed on the debian class, but we want to keep -xlnx
+DEBIAN_NOAUTONAME:libmali-xlnx = "1"
+
+# Update alternatives will actually have separate postinst scripts (one for each package)
+# This wont work for us, so we create a common postinst script and we pass that as the general
+# libmali-xlnx postinst script, but we defer execution to run on first boot (pkg_postinst_ontarget).
+# This will avoid ldconfig removing the symbolic links when creating the root filesystem.
+python populate_packages_updatealternatives:append () {
+    # We need to remove the 'fake' libmali-xlnx before creating any links
+    libdir = d.getVar('libdir')
+    common_postinst = "#!/bin/sh\nrm " + libdir + "/${MONOLITHIC_LIBMALI}\n"
+    for pkg in (d.getVar('PACKAGES') or "").split():
+        # Not all packages provide an alternative (e.g. ${PN}-lic)
+        postinst = d.getVar('pkg_postinst:%s' % pkg)
+        if postinst:
+            old_postinst = postinst
+            new_postinst = postinst.replace('#!/bin/sh','')
+            common_postinst += new_postinst
+    d.setVar('pkg_postinst_ontarget:%s' % 'libmali-xlnx', common_postinst)
+}
+
+
+# Inhibit warnings about files being stripped
+INHIBIT_PACKAGE_DEBUG_SPLIT = "1"
+INHIBIT_PACKAGE_STRIP = "1"
+INHIBIT_SYSROOT_STRIP = "1"
+
+RREPLACES:${PN} = "libegl libgles1 libglesv1-cm1 libgles2 libglesv2-2 libgbm"
+RPROVIDES:${PN} = "libegl libgles1 libglesv1-cm1 libgles2 libglesv2-2 libgbm"
+RCONFLICTS:${PN} = "libegl libgles1 libglesv1-cm1 libgles2 libglesv2-2 libgbm"
+
+# These libraries shouldn't get installed in world builds unless something
+# explicitly depends upon them.
+EXCLUDE_FROM_WORLD = "1"
+FILES:${PN} += "${libdir}/*"
+
+do_package:append() {
+
+    shlibswork_dir = d.getVar('SHLIBSWORKDIR')
+    pkg_filename = d.getVar('PN') + ".list"
+    shlibs_file = os.path.join(shlibswork_dir, pkg_filename)
+    lines = ""
+    with open(shlibs_file, "r") as f:
+        lines = f.readlines()
+    with open(shlibs_file, "w") as f:
+        for line in lines:
+            if d.getVar('MALI_BACKEND_DEFAULT') in line.strip("\n"):
+                 f.write(line)
+}
diff --git a/meta-xilinx-core/recipes-graphics/libglu/libglu_%.bbappend b/meta-xilinx-core/recipes-graphics/libglu/libglu_%.bbappend
new file mode 100644
index 00000000..54fb4298
--- /dev/null
+++ b/meta-xilinx-core/recipes-graphics/libglu/libglu_%.bbappend
@@ -0,0 +1,3 @@
+# OpenGL comes from libmali, adjust parameters
+DEPENDS:append:mali400 =  " virtual/libgles2"
+PACKAGE_ARCH:mali400 = "${SOC_VARIANT_ARCH}"
diff --git a/meta-xilinx-core/recipes-graphics/libsdl2/libsdl2_%.bbappend b/meta-xilinx-core/recipes-graphics/libsdl2/libsdl2_%.bbappend
new file mode 100644
index 00000000..c3b20716
--- /dev/null
+++ b/meta-xilinx-core/recipes-graphics/libsdl2/libsdl2_%.bbappend
@@ -0,0 +1,3 @@
+# Has a dependency on libmali
+PACKAGE_ARCH:mali400 = "${SOC_VARIANT_ARCH}"
+
diff --git a/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali.bb b/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali.bb
new file mode 100644
index 00000000..1e584241
--- /dev/null
+++ b/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali.bb
@@ -0,0 +1,55 @@
+SUMMARY = "A Mali 400 Linux Kernel module"
+SECTION = "kernel/modules"
+
+LICENSE = "GPLv2"
+LIC_FILES_CHKSUM = " \
+        file://linux/license/gpl/mali_kernel_license.h;md5=f5af2d61f4c1eb262cb6a557aaa1070a \
+        "
+
+PV = "r9p0-01rel0"
+
+SRC_URI = " \
+        https://developer.arm.com/-/media/Files/downloads/mali-drivers/kernel/mali-utgard-gpu/DX910-SW-99002-${PV}.tgz \
+        file://0001-Change-Makefile-to-be-compatible-with-Yocto.patch \
+        file://0002-staging-mali-r8p0-01rel0-Add-the-ZYNQ-ZYNQMP-platfor.patch \
+        file://0003-staging-mali-r8p0-01rel0-Remove-unused-trace-macros.patch \
+        file://0004-staging-mali-r8p0-01rel0-Don-t-include-mali_read_phy.patch \
+        file://0005-linux-mali_kernel_linux.c-Handle-clock-when-probed-a.patch \
+        file://0006-arm.c-global-variable-dma_ops-is-removed-from-the-ke.patch \
+        file://0010-common-mali_pm.c-Add-PM-runtime-barrier-after-removi.patch \
+        file://0011-linux-mali_kernel_linux.c-Enable-disable-clock-for-r.patch\
+        file://0012-linux-mali_memory_os_alloc-Remove-__GFP_COLD.patch\
+        file://0013-linux-mali_memory_secure-Add-header-file-dma-direct..patch\
+        file://0014-linux-mali_-timer-Get-rid-of-init_timer.patch\
+        file://0015-fix-driver-failed-to-check-map-error.patch \
+        file://0016-mali_memory_secure-Kernel-5.0-onwards-access_ok-API-.patch \
+        file://0017-Support-for-vm_insert_pfn-deprecated-from-kernel-4.2.patch \
+        file://0018-Change-return-type-to-vm_fault_t-for-fault-handler.patch \
+        file://0019-get_monotonic_boottime-ts-deprecated-from-kernel-4.2.patch \
+        file://0020-Fix-ioremap_nocache-deprecation-in-kernel-5.6.patch \
+        file://0021-Use-updated-timekeeping-functions-in-kernel-5.6.patch \
+        file://0022-Set-HAVE_UNLOCKED_IOCTL-default-to-true.patch \
+        file://0023-Use-PTR_ERR_OR_ZERO-instead-of-PTR_RET.patch \
+        "
+SRC_URI[md5sum] = "85ea110dd6675c70b7d01af87ec9633c"
+SRC_URI[sha256sum] = "7a67127341d17640c1fff5dad80258fb2a37c8a2121b81525fe2327e4532ce2b"
+
+inherit module
+
+PARALLEL_MAKE = "-j 1"
+
+S = "${WORKDIR}/DX910-SW-99002-${PV}/driver/src/devicedrv/mali"
+
+COMPATIBLE_MACHINE = "^$"
+COMPATIBLE_MACHINE:zynqmp-eg = "zynqmp-eg"
+COMPATIBLE_MACHINE:zynqmp-ev = "zynqmp-ev"
+
+EXTRA_OEMAKE = 'KDIR="${STAGING_KERNEL_DIR}" \
+                ARCH="${ARCH}" \
+                BUILD=release \
+                MALI_PLATFORM="arm" \
+                USING_DT=1 \
+                MALI_SHARED_INTERRUPTS=1 \
+                CROSS_COMPILE="${TARGET_PREFIX}" \
+                MALI_QUIET=1 \
+                '
diff --git a/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0001-Change-Makefile-to-be-compatible-with-Yocto.patch b/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0001-Change-Makefile-to-be-compatible-with-Yocto.patch
new file mode 100644
index 00000000..3c82f602
--- /dev/null
+++ b/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0001-Change-Makefile-to-be-compatible-with-Yocto.patch
@@ -0,0 +1,47 @@
+From 6d283b9aa3f7fb761da4cb076b47a62275fc4caa Mon Sep 17 00:00:00 2001
+From: Madhurkiran Harikrishnan <madhurki@xilinx.com>
+Date: Tue, 21 Nov 2017 03:57:25 -0800
+Subject: [PATCH 1/9] Change Makefile to be compatible with Yocto
+
+Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
+Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com>
+Signed-off-by: Madhurkiran Harikrishnan <madhurki@xilinx.com>
+Upstream Status: Inappropriate [Xilinx specific]
+---
+ driver/src/devicedrv/mali/Makefile | 11 +++++++++--
+ 1 file changed, 9 insertions(+), 2 deletions(-)
+
+diff --git a/driver/src/devicedrv/mali/Makefile b/driver/src/devicedrv/mali/Makefile
+index 5a259fe..a6dd94c 100644
+--- Makefile
++++ b/Makefile
+@@ -89,7 +89,11 @@ endif
+ # Define host system directory
+ KDIR-$(shell uname -m):=/lib/modules/$(shell uname -r)/build
+ 
+-include $(KDIR)/.config
++ifeq ($(O),)
++       -include $(KDIR)/.config
++else
++       -include $(O)/.config
++endif
+ 
+ ifeq ($(ARCH), arm)
+ # when compiling for ARM we're cross compiling
+@@ -204,9 +208,12 @@ EXTRA_DEFINES += -DMALI_MEM_SWAP_TRACKING=1
+ endif
+ 
+ all: $(UMP_SYMVERS_FILE)
+-       $(MAKE) ARCH=$(ARCH) -C $(KDIR) M=$(CURDIR) modules
++       $(MAKE) ARCH=$(ARCH) -C $(KDIR) M=$(CURDIR) O=$(O) modules
+        @rm $(FILES_PREFIX)__malidrv_build_info.c $(FILES_PREFIX)__malidrv_build_info.o
+ 
++modules_install:
++       $(MAKE) ARCH=$(ARCH) -C $(KDIR) M=$(CURDIR) modules_install
++
+ clean:
+        $(MAKE) ARCH=$(ARCH) -C $(KDIR) M=$(CURDIR) clean
+ 
+-- 
+2.7.4
+
diff --git a/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0002-staging-mali-r8p0-01rel0-Add-the-ZYNQ-ZYNQMP-platfor.patch b/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0002-staging-mali-r8p0-01rel0-Add-the-ZYNQ-ZYNQMP-platfor.patch
new file mode 100644
index 00000000..0a7b6736
--- /dev/null
+++ b/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0002-staging-mali-r8p0-01rel0-Add-the-ZYNQ-ZYNQMP-platfor.patch
@@ -0,0 +1,52 @@
+From f27aab2b0e4d5dea9b5a0e4648c142257940c428 Mon Sep 17 00:00:00 2001
+From: Hyun Kwon <hyun.kwon@xilinx.com>
+Date: Thu, 25 Jun 2015 17:14:42 -0700
+Subject: [PATCH 2/9] staging: mali: r8p0-01rel0: Add the ZYNQ/ZYNQMP platform
+
+Add the number of PP cores that is required for Zynq/ZynqMP configuration.
+
+Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com>
+Signed-off-by: Michal Simek <michal.simek@xilinx.com>
+Upstream Status: Inappropriate [Xilinx specific]
+---
+ driver/src/devicedrv/mali/platform/arm/arm.c | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/driver/src/devicedrv/mali/platform/arm/arm.c b/driver/src/devicedrv/mali/platform/arm/arm.c
+index 4e09aca..fac99bc 100644
+--- platform/arm/arm.c
++++ b/platform/arm/arm.c
+@@ -261,6 +261,10 @@ static struct mali_gpu_device_data mali_gpu_data = {
+        .dedicated_mem_start = 0x80000000, /* Physical start address (use 0xD0000000 for old indirect setup) */
+        .dedicated_mem_size = 0x10000000, /* 256MB */
+ #endif
++#if defined(CONFIG_ARCH_ZYNQ) || defined(CONFIG_ARCH_ZYNQMP)
++       .fb_start = 0x00000000,
++       .fb_size = 0xfffff000,
++#else
+ #if defined(CONFIG_ARM64)
+        /* Some framebuffer drivers get the framebuffer dynamically, such as through GEM,
+        * in which the memory resource can't be predicted in advance.
+@@ -271,6 +275,7 @@ static struct mali_gpu_device_data mali_gpu_data = {
+        .fb_start = 0xe0000000,
+        .fb_size = 0x01000000,
+ #endif
++#endif /* !defined(CONFIG_ARCH_ZYNQ) && !defined(CONFIG_ARCH_ZYNQMP) */
+        .control_interval = 1000, /* 1000ms */
+        .utilization_callback = mali_gpu_utilization_callback,
+        .get_clock_info = NULL,
+@@ -505,6 +510,11 @@ int mali_platform_device_init(struct platform_device *device)
+                        mali_write_phys(0xC0010020, 0xA); /* Enable direct memory mapping for FPGA */
+                }
+        }
++#elif defined(CONFIG_ARCH_ZYNQ) || defined(CONFIG_ARCH_ZYNQMP)
++
++       MALI_DEBUG_PRINT(4, ("Registering Zynq/ZynqMP Mali-400 device\n"));
++       num_pp_cores = 2;
++
+ #endif
+ 
+        /* After kernel 3.15 device tree will default set dev
+-- 
+2.7.4
+
diff --git a/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0003-staging-mali-r8p0-01rel0-Remove-unused-trace-macros.patch b/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0003-staging-mali-r8p0-01rel0-Remove-unused-trace-macros.patch
new file mode 100644
index 00000000..98aa6ac9
--- /dev/null
+++ b/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0003-staging-mali-r8p0-01rel0-Remove-unused-trace-macros.patch
@@ -0,0 +1,35 @@
+From d6e44bbf8d1377f78481f611dec237e8d24baf74 Mon Sep 17 00:00:00 2001
+From: Madhurkiran Harikrishnan <madhurki@xilinx.com>
+Date: Tue, 21 Nov 2017 04:00:27 -0800
+Subject: [PATCH 3/9] staging: mali: r8p0-01rel0: Remove unused trace macros
+
+TRACE_SYSTEM_STRING is not need in each trace file anymore.
+
+Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com>
+Signed-off-by: Madhurkiran Harikrishnan <madhurki@xilinx.com>
+Upstream Status: Pending
+---
+ driver/src/devicedrv/mali/linux/mali_linux_trace.h | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/driver/src/devicedrv/mali/linux/mali_linux_trace.h b/driver/src/devicedrv/mali/linux/mali_linux_trace.h
+index 7f0b19d..33cb1ca 100644
+--- linux/mali_linux_trace.h
++++ b/linux/mali_linux_trace.h
+@@ -13,13 +13,11 @@
+ 
+ #include <linux/types.h>
+ 
+-#include <linux/stringify.h>
+ #include <linux/tracepoint.h>
+ 
+ #undef  TRACE_SYSTEM
+ #define TRACE_SYSTEM mali
+ #ifndef TRACEPOINTS_ENABLED
+-#define TRACE_SYSTEM_STRING __stringfy(TRACE_SYSTEM)
+ #endif
+ #define TRACE_INCLUDE_PATH .
+ #define TRACE_INCLUDE_FILE mali_linux_trace
+-- 
+2.7.4
+
diff --git a/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0004-staging-mali-r8p0-01rel0-Don-t-include-mali_read_phy.patch b/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0004-staging-mali-r8p0-01rel0-Don-t-include-mali_read_phy.patch
new file mode 100644
index 00000000..c5c49679
--- /dev/null
+++ b/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0004-staging-mali-r8p0-01rel0-Don-t-include-mali_read_phy.patch
@@ -0,0 +1,47 @@
+From 2f5e8944357f43fbde4cb642c6ee4a699c88efb5 Mon Sep 17 00:00:00 2001
+From: Hyun Kwon <hyun.kwon@xilinx.com>
+Date: Wed, 29 Jun 2016 09:14:37 -0700
+Subject: [PATCH 4/9] staging: mali: r8p0-01rel0: Don't include
+ mali_read_phys() for zynq/zynqmp
+
+mali_read_phys() is not used with CONFIG_ARCH_ZYNQ and CONFIG_ARCH_ZYNQMP.
+
+Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com>
+Upstream Status: Inappropriate [Xilinx specific]
+---
+ driver/src/devicedrv/mali/platform/arm/arm.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/driver/src/devicedrv/mali/platform/arm/arm.c b/driver/src/devicedrv/mali/platform/arm/arm.c
+index fac99bc..62f9be6 100644
+--- platform/arm/arm.c
++++ b/platform/arm/arm.c
+@@ -38,7 +38,9 @@
+ static int mali_core_scaling_enable = 0;
+ 
+ void mali_gpu_utilization_callback(struct mali_gpu_utilization_data *data);
++#if !(defined(CONFIG_ARCH_ZYNQ) || defined(CONFIG_ARCH_ZYNQMP))
+ static u32 mali_read_phys(u32 phys_addr);
++#endif
+ #if defined(CONFIG_ARCH_REALVIEW)
+ static void mali_write_phys(u32 phys_addr, u32 value);
+ #endif
+@@ -578,6 +580,7 @@ int mali_platform_device_deinit(struct platform_device *device)
+ 
+ #endif /* CONFIG_MALI_DT */
+ 
++#if !(defined(CONFIG_ARCH_ZYNQ) || defined(CONFIG_ARCH_ZYNQMP))
+ static u32 mali_read_phys(u32 phys_addr)
+ {
+        u32 phys_addr_page = phys_addr & 0xFFFFE000;
+@@ -592,6 +595,7 @@ static u32 mali_read_phys(u32 phys_addr)
+ 
+        return ret;
+ }
++#endif
+ 
+ #if defined(CONFIG_ARCH_REALVIEW)
+ static void mali_write_phys(u32 phys_addr, u32 value)
+-- 
+2.7.4
+
diff --git a/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0005-linux-mali_kernel_linux.c-Handle-clock-when-probed-a.patch b/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0005-linux-mali_kernel_linux.c-Handle-clock-when-probed-a.patch
new file mode 100644
index 00000000..3d784604
--- /dev/null
+++ b/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0005-linux-mali_kernel_linux.c-Handle-clock-when-probed-a.patch
@@ -0,0 +1,90 @@
+From e67e20ec6ff0c9720d87844270421453c738066a Mon Sep 17 00:00:00 2001
+From: Madhurkiran Harikrishnan <madhurki@xilinx.com>
+Date: Thu, 16 Feb 2017 12:15:58 -0800
+Subject: [PATCH 5/9] linux/mali_kernel_linux.c: Handle clock when probed and
+ removed
+
+This patch will handle the clock through clock
+specifier for GPU PP0 and PP1.
+
+Signed-off-by: Madhurkiran Harikrishnan <madhurki@xilinx.com>
+Upstream Status: Inappropriate [Xilinx specific]
+---
+ .../src/devicedrv/mali/linux/mali_kernel_linux.c   | 40 +++++++++++++++++++++-
+ 1 file changed, 39 insertions(+), 1 deletion(-)
+
+diff --git a/driver/src/devicedrv/mali/linux/mali_kernel_linux.c b/driver/src/devicedrv/mali/linux/mali_kernel_linux.c
+index d7893a3..f15fb56 100644
+--- linux/mali_kernel_linux.c
++++ b/linux/mali_kernel_linux.c
+@@ -45,6 +45,14 @@
+ #if defined(CONFIG_MALI400_INTERNAL_PROFILING)
+ #include "mali_profiling_internal.h"
+ #endif
++
++#if defined(CONFIG_ARCH_ZYNQMP)
++/* Initialize variables for clocks */
++struct clk *clk_gpu;
++struct clk *clk_gpu_pp0;
++struct clk *clk_gpu_pp1;
++#endif
++
+ #if defined(CONFIG_MALI400_PROFILING) && defined(CONFIG_MALI_DVFS)
+ #include "mali_osk_profiling.h"
+ #include "mali_dvfs_policy.h"
+@@ -580,7 +588,23 @@ static int mali_probe(struct platform_device *pdev)
+        }
+ #endif
+ 
+-
++#if defined(CONFIG_ARCH_ZYNQMP)
++       /* Initialize clocks for GPU and PP */
++       clk_gpu = devm_clk_get(&pdev->dev, "gpu");
++       if (IS_ERR(clk_gpu))
++               return PTR_ERR(clk_gpu);
++       clk_prepare_enable(clk_gpu);
++
++       clk_gpu_pp0 = devm_clk_get(&pdev->dev, "gpu_pp0");
++       if (IS_ERR(clk_gpu_pp0))
++               return PTR_ERR(clk_gpu_pp0);
++       clk_prepare_enable(clk_gpu_pp0);
++
++       clk_gpu_pp1 = devm_clk_get(&pdev->dev, "gpu_pp1");
++       if (IS_ERR(clk_gpu_pp1))
++               return PTR_ERR(clk_gpu_pp1);
++       clk_prepare_enable(clk_gpu_pp1);
++#endif
+        if (_MALI_OSK_ERR_OK == _mali_osk_wq_init()) {
+                /* Initialize the Mali GPU HW specified by pdev */
+                if (_MALI_OSK_ERR_OK == mali_initialize_subsystems()) {
+@@ -608,6 +632,12 @@ static int mali_probe(struct platform_device *pdev)
+                _mali_osk_wq_term();
+        }
+ 
++#if defined(CONFIG_ARCH_ZYNQMP)
++       clk_disable_unprepare(clk_gpu);
++       clk_disable_unprepare(clk_gpu_pp0);
++       clk_disable_unprepare(clk_gpu_pp1);
++#endif
++
+ #ifdef CONFIG_MALI_DEVFREQ
+        mali_devfreq_term(mdev);
+ devfreq_init_failed:
+@@ -673,6 +703,14 @@ static int mali_remove(struct platform_device *pdev)
+        mali_platform_device_deinit(mali_platform_device);
+ #endif
+        mali_platform_device = NULL;
++
++#if defined(CONFIG_ARCH_ZYNQMP)
++       /* Remove clock */
++       clk_disable_unprepare(clk_gpu);
++       clk_disable_unprepare(clk_gpu_pp0);
++       clk_disable_unprepare(clk_gpu_pp1);
++#endif
++
+        return 0;
+ }
+ 
+-- 
+2.7.4
+
diff --git a/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0006-arm.c-global-variable-dma_ops-is-removed-from-the-ke.patch b/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0006-arm.c-global-variable-dma_ops-is-removed-from-the-ke.patch
new file mode 100644
index 00000000..3e1745fd
--- /dev/null
+++ b/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0006-arm.c-global-variable-dma_ops-is-removed-from-the-ke.patch
@@ -0,0 +1,35 @@
+From ed7242238151c12029c566d1974058c579d8ae3d Mon Sep 17 00:00:00 2001
+From: Madhurkiran Harikrishnan <madhurki@xilinx.com>
+Date: Wed, 25 Jan 2017 10:00:33 -0800
+Subject: [PATCH 6/9] arm.c: global variable dma_ops is removed from the kernel
+ 4.7
+
+Refer kernel commit 1dccb598df549d892b6450c261da54cdd7af44b4, the global
+dma_ops variable and the special-casing for ACPI is removed , and just
+returns the dma ops that got set for the device, or the dummy_dma_ops
+if none were present.
+
+Signed-off-by: Madhurkiran Harikrishnan <madhurki@xilinx.com>
+Upstream Status: Pending
+---
+ driver/src/devicedrv/mali/platform/arm/arm.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/driver/src/devicedrv/mali/platform/arm/arm.c b/driver/src/devicedrv/mali/platform/arm/arm.c
+index 62f9be6..57ca989 100644
+--- platform/arm/arm.c
++++ b/platform/arm/arm.c
+@@ -529,8 +529,9 @@ int mali_platform_device_init(struct platform_device *device)
+         */
+        if (!device->dev.dma_mask)
+                device->dev.dma_mask = &device->dev.coherent_dma_mask;
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0))
+        device->dev.archdata.dma_ops = dma_ops;
+-
++#endif
+        err = platform_device_add_data(device, &mali_gpu_data, sizeof(mali_gpu_data));
+ 
+        if (0 == err) {
+-- 
+2.7.4
+
diff --git a/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0010-common-mali_pm.c-Add-PM-runtime-barrier-after-removi.patch b/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0010-common-mali_pm.c-Add-PM-runtime-barrier-after-removi.patch
new file mode 100644
index 00000000..98a86c88
--- /dev/null
+++ b/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0010-common-mali_pm.c-Add-PM-runtime-barrier-after-removi.patch
@@ -0,0 +1,31 @@
+From 58e2c55176f1a146781430b2a570c8ce5f80d426 Mon Sep 17 00:00:00 2001
+From: Madhurkiran Harikrishnan <madhurki@xilinx.com>
+Date: Mon, 28 Aug 2017 09:40:37 -0700
+Subject: [PATCH] common/mali_pm.c: Add PM runtime barrier after removing
+ suspend
+
+Runtime PM suspend "put" results in addition of PM suspend
+API in work queue. This barrier API will remove it from
+the work queue.
+
+Signed-off-by: Madhurkiran Harikrishnan <madhurki@xilinx.com>
+Upstream-Status: Pending
+---
+ driver/src/devicedrv/mali/common/mali_pm.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/driver/src/devicedrv/mali/common/mali_pm.c b/driver/src/devicedrv/mali/common/mali_pm.c
+index 858c689..62a1e5f 100644
+--- common/mali_pm.c
++++ b/common/mali_pm.c
+@@ -301,6 +301,7 @@ void mali_pm_init_end(void)
+        }
+ 
+        _mali_osk_pm_dev_ref_put();
++       _mali_osk_pm_dev_barrier();
+ }
+ 
+ void mali_pm_update_sync(void)
+-- 
+2.7.4
+
diff --git a/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0011-linux-mali_kernel_linux.c-Enable-disable-clock-for-r.patch b/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0011-linux-mali_kernel_linux.c-Enable-disable-clock-for-r.patch
new file mode 100644
index 00000000..38ab4042
--- /dev/null
+++ b/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0011-linux-mali_kernel_linux.c-Enable-disable-clock-for-r.patch
@@ -0,0 +1,153 @@
+From aeff13ad9e9ef73172a9325f669aefd3c0403dbb Mon Sep 17 00:00:00 2001
+From: Madhurkiran Harikrishnan <madhurki@xilinx.com>
+Date: Wed, 21 Feb 2018 16:52:15 -0800
+Subject: [PATCH] linux/mali_kernel_linux.c: Enable/disable clock for runtime
+ resume/suspend
+
+Enable/Disable the clock for GP,PP0 and PP1 during runtime
+resume/suspend.
+
+Signed-off-by: Madhurkiran Harikrishnan <madhurki@xilinx.com>
+Reviewed-by: Hyun Kwon <hyunk@xilinx.com>
+Upstream Status: Inappropriate [Xilinx specific]
+---
+ .../src/devicedrv/mali/linux/mali_kernel_linux.c   | 65 ++++++++++++++++++----
+ 1 file changed, 54 insertions(+), 11 deletions(-)
+
+diff --git a/driver/src/devicedrv/mali/linux/mali_kernel_linux.c b/driver/src/devicedrv/mali/linux/mali_kernel_linux.c
+index f15fb56..e61f33b 100644
+--- linux/mali_kernel_linux.c
++++ b/linux/mali_kernel_linux.c
+@@ -51,6 +51,7 @@
+ struct clk *clk_gpu;
+ struct clk *clk_gpu_pp0;
+ struct clk *clk_gpu_pp1;
++mali_bool clk_enabled;
+ #endif
+ 
+ #if defined(CONFIG_MALI400_PROFILING) && defined(CONFIG_MALI_DVFS)
+@@ -281,6 +282,46 @@ struct file_operations mali_fops = {
+        .mmap = mali_mmap
+ };
+ 
++static int mali_enable_clk(void)
++{
++#if defined(CONFIG_ARCH_ZYNQMP)
++       int err = 0;
++
++       if (clk_enabled)
++               return 0;
++
++       clk_enabled = MALI_TRUE;
++       err = clk_prepare_enable(clk_gpu);
++       if (err) {
++               MALI_PRINT_ERROR(("Could not enable clock for GP\n\r"));
++               return err;
++       }
++       err = clk_prepare_enable(clk_gpu_pp0);
++       if (err) {
++               MALI_PRINT_ERROR(("Could not enable clock for PP0\n\r"));
++               return err;
++       }
++       err = clk_prepare_enable(clk_gpu_pp1);
++       if (err) {
++               MALI_PRINT_ERROR(("Could not enable clock for PP1\n\r"));
++               return err;
++       }
++#endif
++       return 0;
++}
++
++static void mali_disable_clk(void)
++{
++#if defined(CONFIG_ARCH_ZYNQMP)
++       if (clk_enabled) {
++               clk_enabled = MALI_FALSE;
++               clk_disable_unprepare(clk_gpu);
++               clk_disable_unprepare(clk_gpu_pp0);
++               clk_disable_unprepare(clk_gpu_pp1);
++       }
++#endif
++}
++
+ #if MALI_ENABLE_CPU_CYCLES
+ void mali_init_cpu_time_counters(int reset, int enable_divide_by_64)
+ {
+@@ -593,18 +634,19 @@ static int mali_probe(struct platform_device *pdev)
+        clk_gpu = devm_clk_get(&pdev->dev, "gpu");
+        if (IS_ERR(clk_gpu))
+                return PTR_ERR(clk_gpu);
+-       clk_prepare_enable(clk_gpu);
+ 
+        clk_gpu_pp0 = devm_clk_get(&pdev->dev, "gpu_pp0");
+        if (IS_ERR(clk_gpu_pp0))
+                return PTR_ERR(clk_gpu_pp0);
+-       clk_prepare_enable(clk_gpu_pp0);
+ 
+        clk_gpu_pp1 = devm_clk_get(&pdev->dev, "gpu_pp1");
+        if (IS_ERR(clk_gpu_pp1))
+                return PTR_ERR(clk_gpu_pp1);
+-       clk_prepare_enable(clk_gpu_pp1);
+ #endif
++
++       err = mali_enable_clk();
++       if (err)
++               return err;
+        if (_MALI_OSK_ERR_OK == _mali_osk_wq_init()) {
+                /* Initialize the Mali GPU HW specified by pdev */
+                if (_MALI_OSK_ERR_OK == mali_initialize_subsystems()) {
+@@ -632,11 +674,6 @@ static int mali_probe(struct platform_device *pdev)
+                _mali_osk_wq_term();
+        }
+ 
+-#if defined(CONFIG_ARCH_ZYNQMP)
+-       clk_disable_unprepare(clk_gpu);
+-       clk_disable_unprepare(clk_gpu_pp0);
+-       clk_disable_unprepare(clk_gpu_pp1);
+-#endif
+ 
+ #ifdef CONFIG_MALI_DEVFREQ
+        mali_devfreq_term(mdev);
+@@ -644,6 +681,7 @@ devfreq_init_failed:
+        mali_pm_metrics_term(mdev);
+ pm_metrics_init_failed:
+        clk_disable_unprepare(mdev->clock);
++       mali_disable_clk();
+ clock_prepare_failed:
+        clk_put(mdev->clock);
+ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0)) && defined(CONFIG_OF) \
+@@ -706,9 +744,7 @@ static int mali_remove(struct platform_device *pdev)
+ 
+ #if defined(CONFIG_ARCH_ZYNQMP)
+        /* Remove clock */
+-       clk_disable_unprepare(clk_gpu);
+-       clk_disable_unprepare(clk_gpu_pp0);
+-       clk_disable_unprepare(clk_gpu_pp1);
++       mali_disable_clk();
+ #endif
+ 
+        return 0;
+@@ -816,6 +852,8 @@ static int mali_driver_runtime_suspend(struct device *dev)
+                devfreq_suspend_device(mdev->devfreq);
+ #endif
+ 
++       mali_disable_clk();
++
+                return 0;
+        } else {
+                return -EBUSY;
+@@ -824,6 +862,11 @@ static int mali_driver_runtime_suspend(struct device *dev)
+ 
+ static int mali_driver_runtime_resume(struct device *dev)
+ {
++       int err ;
++
++       err = mali_enable_clk();
++       if (err)
++               return err;
+ #ifdef CONFIG_MALI_DEVFREQ
+        struct mali_device *mdev = dev_get_drvdata(dev);
+        if (!mdev)
+-- 
+2.7.4
+
diff --git a/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0012-linux-mali_memory_os_alloc-Remove-__GFP_COLD.patch b/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0012-linux-mali_memory_os_alloc-Remove-__GFP_COLD.patch
new file mode 100644
index 00000000..24f0a22c
--- /dev/null
+++ b/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0012-linux-mali_memory_os_alloc-Remove-__GFP_COLD.patch
@@ -0,0 +1,33 @@
+From 779b1883d56804ecd08fe7f57d6c01e3db4e893b Mon Sep 17 00:00:00 2001
+From: Madhurkiran Harikrishnan <madhurkiran.harikrishnan@xilinx.com>
+Date: Wed, 5 Dec 2018 18:07:29 -0800
+Subject: [PATCH 1/3] linux: mali_memory_os_alloc: Remove __GFP_COLD
+
+The support for Cache hot and cold pages are removed from the kernel.
+For more information refer kernel commit 453f85d43fa9ee243f0fc3ac4e1be45615301e3f
+
+Signed-off-by: Madhurkiran Harikrishnan <madhurkiran.harikrishnan@xilinx.com>
+Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
+Upstream Status: Pending
+---
+ driver/src/devicedrv/mali/linux/mali_memory_os_alloc.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/driver/src/devicedrv/mali/linux/mali_memory_os_alloc.c b/driver/src/devicedrv/mali/linux/mali_memory_os_alloc.c
+index 1602371..830e8c6 100644
+--- linux/mali_memory_os_alloc.c
++++ b/linux/mali_memory_os_alloc.c
+@@ -202,7 +202,9 @@ int mali_mem_os_alloc_pages(mali_mem_os_mem *os_mem, u32 size)
+        /* Allocate new pages, if needed. */
+        for (i = 0; i < remaining; i++) {
+                dma_addr_t dma_addr;
+-#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0)
++               gfp_t flags = __GFP_ZERO | __GFP_RETRY_MAYFAIL | __GFP_NOWARN;
++#elif LINUX_VERSION_CODE == KERNEL_VERSION(4, 14, 0)
+                gfp_t flags = __GFP_ZERO | __GFP_RETRY_MAYFAIL | __GFP_NOWARN | __GFP_COLD;
+ #else
+                gfp_t flags = __GFP_ZERO | __GFP_REPEAT | __GFP_NOWARN | __GFP_COLD;
+-- 
+2.7.4
+
diff --git a/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0013-linux-mali_memory_secure-Add-header-file-dma-direct..patch b/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0013-linux-mali_memory_secure-Add-header-file-dma-direct..patch
new file mode 100644
index 00000000..c28a83f4
--- /dev/null
+++ b/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0013-linux-mali_memory_secure-Add-header-file-dma-direct..patch
@@ -0,0 +1,34 @@
+From d20b6eb3e48e56558488dbdda98875b1aed0c29f Mon Sep 17 00:00:00 2001
+From: Madhurkiran Harikrishnan <madhurkiran.harikrishnan@xilinx.com>
+Date: Wed, 5 Dec 2018 18:13:28 -0800
+Subject: [PATCH 2/3] linux: mali_memory_secure: Add header file dma-direct.h
+
+Add dma-direct.h header, as API dma_to_phys is defined here.
+refer kernel commit ea8c64ace86647260ec4255f483e5844d62af2df
+
+Signed-off-by: Madhurkiran Harikrishnan <madhurkiran.harikrishnan@xilinx.com>
+Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
+Upstream Status: Pending
+---
+ driver/src/devicedrv/mali/linux/mali_memory_secure.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/driver/src/devicedrv/mali/linux/mali_memory_secure.c b/driver/src/devicedrv/mali/linux/mali_memory_secure.c
+index 2836b1b..4f55fa5 100644
+--- linux/mali_memory_secure.c
++++ b/linux/mali_memory_secure.c
+@@ -13,7 +13,11 @@
+ #include "mali_memory_secure.h"
+ #include "mali_osk.h"
+ #include <linux/mutex.h>
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 16, 0)
++#include <linux/dma-direct.h>
++#else
+ #include <linux/dma-mapping.h>
++#endif
+ #include <linux/dma-buf.h>
+ 
+ _mali_osk_errcode_t mali_mem_secure_attach_dma_buf(mali_mem_secure *secure_mem, u32 size, int mem_fd)
+-- 
+2.7.4
+
diff --git a/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0014-linux-mali_-timer-Get-rid-of-init_timer.patch b/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0014-linux-mali_-timer-Get-rid-of-init_timer.patch
new file mode 100644
index 00000000..a7c1d5cc
--- /dev/null
+++ b/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0014-linux-mali_-timer-Get-rid-of-init_timer.patch
@@ -0,0 +1,156 @@
+From b6936450484b5aa9dd2438367a907af020341d1d Mon Sep 17 00:00:00 2001
+From: Madhurkiran Harikrishnan <madhurkiran.harikrishnan@xilinx.com>
+Date: Thu, 6 Dec 2018 13:30:44 -0800
+Subject: [PATCH 3/3] linux: mali_*timer: Get rid of init_timer
+
+kernel 4.19 got rid of ancient init_timer. Hence, replace it with
+timer_setup API. For more information refer kernel commit
+7eeb6b893bd28c68b6d664de1d3120e49b855cdb
+
+Signed-off-by: Madhurkiran Harikrishnan <madhurkiran.harikrishnan@xilinx.com>
+Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
+Upstream Status: Pending
+---
+ driver/src/devicedrv/mali/common/mali_control_timer.c |  6 ++++++
+ driver/src/devicedrv/mali/common/mali_group.c         |  6 ++++++
+ driver/src/devicedrv/mali/common/mali_osk.h           | 15 ++++++++++++++-
+ driver/src/devicedrv/mali/linux/mali_osk_timers.c     | 15 ++++++++++++++-
+ 4 files changed, 40 insertions(+), 2 deletions(-)
+
+diff --git a/driver/src/devicedrv/mali/common/mali_control_timer.c b/driver/src/devicedrv/mali/common/mali_control_timer.c
+index 1296ffe..d24b934 100644
+--- common/mali_control_timer.c
++++ b/common/mali_control_timer.c
+@@ -65,11 +65,17 @@ _mali_osk_errcode_t mali_control_timer_init(void)
+                }
+        }
+ 
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)
++       mali_control_timer = _mali_osk_timer_init(mali_control_timer_callback);
++#else
+        mali_control_timer = _mali_osk_timer_init();
++#endif
+        if (NULL == mali_control_timer) {
+                return _MALI_OSK_ERR_FAULT;
+        }
++#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 14, 0)
+        _mali_osk_timer_setcallback(mali_control_timer, mali_control_timer_callback, NULL);
++#endif
+ 
+        return _MALI_OSK_ERR_OK;
+ }
+diff --git a/driver/src/devicedrv/mali/common/mali_group.c b/driver/src/devicedrv/mali/common/mali_group.c
+index 5c7b3f4..1702e9a 100644
+--- common/mali_group.c
++++ b/common/mali_group.c
+@@ -65,9 +65,15 @@ struct mali_group *mali_group_create(struct mali_l2_cache_core *core,
+ 
+        group = _mali_osk_calloc(1, sizeof(struct mali_group));
+        if (NULL != group) {
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)
++               group->timeout_timer = _mali_osk_timer_init(mali_group_timeout);
++#else
+                group->timeout_timer = _mali_osk_timer_init();
++#endif
+                if (NULL != group->timeout_timer) {
++#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 14, 0)
+                        _mali_osk_timer_setcallback(group->timeout_timer, mali_group_timeout, (void *)group);
++#endif
+ 
+                        group->l2_cache_core[0] = core;
+                        _mali_osk_list_init(&group->group_list);
+diff --git a/driver/src/devicedrv/mali/common/mali_osk.h b/driver/src/devicedrv/mali/common/mali_osk.h
+index a501778..fe93d79 100644
+--- common/mali_osk.h
++++ b/common/mali_osk.h
+@@ -947,7 +947,17 @@ _mali_osk_errcode_t _mali_osk_notification_queue_dequeue(_mali_osk_notification_
+  * asked for.
+  *
+  * @{ */
+-
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)
++/** @brief Initialize a timer
++ *
++ * Allocates resources for a new timer, and initializes them. This does not
++ * start the timer.
++ *
++ * @param callback Function to call when timer expires
++ * @return a pointer to the allocated timer object, or NULL on failure.
++ */
++_mali_osk_timer_t *_mali_osk_timer_init(_mali_osk_timer_callback_t callback);
++#else
+ /** @brief Initialize a timer
+  *
+  * Allocates resources for a new timer, and initializes them. This does not
+@@ -956,6 +966,7 @@ _mali_osk_errcode_t _mali_osk_notification_queue_dequeue(_mali_osk_notification_
+  * @return a pointer to the allocated timer object, or NULL on failure.
+  */
+ _mali_osk_timer_t *_mali_osk_timer_init(void);
++#endif
+ 
+ /** @brief Start a timer
+  *
+@@ -1034,6 +1045,7 @@ void _mali_osk_timer_del_async(_mali_osk_timer_t *tim);
+  */
+ mali_bool _mali_osk_timer_pending(_mali_osk_timer_t *tim);
+ 
++#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 14, 0)
+ /** @brief Set a timer's callback parameters.
+  *
+  * This must be called at least once before a timer is started/modified.
+@@ -1047,6 +1059,7 @@ mali_bool _mali_osk_timer_pending(_mali_osk_timer_t *tim);
+  * @param data Function-specific data to supply to the function on expiry.
+  */
+ void _mali_osk_timer_setcallback(_mali_osk_timer_t *tim, _mali_osk_timer_callback_t callback, void *data);
++#endif
+ 
+ /** @brief Terminate a timer, and deallocate resources.
+  *
+diff --git a/driver/src/devicedrv/mali/linux/mali_osk_timers.c b/driver/src/devicedrv/mali/linux/mali_osk_timers.c
+index e5d7238..f9b5a86 100644
+--- linux/mali_osk_timers.c
++++ b/linux/mali_osk_timers.c
+@@ -21,13 +21,24 @@
+ struct _mali_osk_timer_t_struct {
+        struct timer_list timer;
+ };
+-
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)
++typedef void (*timer_timeout_function_t)(struct timer_list *);
++#else
+ typedef void (*timer_timeout_function_t)(unsigned long);
++#endif
+ 
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)
++_mali_osk_timer_t *_mali_osk_timer_init(_mali_osk_timer_callback_t callback)
++#else
+ _mali_osk_timer_t *_mali_osk_timer_init(void)
++#endif
+ {
+        _mali_osk_timer_t *t = (_mali_osk_timer_t *)kmalloc(sizeof(_mali_osk_timer_t), GFP_KERNEL);
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)
++       if (NULL != t) timer_setup(&t->timer, (timer_timeout_function_t)callback, 0);
++#else
+        if (NULL != t) init_timer(&t->timer);
++#endif
+        return t;
+ }
+ 
+@@ -62,12 +73,14 @@ mali_bool _mali_osk_timer_pending(_mali_osk_timer_t *tim)
+        return 1 == timer_pending(&(tim->timer));
+ }
+ 
++#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 14, 0)
+ void _mali_osk_timer_setcallback(_mali_osk_timer_t *tim, _mali_osk_timer_callback_t callback, void *data)
+ {
+        MALI_DEBUG_ASSERT_POINTER(tim);
+        tim->timer.data = (unsigned long)data;
+        tim->timer.function = (timer_timeout_function_t)callback;
+ }
++#endif
+ 
+ void _mali_osk_timer_term(_mali_osk_timer_t *tim)
+ {
+-- 
+2.7.4
+
diff --git a/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0015-fix-driver-failed-to-check-map-error.patch b/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0015-fix-driver-failed-to-check-map-error.patch
new file mode 100644
index 00000000..5363c37e
--- /dev/null
+++ b/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0015-fix-driver-failed-to-check-map-error.patch
@@ -0,0 +1,17 @@
+Index: mali/linux/mali_memory_os_alloc.c
+===================================================================
+--- mali.orig/linux/mali_memory_os_alloc.c
++++ mali/linux/mali_memory_os_alloc.c
+@@ -239,8 +239,10 @@ int mali_mem_os_alloc_pages(mali_mem_os_
+                /* Ensure page is flushed from CPU caches. */
+                dma_addr = dma_map_page(&mali_platform_device->dev, new_page,
+                                        0, _MALI_OSK_MALI_PAGE_SIZE, DMA_BIDIRECTIONAL);
+-               dma_unmap_page(&mali_platform_device->dev, dma_addr,
+-                              _MALI_OSK_MALI_PAGE_SIZE, DMA_BIDIRECTIONAL);
++               err = dma_mapping_error(&mali_platform_device->dev, dma_addr);
++               if (likely(!err))
++                       dma_unmap_page(&mali_platform_device->dev, dma_addr,
++                                      _MALI_OSK_MALI_PAGE_SIZE, DMA_BIDIRECTIONAL);
+                dma_addr = dma_map_page(&mali_platform_device->dev, new_page,
+                                        0, _MALI_OSK_MALI_PAGE_SIZE, DMA_BIDIRECTIONAL);
+ 
diff --git a/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0016-mali_memory_secure-Kernel-5.0-onwards-access_ok-API-.patch b/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0016-mali_memory_secure-Kernel-5.0-onwards-access_ok-API-.patch
new file mode 100644
index 00000000..dc8bbebf
--- /dev/null
+++ b/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0016-mali_memory_secure-Kernel-5.0-onwards-access_ok-API-.patch
@@ -0,0 +1,47 @@
+From 8cf1dd43f3f25cb4afb84dfc3b0e7c02bc8f7f0c Mon Sep 17 00:00:00 2001
+From: Madhurkiran Harikrishnan <madhurkiran.harikrishnan@xilinx.com>
+Date: Mon, 24 Feb 2020 18:19:37 -0800
+Subject: [LINUX][rel-v2020.1][PATCH v1 1/3] mali_memory_secure: Kernel 5.0
+ onwards 'access_ok' API does not take 'type' as input parameter
+
+'access_ok' no longer needs 'type' as input paramter from kernel 5.0
+onwards.
+
+Signed-off-by: Madhurkiran Harikrishnan <madhurkiran.harikrishnan@xilinx.com>
+---
+ driver/src/devicedrv/mali/linux/mali_ukk_mem.c | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/driver/src/devicedrv/mali/linux/mali_ukk_mem.c b/driver/src/devicedrv/mali/linux/mali_ukk_mem.c
+index 4ec57dc..270bb6d 100644
+--- linux/mali_ukk_mem.c
++++ b/linux/mali_ukk_mem.c
+@@ -207,8 +207,13 @@ int mem_write_safe_wrapper(struct mali_session_data *session_data, _mali_uk_mem_
+        kargs.ctx = (uintptr_t)session_data;
+ 
+        /* Check if we can access the buffers */
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 0, 0)
++       if (!access_ok((const void __user *)kargs.dest, kargs.size)
++           || !access_ok((const void __user *)kargs.src, kargs.size)) {
++#else
+        if (!access_ok(VERIFY_WRITE, kargs.dest, kargs.size)
+            || !access_ok(VERIFY_READ, kargs.src, kargs.size)) {
++#endif
+                return -EINVAL;
+        }
+ 
+@@ -266,7 +271,11 @@ int mem_dump_mmu_page_table_wrapper(struct mali_session_data *session_data, _mal
+                goto err_exit;
+ 
+        user_buffer = (void __user *)(uintptr_t)kargs.buffer;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 0, 0)
++       if (!access_ok(user_buffer, kargs.size))
++#else
+        if (!access_ok(VERIFY_WRITE, user_buffer, kargs.size))
++#endif
+                goto err_exit;
+ 
+        /* allocate temporary buffer (kernel side) to store mmu page table info */
+-- 
+2.7.4
+
diff --git a/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0017-Support-for-vm_insert_pfn-deprecated-from-kernel-4.2.patch b/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0017-Support-for-vm_insert_pfn-deprecated-from-kernel-4.2.patch
new file mode 100644
index 00000000..9c4bbee9
--- /dev/null
+++ b/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0017-Support-for-vm_insert_pfn-deprecated-from-kernel-4.2.patch
@@ -0,0 +1,146 @@
+From 953cab73b8bc487da330aa454abd7f8c7466737e Mon Sep 17 00:00:00 2001
+From: Madhurkiran Harikrishnan <madhurkiran.harikrishnan@xilinx.com>
+Date: Mon, 24 Feb 2020 18:32:16 -0800
+Subject: [LINUX][rel-v2020.1][PATCH v1 2/3] Support for vm_insert_pfn
+ deprecated from kernel 4.20
+
+From kernel 4.20 onwards, support for vm_insert_pfn is deprecated.
+Hence, replace the same with vmf_insert_pfn.
+
+Signed-off-by: Madhurkiran Harikrishnan <madhurkiran.harikrishnan@xilinx.com>
+---
+ .../devicedrv/mali/linux/mali_memory_block_alloc.c   |  6 +++++-
+ driver/src/devicedrv/mali/linux/mali_memory_cow.c    | 14 ++++++++++++--
+ .../src/devicedrv/mali/linux/mali_memory_os_alloc.c  | 20 +++++++++++++++++---
+ driver/src/devicedrv/mali/linux/mali_memory_secure.c |  7 ++++++-
+ 4 files changed, 40 insertions(+), 7 deletions(-)
+
+diff --git a/driver/src/devicedrv/mali/linux/mali_memory_block_alloc.c b/driver/src/devicedrv/mali/linux/mali_memory_block_alloc.c
+index 0c5b6c3..e528699 100644
+--- linux/mali_memory_block_alloc.c
++++ b/linux/mali_memory_block_alloc.c
+@@ -309,9 +309,13 @@ int mali_mem_block_cpu_map(mali_mem_backend *mem_bkend, struct vm_area_struct *v
+ 
+        list_for_each_entry(m_page, &block_mem->pfns, list) {
+                MALI_DEBUG_ASSERT(m_page->type == MALI_PAGE_NODE_BLOCK);
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 20, 0)
++               ret = vmf_insert_pfn(vma, addr, _mali_page_node_get_pfn(m_page));
++               if (unlikely(VM_FAULT_ERROR & ret)) {
++#else
+                ret = vm_insert_pfn(vma, addr, _mali_page_node_get_pfn(m_page));
+-
+                if (unlikely(0 != ret)) {
++#endif
+                        return -EFAULT;
+                }
+                addr += _MALI_OSK_MALI_PAGE_SIZE;
+diff --git a/driver/src/devicedrv/mali/linux/mali_memory_cow.c b/driver/src/devicedrv/mali/linux/mali_memory_cow.c
+index f1d44fe..1dae1d6 100644
+--- linux/mali_memory_cow.c
++++ b/linux/mali_memory_cow.c
+@@ -532,9 +532,14 @@ int mali_mem_cow_cpu_map(mali_mem_backend *mem_bkend, struct vm_area_struct *vma
+                 * flush which makes it way slower than remap_pfn_range or vm_insert_pfn.

+                ret = vm_insert_page(vma, addr, page);

+                */

++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 20, 0)
++               ret = vmf_insert_pfn(vma, addr, _mali_page_node_get_pfn(m_page));

++               if (unlikely(VM_FAULT_ERROR & ret)) {
++#else
+                ret = vm_insert_pfn(vma, addr, _mali_page_node_get_pfn(m_page));

+-

+                if (unlikely(0 != ret)) {

++#endif
++

+                        return ret;

+                }

+                addr += _MALI_OSK_MALI_PAGE_SIZE;

+@@ -569,9 +574,14 @@ _mali_osk_errcode_t mali_mem_cow_cpu_map_pages_locked(mali_mem_backend *mem_bken
+ 

+        list_for_each_entry(m_page, &cow->pages, list) {

+                if ((count >= offset) && (count < offset + num)) {

++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 20, 0)
++                       ret = vmf_insert_pfn(vma, vaddr, _mali_page_node_get_pfn(m_page));

++                       if (unlikely(VM_FAULT_ERROR & ret)) {
++#else
+                        ret = vm_insert_pfn(vma, vaddr, _mali_page_node_get_pfn(m_page));

+-

+                        if (unlikely(0 != ret)) {

++#endif
++

+                                if (count == offset) {

+                                        return _MALI_OSK_ERR_FAULT;

+                                } else {

+diff --git a/driver/src/devicedrv/mali/linux/mali_memory_os_alloc.c b/driver/src/devicedrv/mali/linux/mali_memory_os_alloc.c
+index 3fb6f05..7de3920 100644
+--- linux/mali_memory_os_alloc.c
++++ b/linux/mali_memory_os_alloc.c
+@@ -378,9 +378,14 @@ int mali_mem_os_cpu_map(mali_mem_backend *mem_bkend, struct vm_area_struct *vma)
+                ret = vm_insert_page(vma, addr, page);
+                */
+                page = m_page->page;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 20, 0)
++               ret = vmf_insert_pfn(vma, addr, page_to_pfn(page));
++               if (unlikely(VM_FAULT_ERROR & ret)) {
++#else
+                ret = vm_insert_pfn(vma, addr, page_to_pfn(page));
+-
+                if (unlikely(0 != ret)) {
++#endif
++
+                        return -EFAULT;
+                }
+                addr += _MALI_OSK_MALI_PAGE_SIZE;
+@@ -416,9 +421,13 @@ _mali_osk_errcode_t mali_mem_os_resize_cpu_map_locked(mali_mem_backend *mem_bken
+ 
+                        vm_end -= _MALI_OSK_MALI_PAGE_SIZE;
+                        if (mapping_page_num > 0) {
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 20, 0)
++                               ret = vmf_insert_pfn(vma, vm_end, page_to_pfn(m_page->page));
++                               if (unlikely(VM_FAULT_ERROR & ret)) {
++#else
+                                ret = vm_insert_pfn(vma, vm_end, page_to_pfn(m_page->page));
+-
+                                if (unlikely(0 != ret)) {
++#endif
+                                        /*will return -EBUSY If the page has already been mapped into table, but it's OK*/
+                                        if (-EBUSY == ret) {
+                                                break;
+@@ -439,9 +448,14 @@ _mali_osk_errcode_t mali_mem_os_resize_cpu_map_locked(mali_mem_backend *mem_bken
+                list_for_each_entry(m_page, &os_mem->pages, list) {
+                        if (count >= offset) {
+ 
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 20, 0)
++                               ret = vmf_insert_pfn(vma, vstart, page_to_pfn(m_page->page));
++                               if (unlikely(VM_FAULT_ERROR & ret)) {
++#else
+                                ret = vm_insert_pfn(vma, vstart, page_to_pfn(m_page->page));
+-
+                                if (unlikely(0 != ret)) {
++#endif
++
+                                        /*will return -EBUSY If the page has already been mapped into table, but it's OK*/
+                                        if (-EBUSY == ret) {
+                                                break;
+diff --git a/driver/src/devicedrv/mali/linux/mali_memory_secure.c b/driver/src/devicedrv/mali/linux/mali_memory_secure.c
+index 5546304..cebd1c8 100644
+--- linux/mali_memory_secure.c
++++ b/linux/mali_memory_secure.c
+@@ -132,9 +132,14 @@ int mali_mem_secure_cpu_map(mali_mem_backend *mem_bkend, struct vm_area_struct *
+                MALI_DEBUG_ASSERT(0 == size % _MALI_OSK_MALI_PAGE_SIZE);
+ 
+                for (j = 0; j < size / _MALI_OSK_MALI_PAGE_SIZE; j++) {
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 20, 0)
++                       ret = vmf_insert_pfn(vma, addr, PFN_DOWN(phys));
++                       if (unlikely(VM_FAULT_ERROR & ret)) {
++#else
+                        ret = vm_insert_pfn(vma, addr, PFN_DOWN(phys));
+-
+                        if (unlikely(0 != ret)) {
++#endif
++
+                                return -EFAULT;
+                        }
+                        addr += _MALI_OSK_MALI_PAGE_SIZE;
+-- 
+2.7.4
+
diff --git a/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0018-Change-return-type-to-vm_fault_t-for-fault-handler.patch b/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0018-Change-return-type-to-vm_fault_t-for-fault-handler.patch
new file mode 100644
index 00000000..9797db62
--- /dev/null
+++ b/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0018-Change-return-type-to-vm_fault_t-for-fault-handler.patch
@@ -0,0 +1,32 @@
+From ad5c569f0cc40698699fc2f2c1db3ceb9f8b8f35 Mon Sep 17 00:00:00 2001
+From: Madhurkiran Harikrishnan <madhurkiran.harikrishnan@xilinx.com>
+Date: Tue, 25 Feb 2020 11:36:01 -0800
+Subject: [LINUX][rel-v2020.1][PATCH v1 3/3] Change return type to vm_fault_t
+ for fault handler
+
+From kernel 4.17 onwards the return type of fault handler for
+vm_operations is of type 'vm_fault_t'.
+
+Signed-off-by: Madhurkiran Harikrishnan <madhurkiran.harikrishnan@xilinx.com>
+---
+ driver/src/devicedrv/mali/linux/mali_memory.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/driver/src/devicedrv/mali/linux/mali_memory.c b/driver/src/devicedrv/mali/linux/mali_memory.c
+index c0f0982..2b2b209 100644
+--- linux/mali_memory.c
++++ b/linux/mali_memory.c
+@@ -70,7 +70,9 @@ static void mali_mem_vma_close(struct vm_area_struct *vma)
+        }
+ }
+ 
+-#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 11, 0)
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 17, 0)
++static vm_fault_t  mali_mem_vma_fault(struct vm_fault *vmf)
++#elif LINUX_VERSION_CODE >= KERNEL_VERSION(4, 11, 0)
+ static int mali_mem_vma_fault(struct vm_fault *vmf)
+ #else
+ static int mali_mem_vma_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
+-- 
+2.7.4
+
diff --git a/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0019-get_monotonic_boottime-ts-deprecated-from-kernel-4.2.patch b/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0019-get_monotonic_boottime-ts-deprecated-from-kernel-4.2.patch
new file mode 100644
index 00000000..154bb673
--- /dev/null
+++ b/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0019-get_monotonic_boottime-ts-deprecated-from-kernel-4.2.patch
@@ -0,0 +1,36 @@
+From c6a6b39cea3fdfd91cae7f2a4ef6f36d2c55fdd6 Mon Sep 17 00:00:00 2001
+From: Madhurkiran Harikrishnan <madhurkiran.harikrishnan@xilinx.com>
+Date: Tue, 25 Feb 2020 15:17:17 -0800
+Subject: [LINUX][rel-v2020.1][PATCH v1] "get_monotonic_boottime(&ts)"
+ deprecated from kernel 4.20 onwards
+
+As "get_monotonic_boottime(&ts)" is deprecated, replace the same with
+"ktime_get_boottime_ts64(&ts)". Refer kernel commit ID
+976516404ff3fab2a8caa8bd6f5efc1437fed0b8
+
+Signed-off-by: Madhurkiran Harikrishnan <madhurkiran.harikrishnan@xilinx.com>
+---
+ driver/src/devicedrv/mali/linux/mali_osk_time.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/driver/src/devicedrv/mali/linux/mali_osk_time.c b/driver/src/devicedrv/mali/linux/mali_osk_time.c
+index 03046a5..bfcbf7f 100644
+--- linux/mali_osk_time.c
++++ b/linux/mali_osk_time.c
+@@ -53,7 +53,13 @@ u64 _mali_osk_time_get_ns(void)
+ 
+ u64 _mali_osk_boot_time_get_ns(void)
+ {
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 20, 0)
++       struct timespec64 tsval;
++       ktime_get_boottime_ts64(&tsval);
++       return (u64)timespec64_to_ns(&tsval);
++#else
+        struct timespec tsval;
+        get_monotonic_boottime(&tsval);
+        return (u64)timespec_to_ns(&tsval);
++#endif
+ }
+-- 
+2.7.4
+
diff --git a/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0020-Fix-ioremap_nocache-deprecation-in-kernel-5.6.patch b/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0020-Fix-ioremap_nocache-deprecation-in-kernel-5.6.patch
new file mode 100644
index 00000000..ff86091f
--- /dev/null
+++ b/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0020-Fix-ioremap_nocache-deprecation-in-kernel-5.6.patch
@@ -0,0 +1,92 @@
+From cbc2351e8acf7ed38f6d965e5ea21620e45eda30 Mon Sep 17 00:00:00 2001
+From: Dylan Yip <dylan.yip@xilinx.com>
+Date: Tue, 9 Feb 2021 10:05:41 -0800
+Subject: [PATCH 20/23] Fix ioremap_nocache() deprecation in kernel 5.6
+
+As of commit 4bdc0d676a643140 ("remove ioremap_nocache and
+devm_ioremap_nocache") from kernel 5.6, ioremap_nocache has been
+removed because ioremap is already non-cached by default. So replace all
+calls with ioremap.
+
+Signed-off-by: Dylan Yip <dylan.yip@xilinx.com>
+---
+ linux/mali_memory_cow.c        |  4 ++++
+ linux/mali_osk_low_level_mem.c |  4 ++++
+ platform/arm/arm.c             | 12 ++++++++++++
+ 3 files changed, 20 insertions(+)
+
+diff --git a/linux/mali_memory_cow.c b/linux/mali_memory_cow.c
+index 1dae1d6..6fadd42 100644
+--- a/linux/mali_memory_cow.c
++++ b/linux/mali_memory_cow.c
+@@ -693,7 +693,11 @@ void _mali_mem_cow_copy_page(mali_page_node *src_node, mali_page_node *dst_node)
+                /*

+                * use ioremap to map src for BLOCK memory

+                */

++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 6, 0)

++               src = ioremap(_mali_page_node_get_dma_addr(src_node), _MALI_OSK_MALI_PAGE_SIZE);

++#else

+                src = ioremap_nocache(_mali_page_node_get_dma_addr(src_node), _MALI_OSK_MALI_PAGE_SIZE);

++#endif

+                memcpy(dst, src , _MALI_OSK_MALI_PAGE_SIZE);

+                iounmap(src);

+        }

+diff --git a/linux/mali_osk_low_level_mem.c b/linux/mali_osk_low_level_mem.c
+index 84f93d9..5a0a725 100644
+--- a/linux/mali_osk_low_level_mem.c
++++ b/linux/mali_osk_low_level_mem.c
+@@ -33,7 +33,11 @@ void _mali_osk_write_mem_barrier(void)
+ 
+ mali_io_address _mali_osk_mem_mapioregion(uintptr_t phys, u32 size, const char *description)
+ {
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 6, 0)
++       return (mali_io_address)ioremap(phys, size);
++#else
+        return (mali_io_address)ioremap_nocache(phys, size);
++#endif
+ }
+ 
+ void _mali_osk_mem_unmapioregion(uintptr_t phys, u32 size, mali_io_address virt)
+diff --git a/platform/arm/arm.c b/platform/arm/arm.c
+index b2fb746..e468263 100644
+--- a/platform/arm/arm.c
++++ b/platform/arm/arm.c
+@@ -98,7 +98,11 @@ static int mali_secure_mode_init_juno(void)
+ 
+        MALI_DEBUG_ASSERT(NULL == secure_mode_mapped_addr);
+ 
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 6, 0)
++       secure_mode_mapped_addr = ioremap(phys_addr_page, map_size);
++#else
+        secure_mode_mapped_addr = ioremap_nocache(phys_addr_page, map_size);
++#endif
+        if (NULL != secure_mode_mapped_addr) {
+                return mali_gpu_reset_and_secure_mode_disable_juno();
+        }
+@@ -588,7 +592,11 @@ static u32 mali_read_phys(u32 phys_addr)
+        u32 phys_offset    = phys_addr & 0x00001FFF;
+        u32 map_size       = phys_offset + sizeof(u32);
+        u32 ret = 0xDEADBEEF;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 6, 0)
++       void *mem_mapped = ioremap(phys_addr_page, map_size);
++#else
+        void *mem_mapped = ioremap_nocache(phys_addr_page, map_size);
++#endif
+        if (NULL != mem_mapped) {
+                ret = (u32)ioread32(((u8 *)mem_mapped) + phys_offset);
+                iounmap(mem_mapped);
+@@ -604,7 +612,11 @@ static void mali_write_phys(u32 phys_addr, u32 value)
+        u32 phys_addr_page = phys_addr & 0xFFFFE000;
+        u32 phys_offset    = phys_addr & 0x00001FFF;
+        u32 map_size       = phys_offset + sizeof(u32);
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 6, 0)
++       void *mem_mapped = ioremap(phys_addr_page, map_size);
++#else
+        void *mem_mapped = ioremap_nocache(phys_addr_page, map_size);
++#endif
+        if (NULL != mem_mapped) {
+                iowrite32(value, ((u8 *)mem_mapped) + phys_offset);
+                iounmap(mem_mapped);
+-- 
+2.17.1
+
diff --git a/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0021-Use-updated-timekeeping-functions-in-kernel-5.6.patch b/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0021-Use-updated-timekeeping-functions-in-kernel-5.6.patch
new file mode 100644
index 00000000..adef8e18
--- /dev/null
+++ b/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0021-Use-updated-timekeeping-functions-in-kernel-5.6.patch
@@ -0,0 +1,37 @@
+From bc0f85271681532c7e394229f0155366d1de8779 Mon Sep 17 00:00:00 2001
+From: Dylan Yip <dylan.yip@xilinx.com>
+Date: Mon, 8 Feb 2021 23:47:01 -0800
+Subject: [PATCH 21/23] Use updated timekeeping functions in kernel 5.6
+
+As of commit 412c53a680a9 ("y2038: remove unused time32 interfaces"), 32
+bit timekeeping functions like getnstimeofday() have been removed. So
+use the 64 bit replacements.
+
+Signed-off-by: Dylan Yip <dylan.yip@xilinx.com>
+---
+ linux/mali_osk_time.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/linux/mali_osk_time.c b/linux/mali_osk_time.c
+index bfcbf7f..583d82b 100644
+--- a/linux/mali_osk_time.c
++++ b/linux/mali_osk_time.c
+@@ -46,9 +46,15 @@ void _mali_osk_time_ubusydelay(u32 usecs)
+ 
+ u64 _mali_osk_time_get_ns(void)
+ {
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 6, 0)
++       struct timespec64 tsval;
++       ktime_get_real_ts64(&tsval);
++       return (u64)timespec64_to_ns(&tsval);
++#else
+        struct timespec tsval;
+        getnstimeofday(&tsval);
+        return (u64)timespec_to_ns(&tsval);
++#endif
+ }
+ 
+ u64 _mali_osk_boot_time_get_ns(void)
+-- 
+2.17.1
+
diff --git a/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0022-Set-HAVE_UNLOCKED_IOCTL-default-to-true.patch b/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0022-Set-HAVE_UNLOCKED_IOCTL-default-to-true.patch
new file mode 100644
index 00000000..181df7b7
--- /dev/null
+++ b/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0022-Set-HAVE_UNLOCKED_IOCTL-default-to-true.patch
@@ -0,0 +1,38 @@
+From d17933b6909cc29103befc2ef4e6cf413d9e8fb6 Mon Sep 17 00:00:00 2001
+From: Dylan Yip <dylan.yip@xilinx.com>
+Date: Tue, 9 Feb 2021 08:58:44 -0800
+Subject: [PATCH 22/23] Set HAVE_UNLOCKED_IOCTL default to true
+
+As of commit b19dd42faf41 ("bkl: Remove locked .ioctl file operation")
+of kernel 2.6, the ioctl operation has been replaced with
+unlocked_ioctl. Since this change has been around for almost 10 years,
+go ahead and set the default HAVE_UNLOCKED_IOCTL to be true.
+
+Signed-off-by: Dylan Yip <dylan.yip@xilinx.com>
+---
+ Kbuild | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/Kbuild b/Kbuild
+index 02c3f3d..8c6e6e0 100644
+--- a/Kbuild
++++ b/Kbuild
+@@ -21,6 +21,7 @@ MALI_PP_SCHEDULER_KEEP_SUB_JOB_STARTS_ALIGNED ?= 0
+ MALI_PP_SCHEDULER_FORCE_NO_JOB_OVERLAP_BETWEEN_APPS ?= 0
+ MALI_UPPER_HALF_SCHEDULING ?= 1
+ MALI_ENABLE_CPU_CYCLES ?= 0
++HAVE_UNLOCKED_IOCTL ?= 1
+ 
+ # For customer releases the Linux Device Drivers will be provided as ARM proprietary and GPL releases:
+ # The ARM proprietary product will only include the license/proprietary directory
+@@ -179,6 +180,7 @@ ccflags-y += -DMALI_STATE_TRACKING=1
+ ccflags-y += -DMALI_OS_MEMORY_KERNEL_BUFFER_SIZE_IN_MB=$(OS_MEMORY_KERNEL_BUFFER_SIZE_IN_MB)
+ ccflags-y += -DUSING_GPU_UTILIZATION=$(USING_GPU_UTILIZATION)
+ ccflags-y += -DMALI_ENABLE_CPU_CYCLES=$(MALI_ENABLE_CPU_CYCLES)
++ccflags-y += -DHAVE_UNLOCKED_IOCTL=$(HAVE_UNLOCKED_IOCTL)
+ 
+ ifeq ($(MALI_UPPER_HALF_SCHEDULING),1)
+        ccflags-y += -DMALI_UPPER_HALF_SCHEDULING
+-- 
+2.17.1
+
diff --git a/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0023-Use-PTR_ERR_OR_ZERO-instead-of-PTR_RET.patch b/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0023-Use-PTR_ERR_OR_ZERO-instead-of-PTR_RET.patch
new file mode 100644
index 00000000..bab2bd37
--- /dev/null
+++ b/meta-xilinx-core/recipes-graphics/mali/kernel-module-mali/0023-Use-PTR_ERR_OR_ZERO-instead-of-PTR_RET.patch
@@ -0,0 +1,33 @@
+From e2b52e358e0e030d3881ef80ef09de3662b41210 Mon Sep 17 00:00:00 2001
+From: Dylan Yip <dylan.yip@xilinx.com>
+Date: Tue, 9 Feb 2021 09:48:01 -0800
+Subject: [PATCH 23/23] Use PTR_ERR_OR_ZERO instead of PTR_RET
+
+As of commit fad7c9020948 ("err.h: remove deprecated PTR_RET for good")
+in kernel 5.7, PTR_RET has been removed and replaced with
+PTR_ERR_OR_ZERO. So use this API instead.
+
+Signed-off-by: Dylan Yip <dylan.yip@xilinx.com>
+---
+ linux/mali_memory_dma_buf.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/linux/mali_memory_dma_buf.c b/linux/mali_memory_dma_buf.c
+index 905cd8b..fcdcaac 100644
+--- a/linux/mali_memory_dma_buf.c
++++ b/linux/mali_memory_dma_buf.c
+@@ -281,7 +281,11 @@ int mali_dma_buf_get_size(struct mali_session_data *session, _mali_uk_dma_buf_ge
+        buf = dma_buf_get(fd);
+        if (IS_ERR_OR_NULL(buf)) {
+                MALI_DEBUG_PRINT_ERROR(("Failed to get dma-buf from fd: %d\n", fd));
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 7, 0)
++               return PTR_ERR_OR_ZERO(buf);
++#else
+                return PTR_RET(buf);
++#endif
+        }
+ 
+        if (0 != put_user(buf->size, &user_arg->size)) {
+-- 
+2.17.1
+
diff --git a/meta-xilinx-core/recipes-graphics/mesa/mesa-demos_%.bbappend b/meta-xilinx-core/recipes-graphics/mesa/mesa-demos_%.bbappend
new file mode 100644
index 00000000..ca910830
--- /dev/null
+++ b/meta-xilinx-core/recipes-graphics/mesa/mesa-demos_%.bbappend
@@ -0,0 +1,4 @@
+# OpenGL comes from libmali on ev/eg, when egl is enabled
+DEPENDS:append:mali400 = "${@bb.utils.contains('PACKAGECONFIG', 'egl', ' libmali-xlnx', '', d)}"
+
+PACKAGE_ARCH:mali400 = "${@bb.utils.contains('PACKAGECONFIG', 'egl', '${SOC_VARIANT_ARCH}', '${TUNE_PKGARCH}', d)}"
diff --git a/meta-xilinx-core/recipes-graphics/mesa/mesa-gl_%.bbappend b/meta-xilinx-core/recipes-graphics/mesa/mesa-gl_%.bbappend
new file mode 100644
index 00000000..a5a1eeb2
--- /dev/null
+++ b/meta-xilinx-core/recipes-graphics/mesa/mesa-gl_%.bbappend
@@ -0,0 +1,3 @@
+do_install:append:zynqmp () {
+    rm -rf ${D}${includedir}/KHR/*
+}
diff --git a/meta-xilinx-core/recipes-graphics/virglrenderer/virglrenderer_%.bbappend b/meta-xilinx-core/recipes-graphics/virglrenderer/virglrenderer_%.bbappend
new file mode 100644
index 00000000..c3f773d6
--- /dev/null
+++ b/meta-xilinx-core/recipes-graphics/virglrenderer/virglrenderer_%.bbappend
@@ -0,0 +1,2 @@
+# Has a dependency on libmali
+PACKAGE_ARCH_mali400 = "${SOC_VARIANT_ARCH}"
diff --git a/meta-xilinx-core/recipes-graphics/wayland/files/0001-libweston-Remove-substitute-format-for-ARGB8888.patch b/meta-xilinx-core/recipes-graphics/wayland/files/0001-libweston-Remove-substitute-format-for-ARGB8888.patch
new file mode 100644
index 00000000..33d33b0f
--- /dev/null
+++ b/meta-xilinx-core/recipes-graphics/wayland/files/0001-libweston-Remove-substitute-format-for-ARGB8888.patch
@@ -0,0 +1,29 @@
+From 3fbb596e53524e78703b76c4fdc33cd6ac62f777 Mon Sep 17 00:00:00 2001
+From: Madhurkiran Harikrishnan <madhurkiran.harikrishnan@xilinx.com>
+Date: Fri, 11 Dec 2020 16:21:38 -0800
+Subject: [PATCH] libweston: Remove substitute format for ARGB8888
+
+Xilinx DP gfx layer does not support XRGB8888. Hence, remove the same
+as opaque substitute.
+
+Signed-off-by: Madhurkiran Harikrishnan <madhurkiran.harikrishnan@xilinx.com>
+Upstream-Status : Inappropriate [Xilinx specific]
+---
+ libweston/pixel-formats.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/libweston/pixel-formats.c b/libweston/pixel-formats.c
+index 79dc709..ec2d3b7 100644
+--- a/libweston/pixel-formats.c
++++ b/libweston/pixel-formats.c
+@@ -193,7 +193,6 @@ static const struct pixel_format_info pixel_format_table[] = {
+        {
+                DRM_FORMAT(ARGB8888),
+                BITS_RGBA_FIXED(8, 8, 8, 8),
+-               .opaque_substitute = DRM_FORMAT_XRGB8888,
+                .depth = 32,
+                .bpp = 32,
+                GL_FORMAT(GL_BGRA_EXT),
+-- 
+2.17.1
+
diff --git a/meta-xilinx-core/recipes-graphics/wayland/files/weston.ini b/meta-xilinx-core/recipes-graphics/wayland/files/weston.ini
new file mode 100644
index 00000000..2ff81795
--- /dev/null
+++ b/meta-xilinx-core/recipes-graphics/wayland/files/weston.ini
@@ -0,0 +1,6 @@
+[core]
+idle-time=0
+
+gbm-format=rgb565
+
+require-input=false
diff --git a/meta-xilinx-core/recipes-graphics/wayland/weston-init%.bbappend b/meta-xilinx-core/recipes-graphics/wayland/weston-init%.bbappend
new file mode 100644
index 00000000..ba570d44
--- /dev/null
+++ b/meta-xilinx-core/recipes-graphics/wayland/weston-init%.bbappend
@@ -0,0 +1,7 @@
+FILESEXTRAPATHS:prepend:zynqmp := "${THISDIR}/files:"
+
+SRC_URI:append:zynqmp = " file://weston.ini"
+
+do_install:append:zynqmp() {
+    install -Dm 0700 ${WORKDIR}/weston.ini ${D}/${sysconfdir}/xdg/weston/weston.ini
+}
diff --git a/meta-xilinx-core/recipes-graphics/wayland/weston_%.bbappend b/meta-xilinx-core/recipes-graphics/wayland/weston_%.bbappend
new file mode 100644
index 00000000..caa49063
--- /dev/null
+++ b/meta-xilinx-core/recipes-graphics/wayland/weston_%.bbappend
@@ -0,0 +1,14 @@
+FILESEXTRAPATHS:prepend:zynqmp := "${THISDIR}/files:"
+
+SRC_URI:append:zynqmp = " file://0001-libweston-Remove-substitute-format-for-ARGB8888.patch"
+
+# OpenGL comes from libmali on ev/eg, when egl is enabled
+DEPENDS:append:mali400 = "${@bb.utils.contains('PACKAGECONFIG', 'egl', ' libmali-xlnx', '', d)}"
+
+# Due to the SRC_URI zynqmp specific change, this needs to be SOC_FAMILY_ARCH specific
+SOC_FAMILY_ARCH ??= "${TUNE_PKGARCH}"
+ZYNQMP_PKGARCH = "${SOC_FAMILY_ARCH}"
+# But if egl is enabled, we also need to be SOC_VARIANT_ARCH specific due to libmali
+ZYNQMP_PKGARCH:mali400 = "${@bb.utils.contains('PACKAGECONFIG', 'egl', '${SOC_VARIANT_ARCH}', '${SOC_FAMILY_ARCH}', d)}"
+
+PACKAGE_ARCH:zynqmp = "${ZYNQMP_PKGARCH}"
diff --git a/meta-xilinx-core/recipes-graphics/xorg-xserver/xserver-xf86-config/zynqmp/xorg.conf b/meta-xilinx-core/recipes-graphics/xorg-xserver/xserver-xf86-config/zynqmp/xorg.conf
new file mode 100644
index 00000000..9ef39462
--- /dev/null
+++ b/meta-xilinx-core/recipes-graphics/xorg-xserver/xserver-xf86-config/zynqmp/xorg.conf
@@ -0,0 +1,27 @@
+Section "InputDevice"
+        Identifier      "System Mouse"
+        Driver          "mouse"
+        Option          "Device" "/dev/input/mouse0"
+EndSection
+
+Section "InputDevice"
+        Identifier      "System Keyboard"
+        Driver          "kbd"
+        Option          "Device" "/dev/input/event0"
+EndSection
+
+Section "Device"
+        Identifier      "ZynqMP"
+        Driver          "armsoc"
+        Option          "DRI2"                  "true"
+        Option          "DRI2_PAGE_FLIP"        "false"
+        Option          "DRI2_WAIT_VSYNC"       "true"
+        Option          "SWcursorLCD"           "false"
+        Option          "DEBUG"                 "false"
+EndSection
+
+Section "Screen"
+        Identifier      "DefaultScreen"
+        Device          "ZynqMP"
+        DefaultDepth    16
+EndSection
diff --git a/meta-xilinx-core/recipes-graphics/xorg-xserver/xserver-xf86-config_%.bbappend b/meta-xilinx-core/recipes-graphics/xorg-xserver/xserver-xf86-config_%.bbappend
new file mode 100644
index 00000000..4fc41d05
--- /dev/null
+++ b/meta-xilinx-core/recipes-graphics/xorg-xserver/xserver-xf86-config_%.bbappend
@@ -0,0 +1 @@
+FILESEXTRAPATHS:prepend := "${THISDIR}/${PN}:"
diff --git a/meta-xilinx-core/recipes-kernel/dp/kernel-module-dp_git.bb b/meta-xilinx-core/recipes-kernel/dp/kernel-module-dp_git.bb
new file mode 100755
index 00000000..4d8bd265
--- /dev/null
+++ b/meta-xilinx-core/recipes-kernel/dp/kernel-module-dp_git.bb
@@ -0,0 +1,24 @@
+SUMMARY = "Xilinx DisplayPort Linux Kernel module"
+DESCRIPTION = "Out-of-tree DisplayPort(DP) kernel modules provider for aarch64 devices"
+SECTION = "kernel/modules"
+LICENSE = "GPLv2"
+LIC_FILES_CHKSUM = "file://LICENSE.md;md5=eb723b61539feef013de476e68b5c50a"
+
+XLNX_DP_VERSION = "5.10.0"
+PV = "${XLNX_DP_VERSION}"
+
+S = "${WORKDIR}/git"
+
+BRANCH ?= "xlnx_rel_v2021.2"
+REPO   ?= "git://github.com/xilinx/dp-modules.git;protocol=https"
+SRCREV ?= "46d4790c3d37ad4b878c5a1704df26edb56314f5"
+
+BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}"
+SRC_URI = "${REPO};${BRANCHARG}"
+
+inherit module
+
+EXTRA_OEMAKE += "O=${STAGING_KERNEL_BUILDDIR}"
+COMPATIBLE_MACHINE = "^$"
+COMPATIBLE_MACHINE:zynqmp = "zynqmp"
+COMPATIBLE_MACHINE:versal = "versal"
diff --git a/meta-xilinx-core/recipes-kernel/dtc/python3-dtc_1.6.0.bb b/meta-xilinx-core/recipes-kernel/dtc/python3-dtc_1.6.0.bb
new file mode 100644
index 00000000..f57b2b19
--- /dev/null
+++ b/meta-xilinx-core/recipes-kernel/dtc/python3-dtc_1.6.0.bb
@@ -0,0 +1,27 @@
+SUMMARY = "Device Tree Compiler"
+HOMEPAGE = "https://devicetree.org/"
+DESCRIPTION = "The Device Tree Compiler is a tool used to manipulate the Open-Firmware-like device tree used by PowerPC kernels."
+SECTION = "bootloader"
+LICENSE = "GPLv2 | BSD"
+DEPENDS = "flex-native bison-native swig-native"
+
+SRC_URI = "git://git.kernel.org/pub/scm/utils/dtc/dtc.git"
+
+UPSTREAM_CHECK_GITTAGREGEX = "v(?P<pver>\d+(\.\d+)+)"
+
+LIC_FILES_CHKSUM = "file://libfdt.i;beginline=1;endline=6;md5=afda088c974174a29108c8d80b5dce90"
+
+SRCREV = "2525da3dba9beceb96651dc2986581871dbeca30"
+
+S = "${WORKDIR}/git/pylibfdt"
+
+DEPENDS += "libyaml dtc"
+
+inherit distutils3
+
+do_configure:prepend() {
+    (cd ${S}/../ ; make version_gen.h )
+}
+
+BBCLASSEXTEND = "native nativesdk"
+
diff --git a/meta-xilinx-core/recipes-kernel/hdmi/kernel-module-hdmi_git.bb b/meta-xilinx-core/recipes-kernel/hdmi/kernel-module-hdmi_git.bb
new file mode 100644
index 00000000..65484fca
--- /dev/null
+++ b/meta-xilinx-core/recipes-kernel/hdmi/kernel-module-hdmi_git.bb
@@ -0,0 +1,24 @@
+SUMMARY = "Xilinx HDMI Linux Kernel module"
+DESCRIPTION = "Out-of-tree HDMI kernel modules provider for MPSoC EG/EV devices"
+SECTION = "kernel/modules"
+LICENSE = "GPLv2"
+LIC_FILES_CHKSUM = "file://LICENSE.md;md5=b34277fe156508fd5a650609dc36d1fe"
+
+XLNX_HDMI_VERSION = "5.10.0"
+PV = "${XLNX_HDMI_VERSION}"
+
+S = "${WORKDIR}/git"
+
+BRANCH ?= "xlnx_rel_v2021.2"
+REPO   ?= "git://github.com/Xilinx/hdmi-modules.git;protocol=https"
+SRCREV = "aeb9f2c9a50c5e8dd4245454116c47f841f78825"
+
+BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}"
+SRC_URI = "${REPO};${BRANCHARG}"
+
+inherit module
+
+EXTRA_OEMAKE += "O=${STAGING_KERNEL_BUILDDIR}"
+COMPATIBLE_MACHINE = "^$"
+COMPATIBLE_MACHINE:zynqmp = "zynqmp"
+COMPATIBLE_MACHINE:versal = "versal"
diff --git a/meta-xilinx-core/recipes-kernel/linux-firmware/linux-firmware-ti-bt.bb b/meta-xilinx-core/recipes-kernel/linux-firmware/linux-firmware-ti-bt.bb
new file mode 100644
index 00000000..1ad8ae2e
--- /dev/null
+++ b/meta-xilinx-core/recipes-kernel/linux-firmware/linux-firmware-ti-bt.bb
@@ -0,0 +1,65 @@
+# TIInit_11.8.32.bts is required for bluetooth support but this particular
+# version is not available in the linux-firmware repository.
+#
+SUMMARY = "TI Bluetooth firmware files for use with Linux kernel"
+SECTION = "kernel"
+
+LICENSE = "Firmware-ti-bt"
+
+LIC_FILES_CHKSUM = "file://LICENSE.ti-bt;md5=f39eac9f4573be5b012e8313831e72a9"
+
+# No common license for this, so be sure to include it
+NO_GENERIC_LICENSE[Firmware-ti-bt] = "LICENSE.ti-bt"
+
+SRC_URI = "git://git.ti.com/ti-bt/service-packs.git;protocol=https"
+SRCREV = "c290f8af9e388f37e509ecb111a1b64572b7c225"
+
+S = "${WORKDIR}/git"
+
+inherit allarch
+
+CLEANBROKEN = "1"
+
+do_unpack[postfuncs] += "rename_license"
+
+rename_license() {
+        mv ${S}/LICENSE ${S}/LICENSE.ti-bt
+}
+
+do_compile() {
+        :
+}
+
+do_install() {
+        oe_runmake 'DEST_DIR=${D}' 'BASE_LIB_DIR=${nonarch_base_libdir}'
+
+        # Remove files we're not packaging...
+        rm -f   ${D}${nonarch_base_libdir}/firmware/ti-connectivity/TIInit_7.6.15.bts \
+                ${D}${nonarch_base_libdir}/firmware/ti-connectivity/TIInit_10.6.15.bts \
+                ${D}${nonarch_base_libdir}/firmware/ti-connectivity/TIInit_6.7.16_bt_spec_4.1.bts \
+                ${D}${nonarch_base_libdir}/firmware/ti-connectivity/TIInit_12.8.32.bts \
+                ${D}${nonarch_base_libdir}/firmware/ti-connectivity/TIInit_12.10.28.bts \
+                ${D}${nonarch_base_libdir}/firmware/ti-connectivity/TIInit_6.7.16_avpr_add-on.bts \
+                ${D}${nonarch_base_libdir}/firmware/ti-connectivity/TIInit_6.7.16_bt_spec_4.0.bts \
+                ${D}${nonarch_base_libdir}/firmware/ti-connectivity/TIInit_6.7.16_ble_add-on.bts
+
+        for each in ${D}${nonarch_base_libdir}/firmware/ti-connectivity/* ; do
+                ln -s ti-connectivity/`basename $each` ${D}${nonarch_base_libdir}/firmware/`basename $each`
+        done
+
+        cp LICENSE.ti-bt ${D}${nonarch_base_libdir}/firmware/License.ti-bt
+}
+
+#  11.8.32   =   WL180x, WL183x, WL185x PG2.1 or PG2.2, 8.32 ROM Version
+PACKAGES =+ "${PN}-wl180x ${PN}-license"
+
+FILES:${PN}-license = "${nonarch_base_libdir}/firmware/License.ti-bt"
+
+FILES:${PN}-wl180x = "${nonarch_base_libdir}/firmware/TIInit_11.8.32.bts \
+                      ${nonarch_base_libdir}/firmware/ti-connectivity/TIInit_11.8.32.bts"
+
+RDEPENDS:${PN}-wl180x = "${PN}-license linux-firmware-wl18xx"
+
+LICENSE:${PN}-wl180x = "Firmware-ti-bt"
+
+INSANE_SKIP = "arch"
diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-microblaze.inc b/meta-xilinx-core/recipes-kernel/linux/linux-microblaze.inc
new file mode 100644
index 00000000..4555bc28
--- /dev/null
+++ b/meta-xilinx-core/recipes-kernel/linux/linux-microblaze.inc
@@ -0,0 +1,7 @@
+SRC_URI += "file://mb-no-tree-loop-distribute-patterns.patch"
+
+# MicroBlaze is a uImage target, but its not called 'uImage' instead it is called 'linux.bin.ub'
+python () {
+    if d.getVar('KERNEL_IMAGETYPE', True).endswith('.ub'):
+        d.setVar('DEPENDS', "%s u-boot-mkimage-native" % d.getVar('DEPENDS', True))
+}
diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx-dev.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx-dev.bb
new file mode 100644
index 00000000..acb9938f
--- /dev/null
+++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx-dev.bb
@@ -0,0 +1,18 @@
+# This recipe tracks the 'bleeding edge' linux-xlnx repository.
+# Since this tree is frequently updated, AUTOREV is used to track its contents.
+#
+# To enable this recipe, set PREFERRED_PROVIDER_virtual/kernel = "linux-xlnx-dev"
+
+KBRANCH ?= "master"
+
+# Use the SRCREV for the last tagged revision of linux-xlnx.
+SRCREV ?= '${@oe.utils.conditional("PREFERRED_PROVIDER_virtual/kernel", "linux-xlnx-dev", "${AUTOREV}", "84fb0cc65aae5970471cbc54b0c89009b9b904af", d)}'
+
+# skip version sanity, because the version moves with AUTOREV
+KERNEL_VERSION_SANITY_SKIP = "1"
+
+LINUX_VERSION ?= "4.9+"
+LINUX_VERSION_EXTENSION ?= "-xilinx-dev"
+
+include linux-xlnx.inc
+
diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx.inc b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx.inc
new file mode 100644
index 00000000..31cde189
--- /dev/null
+++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx.inc
@@ -0,0 +1,65 @@
+# This version extension should match CONFIG_LOCALVERSION in defconfig
+XILINX_RELEASE_VERSION ?= ""
+LINUX_VERSION_EXTENSION ?= "-xilinx-${XILINX_RELEASE_VERSION}"
+PV = "${LINUX_VERSION}+git${SRCPV}"
+
+# Sources, by default allow for the use of SRCREV pointing to orphaned tags/commits
+KBRANCH ?= "xlnx_rebase_v5.10"
+SRCBRANCHARG = "${@['nobranch=1', 'branch=${KBRANCH}'][d.getVar('KBRANCH', True) != '']}"
+
+FILESOVERRIDES:append = ":${XILINX_RELEASE_VERSION}"
+KERNELURI ?= "git://github.com/Xilinx/linux-xlnx.git;protocol=https;name=machine"
+YOCTO_META ?= "git://git.yoctoproject.org/yocto-kernel-cache;type=kmeta;name=meta;branch=yocto-5.10;destsuffix=yocto-kmeta"
+SRC_URI = "${KERNELURI};${SRCBRANCHARG} ${YOCTO_META}"
+
+SRCREV_machine ?= "${SRCREV}"
+SRCREV_meta ?= "20b185f6b5afbad309747a7901786e0231dc8195"
+SRCREV_FORMAT = "machine"
+
+require recipes-kernel/linux/linux-yocto.inc
+require linux-microblaze.inc
+
+DESCRIPTION = "Xilinx Kernel"
+LIC_FILES_CHKSUM = "file://COPYING;md5=6bc538ed5bd9a7fc9398086aedcd7e46"
+
+EXTKERNELSRC = "${@'1' if d.getVar('EXTERNALSRC') else ''}"
+
+# Force the use of the KBUILD_DEFCONFIG even if some other defconfig was generated in the ${WORKDIR}
+do_kernel_metadata:prepend () {
+        [ -n "${KBUILD_DEFCONFIG}" ] && [ -e ${WORKDIR}/defconfig ] && rm ${WORKDIR}/defconfig
+}
+
+do_configure:prepend () {
+        if [ -n "${KBUILD_DEFCONFIG}" ] && [ -n "${EXTKERNELSRC}" ]; then
+                cp ${S}/arch/${ARCH}/configs/${KBUILD_DEFCONFIG} ${WORKDIR}/defconfig
+        fi
+}
+
+inherit kernel-simpleimage
+
+# Default to be only compatible with specific machines or soc families
+COMPATIBLE_MACHINE ?= "^$"
+COMPATIBLE_MACHINE:zynq = ".*"
+COMPATIBLE_MACHINE:zynqmp = ".*"
+COMPATIBLE_MACHINE:microblaze = ".*"
+COMPATIBLE_MACHINE:versal = ".*"
+
+# Use DEFCONFIGs for configuring linux-xlnx kernels
+KCONFIG_MODE ?= "alldefconfig"
+KBUILD_DEFCONFIG:zynqmp ?= "xilinx_defconfig"
+KBUILD_DEFCONFIG:zynq ?= "xilinx_zynq_defconfig"
+KBUILD_DEFCONFIG:microblaze ?= "mmu_defconfig"
+KBUILD_DEFCONFIG:versal ?= "xilinx_defconfig"
+
+KERNEL_MODULE_AUTOLOAD:k26 += "usb5744"
+
+# MicroBlaze BSP fragments
+KERNEL_FEATURES:append:kc705-microblazeel = " bsp/xilinx/kc705-microblazeel-features/kc705-microblazeel-features.scc"
+
+KERNEL_FEATURES:append:zynqmp = "${@bb.utils.contains('DISTRO_FEATURES', 'xen', ' features/xen/xen.scc', '', d)}"
+
+KERNEL_FEATURES:append:zynqmp = "${@' features/xilinx/overlay_of/overlay_of.scc' if d.getVar('FPGA_MNGR_RECONFIG_ENABLE') == '1' else ''}"
+
+KERNEL_FEATURES:append:versal = "${@bb.utils.contains('DISTRO_FEATURES', 'xen', ' features/xen/xen.scc', '', d)} features/xilinx/hdmi-module/hdmi-module.scc"
+
+KERNEL_FEATURES:append = " ${@bb.utils.contains('DISTRO_FEATURES', 'virtualization', ' features/ocicontainer/ocicontainer.scc', '', d)}"
diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx/0001-scripts-dtc-Remove-redundant-YYLOC-global-declaratio.patch b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx/0001-scripts-dtc-Remove-redundant-YYLOC-global-declaratio.patch
new file mode 100644
index 00000000..d5b96c2d
--- /dev/null
+++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx/0001-scripts-dtc-Remove-redundant-YYLOC-global-declaratio.patch
@@ -0,0 +1,51 @@
+From e33a814e772cdc36436c8c188d8c42d019fda639 Mon Sep 17 00:00:00 2001
+From: Dirk Mueller <dmueller@suse.com>
+Date: Tue, 14 Jan 2020 18:53:41 +0100
+Subject: [PATCH] scripts/dtc: Remove redundant YYLOC global declaration
+
+gcc 10 will default to -fno-common, which causes this error at link
+time:
+
+  (.text+0x0): multiple definition of `yylloc'; dtc-lexer.lex.o (symbol from plugin):(.text+0x0): first defined here
+
+This is because both dtc-lexer as well as dtc-parser define the same
+global symbol yyloc. Before with -fcommon those were merged into one
+defintion. The proper solution would be to to mark this as "extern",
+however that leads to:
+
+  dtc-lexer.l:26:16: error: redundant redeclaration of 'yylloc' [-Werror=redundant-decls]
+   26 | extern YYLTYPE yylloc;
+      |                ^~~~~~
+In file included from dtc-lexer.l:24:
+dtc-parser.tab.h:127:16: note: previous declaration of 'yylloc' was here
+  127 | extern YYLTYPE yylloc;
+      |                ^~~~~~
+cc1: all warnings being treated as errors
+
+which means the declaration is completely redundant and can just be
+dropped.
+
+Signed-off-by: Dirk Mueller <dmueller@suse.com>
+Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
+[robh: cherry-pick from upstream]
+Cc: stable@vger.kernel.org
+Signed-off-by: Rob Herring <robh@kernel.org>
+---
+ scripts/dtc/dtc-lexer.l | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/scripts/dtc/dtc-lexer.l b/scripts/dtc/dtc-lexer.l
+index 5c6c3fd557d7..b3b7270300de 100644
+--- a/scripts/dtc/dtc-lexer.l
++++ b/scripts/dtc/dtc-lexer.l
+@@ -23,7 +23,6 @@ LINECOMMENT   "//".*\n
+ #include "srcpos.h"
+ #include "dtc-parser.tab.h"
+ 
+-YYLTYPE yylloc;
+ extern bool treesource_error;
+ 
+ /* CAUTION: this will stop working if we ever use yyless() or yyunput() */
+-- 
+2.29.2
+
diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx/mb-no-tree-loop-distribute-patterns.patch b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx/mb-no-tree-loop-distribute-patterns.patch
new file mode 100644
index 00000000..5a4d203d
--- /dev/null
+++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx/mb-no-tree-loop-distribute-patterns.patch
@@ -0,0 +1,47 @@
+Disable tree-loop-distribute-patterns CFLAG
+
+Issue: CR-1086247
+
+GCC 10.2.0 added -ftree-loop-distribute-patterns by default with -O2.  This
+is causing a condition where the kernel will no longer boot.
+
+This is a temporary workaround until we can identify the true cause of
+the boot failure.
+
+Symtoms:
+
+earlycon: uartlite_a0 at MMIO 0x40600000 (options '115200n8')
+printk: bootconsole [uartlite_a0] enabled
+cma: Reserved 16 MiB at 0xaec00000
+Linux version 5.10.0-xilinx-v2020.2 (oe-user@oe-host) (microblazeel-xilinx-linux-gcc (GCC) 10.2.0, GNU ld (GNU Binutils) 2.35.0.20200730) #1 Mon Mar 1 12:58:36 UTC 2021
+setup_memory: max_mapnr: 0x40000
+setup_memory: min_low_pfn: 0x80000
+setup_memory: max_low_pfn: 0xb0000
+setup_memory: max_pfn: 0xc0000
+Zone ranges:
+  DMA      [mem 0x0000000080000000-0x00000000afffffff]
+  Normal   empty
+  HighMem  [mem 0x00000000b0000000-0x00000000bfffffff]
+Movable zone start for each node
+Early memory node ranges
+  node   0: [mem 0x0000000080000000-0x00000000bfffffff]
+Initmem setup node 0 [mem 0x0000000080000000-0x00000000bfffffff]
+<hang>
+
+Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
+
+diff --git a/arch/microblaze/Makefile b/arch/microblaze/Makefile
+index bb980891816d..e368c35ad21c 100644
+--- a/arch/microblaze/Makefile
++++ b/arch/microblaze/Makefile
+@@ -48,6 +48,10 @@ CPUFLAGS-1 += $(call cc-option,-mcpu=v$(CPU_VER))
+ # r31 holds current when in kernel mode
+ KBUILD_CFLAGS += -ffixed-r31 $(CPUFLAGS-y) $(CPUFLAGS-1) $(CPUFLAGS-2)
+ 
++# GCC 10.x now has -ftree-loop-distribute-patterns by default in -O2
++# This causes a boot failure, so disable it
++KBUILD_CFLAGS += -fno-tree-loop-distribute-patterns
++
+ head-y := arch/microblaze/kernel/head.o
+ libs-y += arch/microblaze/lib/
+ core-y += arch/microblaze/kernel/
diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2021.2.bb b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2021.2.bb
new file mode 100644
index 00000000..660f6037
--- /dev/null
+++ b/meta-xilinx-core/recipes-kernel/linux/linux-xlnx_2021.2.bb
@@ -0,0 +1,9 @@
+LINUX_VERSION = "5.10"
+KBRANCH="xlnx_rebase_v5.10"
+SRCREV = "568989d44176ae0a38ea78c16d0590c726d3b60a"
+
+KCONF_AUDIT_LEVEL="0"
+
+include linux-xlnx.inc
+
+FILESEXTRAPATHS:prepend := "${THISDIR}/${PN}:"
diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-yocto-dev.bbappend b/meta-xilinx-core/recipes-kernel/linux/linux-yocto-dev.bbappend
new file mode 100644
index 00000000..05c39951
--- /dev/null
+++ b/meta-xilinx-core/recipes-kernel/linux/linux-yocto-dev.bbappend
@@ -0,0 +1 @@
+require linux-yocto-xilinx.inc
diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-yocto-tiny_%.bbappend b/meta-xilinx-core/recipes-kernel/linux/linux-yocto-tiny_%.bbappend
new file mode 100644
index 00000000..05c39951
--- /dev/null
+++ b/meta-xilinx-core/recipes-kernel/linux/linux-yocto-tiny_%.bbappend
@@ -0,0 +1 @@
+require linux-yocto-xilinx.inc
diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-yocto-xilinx.inc b/meta-xilinx-core/recipes-kernel/linux/linux-yocto-xilinx.inc
new file mode 100644
index 00000000..708c99f0
--- /dev/null
+++ b/meta-xilinx-core/recipes-kernel/linux/linux-yocto-xilinx.inc
@@ -0,0 +1,23 @@
+FILESEXTRAPATHS:prepend := "${THISDIR}/linux-xlnx:"
+
+require linux-microblaze.inc
+
+# Zynq default generic KMACHINE
+COMPATIBLE_MACHINE:zynq = "zynq"
+KMACHINE:zynq = "zynq"
+
+# ZynqMP default generic KMACHINE
+COMPATIBLE_MACHINE:zynqmp = "zynqmp"
+KMACHINE:zynqmp = "zynqmp"
+
+# MicroBlaze KMACHINEs
+KMACHINE:ml605-qemu-microblazeel = "qemumicroblazeel"
+KMACHINE:s3adsp1800-qemu-microblazeeb = "qemumicroblazeeb"
+
+# MicroBlaze default generic KMACHINE
+KMACHINE:microblaze = "microblaze"
+COMPATIBLE_MACHINE:microblaze = "microblaze"
+
+# Default kernel config fragements for specific machines
+KERNEL_FEATURES:append:kc705-microblazeel = " bsp/xilinx/kc705-microblazeel-features/kc705-microblazeel-features.scc"
+
diff --git a/meta-xilinx-core/recipes-kernel/linux/linux-yocto_%.bbappend b/meta-xilinx-core/recipes-kernel/linux/linux-yocto_%.bbappend
new file mode 100644
index 00000000..05c39951
--- /dev/null
+++ b/meta-xilinx-core/recipes-kernel/linux/linux-yocto_%.bbappend
@@ -0,0 +1 @@
+require linux-yocto-xilinx.inc
diff --git a/meta-xilinx-core/recipes-kernel/lopper/lopper.bbappend b/meta-xilinx-core/recipes-kernel/lopper/lopper.bbappend
new file mode 100644
index 00000000..aa552fe5
--- /dev/null
+++ b/meta-xilinx-core/recipes-kernel/lopper/lopper.bbappend
@@ -0,0 +1,54 @@
+DEPENDS = " \
+    dtc \
+    python3-dtc \
+    python3-flask \
+    python3-flask-restful \
+    python3-six \
+    python3-pandas \
+    python3-ruamel-yaml \
+    python3-anytree \
+    python3-pyyaml \
+    python3-humanfriendly \
+"
+
+RDEPENDS:${PN} += " \
+    python3-flask \
+    python3-flask-restful \
+    python3-six \
+    python3-pandas \
+    python3-ruamel-yaml \
+    python3-anytree \
+    python3-pyyaml \
+"
+
+SRC_URI = "git://github.com/devicetree-org/lopper.git;branch=master"
+SRCREV = "4fc085c4be031996e7f48dcaf03d0782989c8d58"
+
+do_install() {
+    install -d "${D}/${bindir}"
+    install -d "${D}/${datadir}/${BPN}"
+
+    install -m 0644 "${S}/README" "${D}/${datadir}/${BPN}"
+    install -m 0644 "${S}/README-architecture.txt" "${D}/${datadir}/${BPN}"
+    install -m 0644 "${S}/README.pydoc" "${D}/${datadir}/${BPN}"
+    install -m 0644 "${S}/LICENSE.md" "${D}/${datadir}/${BPN}"
+
+    install -d "${D}/${datadir}/${BPN}/assists"
+    #install -m 0644 "${S}/assists/"* "${D}/${datadir}/${BPN}/assists/"
+    cp -r "${S}/assists/"* "${D}/${datadir}/${BPN}/assists/"
+
+    install -d "${D}/${datadir}/${BPN}/lops"
+    install -m 0644 "${S}/lops/"* "${D}/${datadir}/${BPN}/lops/"
+
+    install -d "${D}/${datadir}/${BPN}/device-trees"
+    install -m 0644 "${S}/device-trees/"* "${D}/${datadir}/${BPN}/device-trees/"
+
+    install -m 0644 "${S}/"lopper.ini "${D}/${datadir}/${BPN}/"
+
+    install -m 0755 "${S}/"lopper*.py "${D}/${datadir}/${BPN}/"
+    sed -i 's,#!/usr/bin/python3,#!/usr/bin/env python3,' ${D}/${datadir}/${BPN}/lopper.py
+    sed -i 's,#!/usr/bin/python3,#!/usr/bin/env python3,' ${D}/${datadir}/${BPN}/lopper_sanity.py
+
+    datadir_relpath=${@os.path.relpath(d.getVar('datadir'), d.getVar('bindir'))}
+    ln -s "${datadir_relpath}/${BPN}/lopper.py" "${D}/${bindir}/"
+}
diff --git a/meta-xilinx-core/recipes-kernel/lopper/xilinx-lops.bb b/meta-xilinx-core/recipes-kernel/lopper/xilinx-lops.bb
new file mode 100644
index 00000000..77456376
--- /dev/null
+++ b/meta-xilinx-core/recipes-kernel/lopper/xilinx-lops.bb
@@ -0,0 +1,27 @@
+SUMMARY = "Device tree lopper - lops"
+DESCRIPTION = "Xilinx specific lop files"
+SECTION = "bootloader"
+LICENSE = "BSD-3-Clause"
+
+RDEPENDS:${PN} += "lopper"
+
+SRC_URI = " \
+        file://lop-microblaze-yocto.dts \
+        file://lop-xilinx-id-cpus.dts \
+        "
+
+LIC_FILES_CHKSUM = "file://lop-microblaze-yocto.dts;endline=8;md5=a0e89d39fa397ec5d5320409ff701280"
+
+S = "${WORKDIR}"
+
+do_configure[noexec] = '1'
+do_compile[noexec] = '1'
+
+do_install() {
+        mkdir -p ${D}/${datadir}/lopper/lops
+        cp ${S}/lop-microblaze-yocto.dts ${D}/${datadir}/lopper/lops/.
+        cp ${S}/lop-xilinx-id-cpus.dts   ${D}/${datadir}/lopper/lops/.
+}
+
+FILES:${PN} += "${datadir}/lopper/lops"
+BBCLASSEXTEND = "native nativesdk"
diff --git a/meta-xilinx-core/recipes-kernel/lopper/xilinx-lops/lop-microblaze-yocto.dts b/meta-xilinx-core/recipes-kernel/lopper/xilinx-lops/lop-microblaze-yocto.dts
new file mode 100644
index 00000000..72eb4665
--- /dev/null
+++ b/meta-xilinx-core/recipes-kernel/lopper/xilinx-lops/lop-microblaze-yocto.dts
@@ -0,0 +1,244 @@
+/*
+ * Copyright (c) 2020 Xilinx Inc. All rights reserved.
+ *
+ * Author:
+ *       Bruce Ashfield <bruce.ashfield@xilinx.com>
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/dts-v1/;
+
+/ {
+        compatible = "system-device-tree-v1,lop";
+        lops {
+                compatible = "system-device-tree-v1,lop";
+                track_feature: track_feature {
+                        compatible = "system-device-tree-v1,lop,code-v1";
+                        noexec;
+                        code = "
+                            # print( 'track: lopper library routine: %s' % node )
+                            try:
+                                node.tunes[prop] = prop
+                            except:
+                                pass
+                        ";
+                };
+                lop_0_1 {
+                      compatible = "system-device-tree-v1,lop,select-v1";
+                      select_1;
+                      select_2 = "/cpus_microblaze.*/cpu*.*:compatible:.*microblaze";
+                      lop_0_2 {
+                              compatible = "system-device-tree-v1,lop,code-v1";
+                              inherit = "subsystem";
+                              code = "
+                                    for n in tree.__selected__:
+                                        val = n['compatible'].value[0]
+                                        if val == 'pmu-microblaze':
+                                           n.tunes = OrderedDict()
+                                           n.tunes['microblaze'] = 'microblaze'
+                                           n.tunes['version'] = 'v9.2'
+
+                                        if val == 'pmc-microblaze' or val == 'psm-microblaze':
+                                           n.tunes = OrderedDict()
+                                           n.tunes['microblaze'] = 'microblaze'
+                                           n.tunes['version'] = 'v10.0'
+
+                                        n.tune_type = val
+                        ";
+                      };
+                };
+                lop_1_1 {
+                      compatible = "system-device-tree-v1,lop,select-v1";
+                      select_1;
+                      select_2 = "/cpus_microblaze.*/cpu*.*:compatible:.*microblaze";
+                      select_3 = ":xlnx,use-barrel:1";
+                      lop_1_1_1 {
+                          compatible = "system-device-tree-v1,lop,code-v1";
+                          code = "
+                               if __selected__:
+                                   for n in __selected__:
+                                       n.tunes['barrel-shift'] = 'barrel-shift'
+                          ";
+                      };
+                };
+                lop_2_1 {
+                      compatible = "system-device-tree-v1,lop,select-v1";
+                      select_1;
+                      select_2 = "/cpus_microblaze.*/cpu*.*:compatible:.*microblaze";
+                      select_3 = ":xlnx,endianness:!1";
+                      lop_2_1_1 {
+                          compatible = "system-device-tree-v1,lop,code-v1";
+                          code = "
+                               if __selected__:
+                                   for n in __selected__:
+                                       n.tunes['bigendian'] = 'bigendian'
+                          ";
+                      };
+                };
+                lop_3_1 {
+                      compatible = "system-device-tree-v1,lop,select-v1";
+                      select_1;
+                      select_2 = "/cpus_microblaze.*/cpu*.*:compatible:.*microblaze";
+                      select_3 = ":xlnx,data-size:0x40";
+                      lop_3_1_1 {
+                          compatible = "system-device-tree-v1,lop,code-v1";
+                          code = "
+                               if __selected__:
+                                   for n in __selected__:
+                                       n.tunes['64-bit'] = '64-bit'
+                          ";
+                      };
+                };
+                lop_4_1 {
+                      compatible = "system-device-tree-v1,lop,select-v1";
+                      select_1;
+                      select_2 = "/cpus_microblaze.*/cpu*.*:compatible:.*microblaze";
+                      select_3 = ":xlnx,use-pcmp-instr:1";
+                      lop_4_1_1 {
+                          compatible = "system-device-tree-v1,lop,code-v1";
+                          code = "
+                               if __selected__:
+                                   for n in __selected__:
+                                       n.tunes['pattern-compare'] = 'pattern-compare'
+                          ";
+                      };
+                };
+                lop_5_1 {
+                      compatible = "system-device-tree-v1,lop,select-v1";
+                      select_1;
+                      select_2 = "/cpus_microblaze.*/cpu*.*:compatible:.*microblaze";
+                      select_3 = ":xlnx,use-reorder-instr:!0";
+                      lop_5_1_1 {
+                          compatible = "system-device-tree-v1,lop,code-v1";
+                          code = "
+                               if __selected__:
+                                   for n in __selected__:
+                                       n.tunes['reorder'] = 'reorder'
+                          ";
+                      };
+                };
+                lop_6_1 {
+                      compatible = "system-device-tree-v1,lop,select-v1";
+                      select_1;
+                      select_2 = "/cpus_microblaze.*/cpu*.*:compatible:.*microblaze";
+                      select_3 = ":xlnx,area-optimized:2";
+                      lop_6_1_1 {
+                          compatible = "system-device-tree-v1,lop,code-v1";
+                          code = "
+                               if __selected__:
+                                   for n in __selected__:
+                                       n.tunes['frequency-optimized'] = 'frequency-optimized'
+                          ";
+                      };
+                };
+                lop_7_1 {
+                      compatible = "system-device-tree-v1,lop,select-v1";
+                      select_1;
+                      select_2 = "/cpus_microblaze.*/cpu*.*:compatible:.*microblaze";
+                      select_3 = ":xlnx,use-hw-mul:1";
+                      lop_7_1_1 {
+                          compatible = "system-device-tree-v1,lop,code-v1";
+                          code = "
+                               if __selected__:
+                                   for n in __selected__:
+                                       n.tunes['multiply-low'] = 'multiply-low'
+                          ";
+                      };
+                };
+                lop_8_1 {
+                      compatible = "system-device-tree-v1,lop,select-v1";
+                      select_1;
+                      select_2 = "/cpus_microblaze.*/cpu*.*:compatible:.*microblaze";
+                      select_3 = ":xlnx,use-hw-mul:2";
+                      lop_8_1_1 {
+                          compatible = "system-device-tree-v1,lop,code-v1";
+                          code = "
+                               if __selected__:
+                                   for n in __selected__:
+                                       n.tunes['multiply-high'] = 'multiply-high'
+                          ";
+                      };
+                };
+                lop_9_1 {
+                      compatible = "system-device-tree-v1,lop,select-v1";
+                      select_1;
+                      select_2 = "/cpus_microblaze.*/cpu*.*:compatible:.*microblaze";
+                      select_3 = ":xlnx,use-div:1";
+                      lop_9_1_1 {
+                          compatible = "system-device-tree-v1,lop,code-v1";
+                          code = "
+                               if __selected__:
+                                   for n in __selected__:
+                                       n.tunes['divide-hard'] = 'divide-hard'
+                          ";
+                      };
+                };
+                lop_10_1 {
+                      compatible = "system-device-tree-v1,lop,select-v1";
+                      select_1;
+                      select_2 = "/cpus_microblaze.*/cpu*.*:compatible:.*microblaze";
+                      select_3 = ":xlnx,use-fpu:!1";
+                      select_4 = ":xlnx,use-fpu:!2";
+                      lop_10_1_1 {
+                          compatible = "system-device-tree-v1,lop,code-v1";
+                          code = "
+                               if __selected__:
+                                   for n in __selected__:
+                                       n.tunes['fpu-soft'] = 'fpu-soft'
+                          ";
+                      };
+                };
+                lop_11_1 {
+                      compatible = "system-device-tree-v1,lop,select-v1";
+                      select_1;
+                      select_2 = "/cpus_microblaze.*/cpu*.*:compatible:.*microblaze";
+                      select_3 = ":xlnx,use-fpu:1";
+                      lop_11_1_1 {
+                          compatible = "system-device-tree-v1,lop,code-v1";
+                          code = "
+                               if __selected__:
+                                   for n in __selected__:
+                                       n.tunes['fpu-hard'] = 'fpu-hard'
+                          ";
+                      };
+                };
+                lop_12_1 {
+                      compatible = "system-device-tree-v1,lop,select-v1";
+                      select_1;
+                      select_2 = "/cpus_microblaze.*/cpu*.*:compatible:.*microblaze";
+                      select_3 = ":xlnx,use-fpu:2";
+                      lop_12_1_1 {
+                          compatible = "system-device-tree-v1,lop,code-v1";
+                          code = "
+                               if __selected__:
+                                   for n in __selected__:
+                                       n.tunes['fpu-hard-extended'] = 'fpu-hard-extended'
+                          ";
+                      };
+                };
+                lop_output_tunes {
+                      compatible = "system-device-tree-v1,lop,select-v1";
+                      select_1;
+                      select_2 = "/cpus_microblaze.*/cpu*.*:compatible:.*microblaze";
+                      lop_output_code {
+                           compatible = "system-device-tree-v1,lop,code-v1";
+                           code = "
+                               cpu_addr = 0
+                               for n in __selected__:
+                                   tname = re.split('@', n.name)
+                                   tname = tname[0]+str(cpu_addr)
+                                   cpu_addr += 1
+                                   print( 'AVAILTUNES += \"microblaze-%s\"' % tname )
+                                   print( 'TUNE_FEATURES:tune-microblaze-%s = \"' % tname, end='' )
+                                   for t in n.tunes.values():
+                                       print( ' %s' % t, end='' )
+                                   print( '\"' )
+                                   print( 'PACKAGE_EXTRA_ARCHS:tune-microblaze-%s = \"${TUNE_PKGARCH}\"' % tname )
+                                   print( 'TUNE_FEATURES:tune-%s = \"${TUNE_FEATURES:tune-microblaze-%s}\"\\n' % (n.tune_type,tname) )
+
+                               ";
+                      };
+                };
+        };
+};
diff --git a/meta-xilinx-core/recipes-kernel/lopper/xilinx-lops/lop-xilinx-id-cpus.dts b/meta-xilinx-core/recipes-kernel/lopper/xilinx-lops/lop-xilinx-id-cpus.dts
new file mode 100644
index 00000000..67d68bba
--- /dev/null
+++ b/meta-xilinx-core/recipes-kernel/lopper/xilinx-lops/lop-xilinx-id-cpus.dts
@@ -0,0 +1,127 @@
+/*
+ * Copyright (c) 2019,2020 Xilinx Inc. All rights reserved.
+ *
+ * Author:
+ *       Bruce Ashfield <bruce.ashfield@xilinx.com>
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/dts-v1/;
+
+/ {
+        compatible = "system-device-tree-v1,lop";
+        lops {
+                compatible = "system-device-tree-v1,lop";
+                lop_0_1 {
+                      compatible = "system-device-tree-v1,lop,select-v1";
+                      select_1;
+                      select_2 = "/.*:os,type:.*";
+                      lop_0_2 {
+                              compatible = "system-device-tree-v1,lop,code-v1";
+                              inherit = "lopper_lib";
+                              code = "
+                                   for s in __selected__:
+                                       os_type = s['os,type'].value[0]
+                                       try:
+                                           domain_name = s.label
+                                       except:
+                                            domain_name = s.name
+                                       if not domain_name:
+                                            domain_name = s.name
+                                       try:
+                                           cpu = s['cpus']
+                                       except:
+                                           print( '[ERROR]: os,type node, has no cpu reference' )
+                                       try:
+                                           cpu_node = tree.pnode( cpu.value[0] )
+                                           cpu_mask = cpu[1]
+                                       except:
+                                           print( '[ERROR]: os,type node, has invalid cpu reference' )
+
+                                       cpu_output = {}
+                                       cpus_refd, cpus_unrefd = lopper_lib.cpu_refs( tree, cpu )
+                                       for c in cpus_refd:
+                                           cpu_type = c['compatible'].value[0]
+                                           cpu_output[cpu_type] = '{} {} {}'.format(cpu_type,domain_name,os_type)
+
+                                       # print the summary lines
+                                       for o in cpu_output.values():
+                                           print( '%s' % o )
+                        ";
+                      };
+                };
+                lop_0_3 {
+                      compatible = "system-device-tree-v1,lop,select-v1";
+                      select_1;
+                      select_2 = "/.*:compatible:openamp,domain-v1";
+                      select_3 = ":!os,type:";
+                      select_4 = ":compatible:!xilinx,subsystem-v1";
+                      lop_0_3_1 {
+                              compatible = "system-device-tree-v1,lop,code-v1";
+                              inherit = "lopper_lib";
+                              code = "
+                                   if __selected__:
+                                       print( '# global \\'all\\' domains' )
+                                   # __selected__ are domains with no os,type specificiation
+                                   # we'll dump them to a global 'all' domain
+                                   for s in __selected__:
+                                       os_type = 'linux'
+                                       try:
+                                           domain_name = s.label
+                                       except:
+                                            domain_name = s.name
+                                       if not domain_name:
+                                            domain_name = s.name
+                                       try:
+                                           cpu = s['cpus']
+                                       except:
+                                           print( '[ERROR]: os,type node, has no cpu reference' )
+                                       try:
+                                           cpu_node = tree.pnode( cpu.value[0] )
+                                           cpu_mask = cpu[1]
+                                       except:
+                                           print( '[ERROR]: os,type node, has invalid cpu reference' )
+
+                                       cpu_output = {}
+                                       cpus_refd, cpus_unrefd = lopper_lib.cpu_refs( tree, cpu )
+                                       for c in cpus_refd:
+                                           cpu_type = c['compatible'].value[0]
+                                           cpu_output[cpu_type] = '{} {} {}'.format(cpu_type,domain_name,os_type)
+
+                                       # print the summary lines
+                                       for o in cpu_output.values():
+                                           print( '%s' % o )
+                        ";
+                      };
+                };
+                lop_0_4 {
+                      compatible = "system-device-tree-v1,lop,select-v1";
+                      select_1;
+                      select_2 = "/.*:compatible:cpus,cluster";
+                      lop_0_3_1 {
+                              compatible = "system-device-tree-v1,lop,code-v1";
+                              inherit = "lopper_lib";
+                              code = "
+                                     cpu_output = {}
+                                     for c in __selected__:
+                                         for c_node in c.subnodes( children_only = True ):
+                                             try:
+                                                 cpu_node = c_node['device_type'].value[0]
+                                             except:
+                                                 cpu_node = None
+                                             if cpu_node:
+                                                 if c_node.ref == 0:
+                                                     cpu_type = c_node['compatible'].value[0]
+                                                     cpu_output[cpu_type] = '{} {} {}'.format(cpu_type,'None','None')
+
+                                     if cpu_output:
+                                         print( '# global no-domain cpus' )
+
+                                         for o in cpu_output.values():
+                                             print( '%s' % o )
+                                     ";
+                      };
+                };
+        };
+};
diff --git a/meta-xilinx-core/recipes-multimedia/gstreamer/gstreamer1.0-plugins-base_%.bbappend b/meta-xilinx-core/recipes-multimedia/gstreamer/gstreamer1.0-plugins-base_%.bbappend
new file mode 100644
index 00000000..ca910830
--- /dev/null
+++ b/meta-xilinx-core/recipes-multimedia/gstreamer/gstreamer1.0-plugins-base_%.bbappend
@@ -0,0 +1,4 @@
+# OpenGL comes from libmali on ev/eg, when egl is enabled
+DEPENDS:append:mali400 = "${@bb.utils.contains('PACKAGECONFIG', 'egl', ' libmali-xlnx', '', d)}"
+
+PACKAGE_ARCH:mali400 = "${@bb.utils.contains('PACKAGECONFIG', 'egl', '${SOC_VARIANT_ARCH}', '${TUNE_PKGARCH}', d)}"
diff --git a/meta-xilinx-core/recipes-multimedia/vcu/kernel-module-vcu.bb b/meta-xilinx-core/recipes-multimedia/vcu/kernel-module-vcu.bb
new file mode 100644
index 00000000..93733631
--- /dev/null
+++ b/meta-xilinx-core/recipes-multimedia/vcu/kernel-module-vcu.bb
@@ -0,0 +1,28 @@
+SUMMARY = "Linux kernel module for Video Code Unit"
+DESCRIPTION = "Out-of-tree VCU decoder, encoder and common kernel modules provider for MPSoC EV devices"
+SECTION = "kernel/modules"
+LICENSE = "GPLv2"
+LIC_FILES_CHKSUM = "file://LICENSE.md;md5=eb723b61539feef013de476e68b5c50a"
+
+XILINX_VCU_VERSION = "1.0.0"
+PV = "${XILINX_VCU_VERSION}-xilinx-${XILINX_RELEASE_VERSION}+git${SRCPV}"
+
+S = "${WORKDIR}/git"
+
+BRANCH = "xlnx_rel_v2021.2"
+REPO = "git://github.com/Xilinx/vcu-modules.git;protocol=https"
+SRCREV = "e208ae31f663af77b1b703b3c038ce7bf812fa83"
+
+BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}"
+SRC_URI = "${REPO};${BRANCHARG}"
+
+inherit module
+
+EXTRA_OEMAKE += "O=${STAGING_KERNEL_BUILDDIR}"
+
+RDEPENDS:${PN} = "vcu-firmware"
+
+COMPATIBLE_MACHINE = "^$"
+COMPATIBLE_MACHINE:zynqmp = "zynqmp"
+
+KERNEL_MODULE_AUTOLOAD += "dmaproxy"
diff --git a/meta-xilinx-core/recipes-multimedia/vcu/libomxil-xlnx.bb b/meta-xilinx-core/recipes-multimedia/vcu/libomxil-xlnx.bb
new file mode 100644
index 00000000..7d37c66a
--- /dev/null
+++ b/meta-xilinx-core/recipes-multimedia/vcu/libomxil-xlnx.bb
@@ -0,0 +1,50 @@
+SUMMARY = "OpenMAX Integration layer for VCU"
+DESCRIPTION = "OMX IL Libraries,test applications and headers for VCU"
+LICENSE = "Proprietary"
+LIC_FILES_CHKSUM = "file://LICENSE.md;md5=03a7aef7e6f6a76a59fd9b8ba450b493"
+
+XILINX_VCU_VERSION = "1.0.0"
+PV = "${XILINX_VCU_VERSION}-xilinx-${XILINX_RELEASE_VERSION}+git${SRCPV}"
+
+BRANCH ?= "xlnx_rel_v2021.2"
+REPO   ?= "git://github.com/Xilinx/vcu-omx-il.git;protocol=https"
+SRCREV = "a9d452e772da6bc43f524230c79e6dc0f2442fd7"
+
+BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}"
+SRC_URI = "${REPO};${BRANCHARG}"
+
+S  = "${WORKDIR}/git"
+
+COMPATIBLE_MACHINE = "^$"
+COMPATIBLE_MACHINE:zynqmp = "zynqmp"
+
+PACKAGE_ARCH = "${SOC_FAMILY_ARCH}"
+
+DEPENDS = "libvcu-xlnx"
+RDEPENDS:${PN} = "kernel-module-vcu libvcu-xlnx"
+
+EXTERNAL_INCLUDE="${STAGING_INCDIR}/vcu-ctrl-sw/include"
+
+EXTRA_OEMAKE = " \
+    CC='${CC}' CXX='${CXX} ${CXXFLAGS}' \
+    EXTERNAL_INCLUDE='${EXTERNAL_INCLUDE}' \
+    "
+
+do_install() {
+    install -d ${D}${libdir}
+    install -d ${D}${includedir}/vcu-omx-il
+
+    install -m 0644 ${S}/omx_header/*.h ${D}${includedir}/vcu-omx-il
+
+    install -Dm 0755 ${S}/bin/omx_decoder ${D}/${bindir}/omx_decoder
+    install -Dm 0755 ${S}/bin/omx_encoder ${D}/${bindir}/omx_encoder
+
+    oe_libinstall -C ${S}/bin/ -so libOMX.allegro.core ${D}/${libdir}/
+    oe_libinstall -C ${S}/bin/ -so libOMX.allegro.video_decoder ${D}/${libdir}/
+    oe_libinstall -C ${S}/bin/ -so libOMX.allegro.video_encoder ${D}/${libdir}/
+}
+
+# These libraries shouldn't get installed in world builds unless something
+# explicitly depends upon them.
+
+EXCLUDE_FROM_WORLD = "1"
diff --git a/meta-xilinx-core/recipes-multimedia/vcu/libvcu-xlnx.bb b/meta-xilinx-core/recipes-multimedia/vcu/libvcu-xlnx.bb
new file mode 100644
index 00000000..0a5ab35e
--- /dev/null
+++ b/meta-xilinx-core/recipes-multimedia/vcu/libvcu-xlnx.bb
@@ -0,0 +1,42 @@
+SUMMARY = "Control Software for VCU"
+DESCRIPTION = "Control software libraries, test applications and headers provider for VCU"
+LICENSE = "Proprietary"
+LIC_FILES_CHKSUM = "file://LICENSE.md;md5=03a7aef7e6f6a76a59fd9b8ba450b493"
+
+XILINX_VCU_VERSION = "1.0.0"
+PV = "${XILINX_VCU_VERSION}-xilinx-${XILINX_RELEASE_VERSION}+git${SRCPV}"
+
+BRANCH ?= "xlnx_rel_v2021.2"
+REPO   ?= "git://github.com/Xilinx/vcu-ctrl-sw.git;protocol=https"
+SRCREV = "372f702dc2983f42d219ce37000eae4b0515ec85"
+
+BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}"
+SRC_URI = "${REPO};${BRANCHARG}"
+
+S  = "${WORKDIR}/git"
+
+COMPATIBLE_MACHINE = "^$"
+COMPATIBLE_MACHINE:zynqmp = "zynqmp"
+
+PACKAGE_ARCH = "${SOC_FAMILY_ARCH}"
+
+RDEPENDS:${PN} = "kernel-module-vcu"
+
+EXTRA_OEMAKE = "CC='${CC}' CXX='${CXX} ${CXXFLAGS}'"
+
+do_install() {
+    install -d ${D}${libdir}
+    install -d ${D}${includedir}/vcu-ctrl-sw/include
+
+    install -Dm 0755 ${S}/bin/ctrlsw_encoder ${D}/${bindir}/ctrlsw_encoder
+    install -Dm 0755 ${S}/bin/ctrlsw_decoder ${D}/${bindir}/ctrlsw_decoder
+
+    oe_runmake install_headers INSTALL_HDR_PATH=${D}${includedir}/vcu-ctrl-sw/include
+    oe_libinstall -C ${S}/bin/ -so liballegro_decode ${D}/${libdir}/
+    oe_libinstall -C ${S}/bin/ -so liballegro_encode ${D}/${libdir}/
+}
+
+# These libraries shouldn't get installed in world builds unless something
+# explicitly depends upon them.
+
+EXCLUDE_FROM_WORLD = "1"
diff --git a/meta-xilinx-core/recipes-multimedia/vcu/vcu-firmware.bb b/meta-xilinx-core/recipes-multimedia/vcu/vcu-firmware.bb
new file mode 100644
index 00000000..2c4fc780
--- /dev/null
+++ b/meta-xilinx-core/recipes-multimedia/vcu/vcu-firmware.bb
@@ -0,0 +1,39 @@
+SUMMARY = "Firmware for VCU"
+DESCRIPTION = "Firmware binaries provider for VCU"
+LICENSE = "Proprietary"
+LIC_FILES_CHKSUM = "file://LICENSE;md5=63b45903a9a50120df488435f03cf498"
+
+XILINX_VCU_VERSION = "1.0.0"
+PV = "${XILINX_VCU_VERSION}-xilinx-${XILINX_RELEASE_VERSION}+git${SRCPV}"
+
+S  = "${WORKDIR}/git"
+
+BRANCH ?= "xlnx_rel_v2021.2"
+REPO ?= "git://github.com/Xilinx/vcu-firmware.git;protocol=https"
+SRCREV = "17ef70e3a52b972f2c1f821f7b20d2f7af003711"
+
+BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}"
+SRC_URI   = "${REPO};${BRANCHARG}"
+
+COMPATIBLE_MACHINE = "^$"
+COMPATIBLE_MACHINE:zynqmp = "zynqmp"
+
+PACKAGE_ARCH = "${SOC_FAMILY_ARCH}"
+
+do_install() {
+    install -Dm 0644 ${S}/${XILINX_VCU_VERSION}/lib/firmware/al5d_b.fw ${D}/lib/firmware/al5d_b.fw
+    install -Dm 0644 ${S}/${XILINX_VCU_VERSION}/lib/firmware/al5d.fw ${D}/lib/firmware/al5d.fw
+    install -Dm 0644 ${S}/${XILINX_VCU_VERSION}/lib/firmware/al5e_b.fw ${D}/lib/firmware/al5e_b.fw
+    install -Dm 0644 ${S}/${XILINX_VCU_VERSION}/lib/firmware/al5e.fw ${D}/lib/firmware/al5e.fw
+}
+
+# Inhibit warnings about files being stripped
+INHIBIT_PACKAGE_DEBUG_SPLIT = "1"
+INHIBIT_PACKAGE_STRIP = "1"
+FILES:${PN} = "/lib/firmware/*"
+
+# These libraries shouldn't get installed in world builds unless something
+# explicitly depends upon them.
+EXCLUDE_FROM_WORLD = "1"
+
+INSANE_SKIP:${PN} = "ldflags"
diff --git a/meta-xilinx-core/recipes-support/libgpg-error/files/lock-obj-pub.microblazeel-unknown-linux-gnu.h b/meta-xilinx-core/recipes-support/libgpg-error/files/lock-obj-pub.microblazeel-unknown-linux-gnu.h
new file mode 100644
index 00000000..9843f4d9
--- /dev/null
+++ b/meta-xilinx-core/recipes-support/libgpg-error/files/lock-obj-pub.microblazeel-unknown-linux-gnu.h
@@ -0,0 +1,23 @@
+## lock-obj-pub.microblazeel-xilinx-linux-gnu.h
+## File created by gen-posix-lock-obj - DO NOT EDIT
+## To be included by mkheader into gpg-error.h
+
+typedef struct
+{
+  long _vers;
+  union {
+    volatile char _priv[24];
+    long _x_align;
+    long *_xp_align;
+  } u;
+} gpgrt_lock_t;
+
+#define GPGRT_LOCK_INITIALIZER {1,{{0,0,0,0,0,0,0,0, \
+                                    0,0,0,0,0,0,0,0, \
+                                    0,0,0,0,0,0,0,0}}}
+##
+## Local Variables:
+## mode: c
+## buffer-read-only: t
+## End:
+##
diff --git a/meta-xilinx-core/recipes-support/libgpg-error/libgpg-error_%.bbappend b/meta-xilinx-core/recipes-support/libgpg-error/libgpg-error_%.bbappend
new file mode 100644
index 00000000..f3e920c2
--- /dev/null
+++ b/meta-xilinx-core/recipes-support/libgpg-error/libgpg-error_%.bbappend
@@ -0,0 +1,8 @@
+FILESEXTRAPATHS:prepend := "${THISDIR}/files:"
+
+SRC_URI:append:microblaze = " file://lock-obj-pub.microblazeel-unknown-linux-gnu.h"
+
+do_configure:append:microblaze () {
+        cp ${WORKDIR}/lock-obj-pub.microblazeel-unknown-linux-gnu.h ${S}/src/syscfg/
+}
+
diff --git a/meta-xilinx-core/recipes-xrt/xrt/xrt.inc b/meta-xilinx-core/recipes-xrt/xrt/xrt.inc
new file mode 100644
index 00000000..ccca9922
--- /dev/null
+++ b/meta-xilinx-core/recipes-xrt/xrt/xrt.inc
@@ -0,0 +1,10 @@
+REPO ?= "git://github.com/Xilinx/XRT.git;protocol=https"
+BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}"
+SRC_URI = "${REPO};${BRANCHARG}"
+
+BRANCH= "2021.2"
+SRCREV= "2719b6027e185000fc49783171631db03fc0ef79"
+PV = "202120.2.12.0"
+
+
+
diff --git a/meta-xilinx-core/recipes-xrt/xrt/xrt_git.bb b/meta-xilinx-core/recipes-xrt/xrt/xrt_git.bb
new file mode 100644
index 00000000..f73d3d2b
--- /dev/null
+++ b/meta-xilinx-core/recipes-xrt/xrt/xrt_git.bb
@@ -0,0 +1,50 @@
+SUMMARY  = "Xilinx Runtime(XRT) libraries"
+DESCRIPTION = "Xilinx Runtime User Space Libraries and headers"
+
+require xrt.inc
+
+LICENSE = "GPLv2 & Apache-2.0"
+LIC_FILES_CHKSUM = "file://../LICENSE;md5=da5408f748bce8a9851dac18e66f4bcf \
+                    file://runtime_src/core/edge/drm/zocl/LICENSE;md5=7d040f51aae6ac6208de74e88a3795f8 \
+                    file://runtime_src/core/pcie/driver/linux/xocl/LICENSE;md5=b234ee4d69f5fce4486a80fdaf4a4263 \
+                    file://runtime_src/core/pcie/linux/LICENSE;md5=3b83ef96387f14655fc854ddc3c6bd57 \
+                    file://runtime_src/core/pcie/tools/xbutil/LICENSE;md5=d273d63619c9aeaf15cdaf76422c4f87 \
+                    file://runtime_src/core/edge/tools/xbutil/LICENSE;md5=d273d63619c9aeaf15cdaf76422c4f87 "
+
+S = "${WORKDIR}/git/src"
+
+inherit cmake
+
+BBCLASSEXTEND = "native nativesdk"
+
+# util-linux is for libuuid-dev.
+DEPENDS = "libdrm opencl-headers ocl-icd opencl-clhpp boost util-linux git-replacement-native protobuf-native protobuf elfutils libffi"
+RDEPENDS:${PN} = "bash ocl-icd boost-system boost-filesystem zocl"
+
+EXTRA_OECMAKE += " \
+                -DCMAKE_BUILD_TYPE=Release \
+                -DCMAKE_EXPORT_COMPILE_COMANDS=ON \
+                "
+
+PACKAGE_ARCH:versal-ai-core = "${SOC_VARIANT_ARCH}"
+EXTRA_OECMAKE:append:versal-ai-core += "-DXRT_AIE_BUILD=true"
+TARGET_CXXFLAGS:append:versal-ai-core += "-DXRT_ENABLE_AIE"
+DEPENDS:append:versal-ai-core += " libmetal libxaiengine aiefal"
+RDEPENDS:${PN}:append:versal-ai-core += " libxaiengine aiefal"
+
+FILES_SOLIBSDEV = ""
+FILES:${PN} += "\
+    ${libdir}/lib*.so \
+    ${libdir}/lib*.so.* \
+    /lib/*.so* "
+INSANE_SKIP:${PN} += "dev-so"
+
+pkg_postinst_ontarget:${PN}() {
+  #!/bin/sh
+  if [ ! -e /etc/OpenCL/vendors/xilinx.icd ]; then
+        echo "INFO: Creating ICD entry for Xilinx Platform"
+        mkdir -p /etc/OpenCL/vendors
+        echo "libxilinxopencl.so" > /etc/OpenCL/vendors/xilinx.icd
+        chmod -R 755 /etc/OpenCL
+  fi
+}
diff --git a/meta-xilinx-core/recipes-xrt/zocl/zocl_git.bb b/meta-xilinx-core/recipes-xrt/zocl/zocl_git.bb
new file mode 100644
index 00000000..40578aa2
--- /dev/null
+++ b/meta-xilinx-core/recipes-xrt/zocl/zocl_git.bb
@@ -0,0 +1,20 @@
+SUMMARY  = "Xilinx Runtime(XRT) driver module"
+DESCRIPTION = "Xilinx Runtime driver module provides memory management and compute unit schedule"
+
+
+require recipes-xrt/xrt/xrt.inc
+
+LIC_FILES_CHKSUM = "file://LICENSE;md5=7d040f51aae6ac6208de74e88a3795f8"
+LICENSE = "GPLv2 & Apache-2.0"
+
+S = "${WORKDIR}/git/src/runtime_src/core/edge/drm/zocl"
+
+inherit module
+
+pkg_postinst_ontarget:${PN}() {
+  #!/bin/sh
+  echo "Unloading old XRT Linux kernel modules"
+  ( rmmod zocl || true ) > /dev/null 2>&1
+  echo "Loading new XRT Linux kernel modules"
+  modprobe zocl
+}