diff options
| author | Sivaprasad Addepalli <sivaprasad.addepalli@xilinx.com> | 2024-09-03 06:09:16 +0530 |
|---|---|---|
| committer | Siva Addepalli <sivaprasad.addepalli@xilinx.com> | 2024-09-03 17:07:12 +0530 |
| commit | 95a777ac271f09c86a0ef89363501cd6cb7dc0e2 (patch) | |
| tree | 14707a8e694ae6618f66e249e824909dd96376bd /meta-xilinx-core | |
| parent | c29214b9f00732da2dda223607f1a8d78163d66b (diff) | |
| download | meta-xilinx-95a777ac271f09c86a0ef89363501cd6cb7dc0e2.tar.gz | |
qemu : Updated SRCREV for 2024.2_9347
hcd-dwc3: Correct default number of maximum slots
xlnx-versal-ddrmc-ub: Add fields related to DDRMC5C
xlnx-versal-pmc-int: Add axi slave switch resets
Diffstat (limited to 'meta-xilinx-core')
| -rw-r--r-- | meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-8.1.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-8.1.inc b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-8.1.inc index 7150fe9e..12b9196b 100644 --- a/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-8.1.inc +++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-xilinx-8.1.inc | |||
| @@ -9,7 +9,7 @@ COMPATIBLE_HOST:arm = "null" | |||
| 9 | QEMU_TARGETS = "aarch64 arm microblaze microblazeel riscv32 x86_64" | 9 | QEMU_TARGETS = "aarch64 arm microblaze microblazeel riscv32 x86_64" |
| 10 | 10 | ||
| 11 | BRANCH = "master" | 11 | BRANCH = "master" |
| 12 | SRCREV = "7109e93cf729b5d15c3f712317f2528e4aee6da7" | 12 | SRCREV = "6c4d937e2c2c6fcc1518f6074fa768c186e0b002" |
| 13 | 13 | ||
| 14 | LIC_FILES_CHKSUM = "file://COPYING;md5=441c28d2cf86e15a37fa47e15a72fbac \ | 14 | LIC_FILES_CHKSUM = "file://COPYING;md5=441c28d2cf86e15a37fa47e15a72fbac \ |
| 15 | file://COPYING.LIB;endline=24;md5=8c5efda6cf1e1b03dcfd0e6c0d271c7f" | 15 | file://COPYING.LIB;endline=24;md5=8c5efda6cf1e1b03dcfd0e6c0d271c7f" |