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authorMark Hatle <mark.hatle@amd.com>2024-08-24 13:46:52 -0600
committerMark Hatle <mark.hatle@amd.com>2024-08-27 11:23:38 -0500
commitf3844c8cc0647b8033f6ffb0822a6533c81b8b15 (patch)
tree13a736ddc251e0cfb9fa1e79f8551fd63f5dbb55 /meta-xilinx-core/recipes-devtools/qemu
parent3d0dc636cce43bf50d48cddae98a974e0ffa719b (diff)
downloadmeta-xilinx-f3844c8cc0647b8033f6ffb0822a6533c81b8b15.tar.gz
qemu-devicetrees: Add alternative vck190 config
Reorder the serial ports for an alternative vck190 machine. This puts the Linux (APU) serial ports first in the processing order which will help enable Yocto Project testimage support. Signed-off-by: Mark Hatle <mark.hatle@amd.com>
Diffstat (limited to 'meta-xilinx-core/recipes-devtools/qemu')
-rw-r--r--meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees.inc2
-rw-r--r--meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees/0001-versal-Reorder-serial-ports.patch1466
2 files changed, 1468 insertions, 0 deletions
diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees.inc b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees.inc
index 3e56e349..e98f483b 100644
--- a/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees.inc
+++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees.inc
@@ -14,6 +14,8 @@ REPO ?= "git://github.com/Xilinx/qemu-devicetrees.git;protocol=https"
14BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" 14BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}"
15SRC_URI = "${REPO};${BRANCHARG}" 15SRC_URI = "${REPO};${BRANCHARG}"
16 16
17SRC_URI += "file://0001-versal-Reorder-serial-ports.patch"
18
17S = "${WORKDIR}/git" 19S = "${WORKDIR}/git"
18 20
19# Don't need to do anything 21# Don't need to do anything
diff --git a/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees/0001-versal-Reorder-serial-ports.patch b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees/0001-versal-Reorder-serial-ports.patch
new file mode 100644
index 00000000..23ed3659
--- /dev/null
+++ b/meta-xilinx-core/recipes-devtools/qemu/qemu-devicetrees/0001-versal-Reorder-serial-ports.patch
@@ -0,0 +1,1466 @@
1From 2da2588a1dda1fd7fd2f6fc89db13cc5694d793e Mon Sep 17 00:00:00 2001
2From: Mark Hatle <mark.hatle@amd.com>
3Date: Sat, 24 Aug 2024 11:23:18 -0600
4Subject: [PATCH] versal: Reorder serial ports
5
6This change affects the order of the serial ports when calling qemu.
7Previously the serial ports 0 & 1 were the PMC (firmware) uartlite,
8while the standard serial pors were 2 & 3. Reverse this order to
9ensure that the first two serial ports are the ones used by Linux.
10
11Signed-off-by: Mark Hatle <mark.hatle@amd.com>
12---
13 board-versal-pmc-virt-alt.dts | 230 ++++++++++++++++
14 board-versal-ps-vck190-alt.dts | 58 ++++
15 board-versal-ps-virt-alt.dts | 354 +++++++++++++++++++++++++
16 versal-pmc-alt.dtsi | 40 +++
17 versal-pmc-ppu-alt.dtsi | 252 ++++++++++++++++++
18 versal-ps-iou-alt.dtsi | 467 +++++++++++++++++++++++++++++++++
19 6 files changed, 1401 insertions(+)
20 create mode 100644 board-versal-pmc-virt-alt.dts
21 create mode 100644 board-versal-ps-vck190-alt.dts
22 create mode 100644 board-versal-ps-virt-alt.dts
23 create mode 100644 versal-pmc-alt.dtsi
24 create mode 100644 versal-pmc-ppu-alt.dtsi
25 create mode 100644 versal-ps-iou-alt.dtsi
26
27diff --git a/board-versal-pmc-virt-alt.dts b/board-versal-pmc-virt-alt.dts
28new file mode 100644
29index 00000000..52d23c83
30--- /dev/null
31+++ b/board-versal-pmc-virt-alt.dts
32@@ -0,0 +1,230 @@
33+/*
34+ * Versal Virtual PMC board device tree
35+ *
36+ * Copyright (c) 2016, Xilinx Inc
37+ * All rights reserved.
38+ *
39+ * Redistribution and use in source and binary forms, with or without
40+ * modification, are permitted provided that the following conditions are met:
41+ * * Redistributions of source code must retain the above copyright
42+ * notice, this list of conditions and the following disclaimer.
43+ * * Redistributions in binary form must reproduce the above copyright
44+ * notice, this list of conditions and the following disclaimer in the
45+ * documentation and/or other materials provided with the distribution.
46+ * * Neither the name of the <organization> nor the
47+ * names of its contributors may be used to endorse or promote products
48+ * derived from this software without specific prior written permission.
49+ *
50+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
51+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
52+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
53+ * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
54+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
55+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
56+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
57+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
58+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
59+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
60+ */
61+
62+/dts-v1/;
63+
64+#ifndef VERSAL_NPI_OVERRIDE
65+ #include "versal-npi-memmap.dtsh"
66+#endif
67+
68+#define VERSAL_NPI_GENERIC
69+
70+#include "versal.dtsh"
71+
72+#ifndef MULTI_ARCH
73+#include "versal-pmc-alt.dtsi"
74+#include "versal-psm.dtsi"
75+#include "versal-ddrmc.dtsi"
76+#include "versal-ps-iou-alt.dtsi"
77+#include "versal-pmc-ppu-cpus.dtsi"
78+#include "versal-psm-cpu.dtsi"
79+
80+/ {
81+ /* FIXME: Once we add the NOC, these should be attached to it. */
82+ MEM_REGION(ddr, 0x0, MM_TOP_DDR, 0x00000000, MM_TOP_DDR_SIZE, &ddr_mem) // 2 GB
83+ MEM_SPEC(ddr_2, MM_TOP_DDR_2_H, MM_TOP_DDR_2_L, MM_TOP_DDR_2,
84+ MM_TOP_DDR_2_SIZE_H, MM_TOP_DDR_2_SIZE_L, &ddr_2_mem) // 32 GB
85+
86+ /* Dummy APUs. */
87+ cpu0: apu@0 {
88+ };
89+ cpu1: apu@1 {
90+ };
91+ rpu_cpu0: rpu_cpu0 {
92+ };
93+ rpu_cpu1: rpu_cpu1 {
94+ };
95+#ifndef HAVE_DDRMC_CPUS
96+ ddrmc_ub0: ddrmc_ub@0 {
97+ #interrupt-cells = <1>;
98+ interrupt-controller;
99+ };
100+ ddrmc_ub1: ddrmc_ub@1 {
101+ #interrupt-cells = <1>;
102+ interrupt-controller;
103+ };
104+#endif
105+ /* Dummy GIC. */
106+ gic: apu_gic@0 {
107+ #interrupt-cells = <3>;
108+ interrupt-controller;
109+ };
110+};
111+
112+&pmc_qspi_0 {
113+ SPI_FLASH(qspi_flash_lcs_lb,"m25qu02gcbb", 0x02000000, 0x0 0x0)
114+ SPI_FLASH(qspi_flash_lcs_ub,"m25qu02gcbb", 0x02000000, 0x2 0x1)
115+ SPI_FLASH(qspi_flash_ucs_lb,"m25qu02gcbb", 0x02000000, 0x1 0x0)
116+ SPI_FLASH(qspi_flash_ucs_ub,"m25qu02gcbb", 0x02000000, 0x3 0x1)
117+};
118+
119+&ospi {
120+ SPI_FLASH(ospi_flash_lcs_lb, "mt35xu01gbba", 0x02000000, 0x0 0x0)
121+ SPI_FLASH(ospi_flash_lcs_ub, "mt35xu01gbba", 0x02000000, 0x1 0x0)
122+ SPI_FLASH(ospi_flash_ucs_lb, "mt35xu01gbba", 0x02000000, 0x2 0x0)
123+ SPI_FLASH(ospi_flash_ucs_ub, "mt35xu01gbba", 0x02000000, 0x3 0x0)
124+};
125+
126+#else
127+#include "versal-icnt.dtsi"
128+#include "versal-rams.dtsi"
129+#include "versal-pmc-ppu-cpus.dtsi"
130+#include "versal-psm-cpu.dtsi"
131+
132+/ {
133+ /* FIXME: Once we add the NOC, these should be attached to it. */
134+ MEM_REGION(ddr, 0x0, 0x00000000, 0x00000000, 0x80000000, &ddr_mem)
135+
136+ ps_pmc_rp: ps_pmc_rp@0 {
137+ doc-name = "Remote-port PMC-PS";
138+ compatible = "remote-port";
139+ chrdev-id = "ps-pmc-rp";
140+ };
141+ rp_pmc_ppu0: rp_pmc_ppu0@0 {
142+ compatible = "remote-port-gpio";
143+ remote-ports = <&ps_pmc_rp 1>;
144+ interrupts-extended = < &pmc_ppu0 0 >;
145+ };
146+ rp_pmc_ppu1: rp_pmc_ppu1@0 {
147+ compatible = "remote-port-gpio";
148+ remote-ports = <&ps_pmc_rp 2>;
149+ interrupts-extended = < &pmc_ppu1 0 >;
150+ };
151+ pmc_global: rp_pmc_global@0 {
152+ compatible = "remote-port-gpio";
153+ remote-ports = <&ps_pmc_rp 3>;
154+ #gpio-cells = <1>;
155+ num-gpios = <16>;
156+ };
157+ lmb_pmc_ppu0: lmb_pmc_ppu0@0 {
158+ rp_lmb_pmc_ppu0@0 {
159+ compatible = "remote-port-memory-master";
160+ remote-ports = <&ps_pmc_rp 4>;
161+ reg = < 0x0 0x0 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF /* -1 */ >;
162+ };
163+ };
164+ lmb_pmc_ppu1: lmb_pmc_ppu1@0 {
165+ rp_lmb_pmc_ppu1@0 {
166+ compatible = "remote-port-memory-master";
167+ remote-ports = <&ps_pmc_rp 5>;
168+ reg = < 0x0 0x0 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF /* -1 */ >;
169+ };
170+ };
171+ crl: crl@MM_CRL {
172+ compatible = "remote-port-gpio";
173+ remote-ports = <&ps_pmc_rp 6>;
174+ #gpio-cells = <1>;
175+ num-gpios = <35>;
176+ };
177+ pmc_clk_rst: pmc_clk_rst@0 {
178+ compatible = "remote-port-gpio";
179+ remote-ports = <&ps_pmc_rp 7>;
180+ #gpio-cells = <1>;
181+ num-gpios = <30>;
182+ };
183+ rp_psm0: rp_psm0@0 {
184+ compatible = "remote-port-gpio";
185+ remote-ports = <&ps_pmc_rp 8>;
186+ interrupts-extended = < &psm0 0 >;
187+ };
188+#ifdef MM_NPI_DDRMC_MAIN_0
189+ rp_ddrmc_ub0: rp_ddrmc_ub@0 {
190+ compatible = "remote-port-gpio";
191+ remote-ports = <&ps_pmc_rp 9>;
192+# ifdef HAVE_DDRMC_CPUS
193+ interrupts-extended = < &ddrmc_ub0 0 >;
194+# endif
195+ };
196+
197+ npi_ddrmc_ub0: rp_npi_ddrmc_ub@0 {
198+ compatible = "remote-port-gpio";
199+ remote-ports = <&ps_pmc_rp 11>;
200+ #gpio-cells = <1>;
201+ };
202+#endif
203+#ifdef MM_NPI_DDRMC_MAIN_1
204+ rp_ddrmc_ub1: rp_ddrmc_ub@1 {
205+ compatible = "remote-port-gpio";
206+ remote-ports = <&ps_pmc_rp 10>;
207+ # ifdef HAVE_DDRMC_CPUS
208+ interrupts-extended = < &ddrmc_ub1 0 >;
209+ # endif
210+ };
211+
212+ npi_ddrmc_ub1: rp_npi_ddrmc_ub@1 {
213+ compatible = "remote-port-gpio";
214+ remote-ports = <&ps_pmc_rp 12>;
215+ #gpio-cells = <1>;
216+ };
217+#endif
218+ lmb_psm: lmb_psm@0 {
219+ rp_lmb_psm@0 {
220+ compatible = "remote-port-memory-master";
221+ remote-ports = <&ps_pmc_rp 13>;
222+ reg = < 0x0 0x0 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF /* -1 */ >;
223+ };
224+ };
225+
226+ /* Dummy stub to avoid ifdefs in the interrupt-map. */
227+ pmc_gic_proxy: pmc_gic_proxy {
228+ doc-ignore = <1>;
229+ #interrupt-cells = <3>;
230+ interrupt-controller;
231+ };
232+ psm_gic_proxy: psm_gic_proxy {
233+ doc-ignore = <1>;
234+ #interrupt-cells = <3>;
235+ interrupt-controller;
236+ };
237+ psm0_io_intc: psm0_io_intc {
238+ doc-ignore = <1>;
239+ #interrupt-cells = <1>;
240+ interrupt-controller;
241+ };
242+ pmc_ppu1_io_intc: pmc_ppu1_io_intc {
243+ doc-ignore = <1>;
244+ #interrupt-cells = <1>;
245+ interrupt-controller;
246+ };
247+};
248+#endif
249+
250+/ {
251+ /*
252+ * FIXME: This legacy hook will reset the entire PMC instance
253+ * meaning PSM and PMC MicroBlazes for multi-arch and all
254+ * devices for single-arch.
255+ * Once the CPU reset infrastructure is improved, we should
256+ * remove this.
257+ */
258+ pmc_reset: pmc_reset@ {
259+ compatible = "qemu,reset-device";
260+ gpios = <&pmc_clk_rst CRP_RST_PS_PMC_SRST>;
261+ };
262+};
263diff --git a/board-versal-ps-vck190-alt.dts b/board-versal-ps-vck190-alt.dts
264new file mode 100644
265index 00000000..b61d3d5c
266--- /dev/null
267+++ b/board-versal-ps-vck190-alt.dts
268@@ -0,0 +1,58 @@
269+/*
270+ * Versal Virtual vck190 board device tree
271+ *
272+ * Copyright (c) 2020, Xilinx Inc
273+ * All rights reserved.
274+ *
275+ * Redistribution and use in source and binary forms, with or without
276+ * modification, are permitted provided that the following conditions are met:
277+ * * Redistributions of source code must retain the above copyright
278+ * notice, this list of conditions and the following disclaimer.
279+ * * Redistributions in binary form must reproduce the above copyright
280+ * notice, this list of conditions and the following disclaimer in the
281+ * documentation and/or other materials provided with the distribution.
282+ * * Neither the name of the <organization> nor the
283+ * names of its contributors may be used to endorse or promote products
284+ * derived from this software without specific prior written permission.
285+ *
286+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
287+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
288+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
289+ * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
290+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
291+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
292+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
293+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
294+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
295+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
296+ */
297+#include "board-versal-ps-virt-alt.dts"
298+#include "versal-silicon-freq.dtsi"
299+
300+/{
301+ MEM_REGION64(ddr_3, MM_TOP_DDR_CH1_H, MM_TOP_DDR_CH1_L, MM_TOP_DDR_CH1,
302+ 0x2, 0x0, &ddr_3_mem) // 8 GB
303+};
304+
305+&ps_i2c1 {
306+ i2cswitch@74 {
307+ #address-cells = <1>;
308+ #size-cells = <0>;
309+ compatible = "nxp,pca9548";
310+ reg = <0x74>;
311+ chip-enable = <0x1>;
312+ i2c@0 {
313+ #address-cells = <1>;
314+ #size-cells = <0>;
315+ reg = <0>;
316+ eeprom@54 {
317+ compatible = "at,24c08";
318+ reg = <0x54>;
319+ };
320+ };
321+ };
322+};
323+
324+&ospi_flash_lcs_lb {
325+ compatible = "mt35xu02gbba";
326+};
327diff --git a/board-versal-ps-virt-alt.dts b/board-versal-ps-virt-alt.dts
328new file mode 100644
329index 00000000..7585d196
330--- /dev/null
331+++ b/board-versal-ps-virt-alt.dts
332@@ -0,0 +1,354 @@
333+/*
334+ * Versal Virtual PS board device tree
335+ *
336+ * Copyright (c) 2016-2022, Xilinx Inc.
337+ * Copyright (C) 2022-2024, Advanced Micro Devices, Inc.
338+ * All rights reserved.
339+ *
340+ * Redistribution and use in source and binary forms, with or without
341+ * modification, are permitted provided that the following conditions are met:
342+ * * Redistributions of source code must retain the above copyright
343+ * notice, this list of conditions and the following disclaimer.
344+ * * Redistributions in binary form must reproduce the above copyright
345+ * notice, this list of conditions and the following disclaimer in the
346+ * documentation and/or other materials provided with the distribution.
347+ * * Neither the name of the <organization> nor the
348+ * names of its contributors may be used to endorse or promote products
349+ * derived from this software without specific prior written permission.
350+ *
351+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
352+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
353+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
354+ * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
355+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
356+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
357+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
358+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
359+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
360+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
361+ */
362+#ifndef __BOARD_VERSAL_PS_VIRT__
363+#define __BOARD_VERSAL_PS_VIRT__
364+
365+/dts-v1/;
366+#ifndef VERSAL_NPI_OVERRIDE
367+ #include "versal-npi-memmap.dtsh"
368+#endif
369+
370+#ifndef NUM_APUS
371+/* Base platform has 2 APUs. */
372+#define NUM_APUS 2
373+#endif
374+
375+#define HAS_SMMU
376+#define HAVE_APU_GIC
377+
378+#ifndef RPU_GIC_INTERRUPT_TARGET_STEM
379+#ifdef MULTI_ARCH
380+ #define RPU_GIC_INTERRUPT_TARGET_STEM rpu_intc_redirect_
381+#else
382+ #define RPU_GIC_INTERRUPT_TARGET_STEM rpu_cpu
383+#endif
384+#endif
385+
386+#define VERSAL_NPI_GENERIC
387+
388+#include "versal.dtsh"
389+
390+#include "versal-pmc.dtsi"
391+#include "versal-psm.dtsi"
392+#include "versal-ddrmc.dtsi"
393+#ifdef VERSAL_PSX
394+#include "versal-psx-apu.dtsi"
395+#else
396+#include "versal-ps-apu.dtsi"
397+#include "versal-ps-rpu.dtsi"
398+#include "versal-boot-init.dtsi"
399+#endif
400+#include "versal-ps-iou-alt.dtsi"
401+#include "versal-virtio-mmio.dtsi"
402+#include "versal-boot-init.dtsi"
403+#include "versal-gty.dtsi"
404+#include "versal-silicon-freq.dtsi"
405+
406+/ {
407+#ifdef MULTI_ARCH
408+ ps_pmc_rp: ps_pmc_rp@0 {
409+ doc-status = "complete";
410+ doc-name = "Remote-port PMC";
411+ doc-subdtb = "board-versal-pmc-virt.dtb";
412+ compatible = "remote-port";
413+ chrdev-id = "ps-pmc-rp";
414+ };
415+ pmc_ppu0: rp_pmc_ppu0@0 {
416+ compatible = "remote-port-gpio";
417+ remote-ports = <&ps_pmc_rp 1>;
418+ #interrupt-cells = <1>;
419+ interrupt-controller;
420+ };
421+ pmc_ppu1: rp_pmc_ppu1@0 {
422+ compatible = "remote-port-gpio";
423+ remote-ports = <&ps_pmc_rp 2>;
424+ #interrupt-cells = <1>;
425+ interrupt-controller;
426+ };
427+ rp_pmc_global: rp_pmc_global@0 {
428+ compatible = "remote-port-gpio";
429+ remote-ports = <&ps_pmc_rp 3>;
430+ gpio-controller;
431+ #gpio-cells = <1>;
432+ num-gpios = <16>;
433+
434+ /* We only need to proxy GPIO 1 and 2 (PPU1 RST and WAKE). */
435+ gpios = < &dummy1 0
436+ &pmc_global 1
437+ &pmc_global 2 >;
438+ };
439+ rp_lmb_pmc_ppu0: rp_lmb_pmc_ppu0@0 {
440+ compatible = "remote-port-memory-slave";
441+ remote-ports = <&ps_pmc_rp 4>;
442+ mr = <&lmb_pmc_ppu0>;
443+ };
444+ rp_lmb_pmc_ppu1: rp_lmb_pmc_ppu1@0 {
445+ compatible = "remote-port-memory-slave";
446+ remote-ports = <&ps_pmc_rp 5>;
447+ mr = <&lmb_pmc_ppu1>;
448+ };
449+ rp_crl: rp_crl@0 {
450+ compatible = "remote-port-gpio";
451+ remote-ports = <&ps_pmc_rp 6>;
452+ gpio-controller;
453+ #gpio-cells = <1>;
454+ num-gpios = <35>;
455+
456+ gpios = <
457+ &crl 0
458+ &crl 1
459+ &crl 2
460+ &crl 3
461+ &crl 4
462+ &crl 5
463+ &crl 6
464+ &crl 7
465+ &crl 8
466+ &crl 9
467+ &crl 10
468+ &crl 11
469+ &crl 12
470+ &crl 13
471+ &crl 14
472+ &crl 15
473+ &crl 16
474+ &crl 17
475+ &crl 18
476+ &crl 19
477+ &crl 20
478+ &crl 21
479+ &crl 22
480+ &crl 23
481+ &crl 24
482+ &crl 25
483+ &crl 26
484+ &crl 27
485+ &crl 28
486+ &crl 29
487+ &crl 30
488+ &crl 31
489+ &dummy1 0
490+ &dummy1 0
491+ &crl 34 >;
492+ };
493+ rp_pmc_clk_rst: rp_pmc_clk_rst@0 {
494+ compatible = "remote-port-gpio";
495+ remote-ports = <&ps_pmc_rp 7>;
496+ gpio-controller;
497+ #gpio-cells = <1>;
498+ num-gpios = <30>;
499+
500+ gpios = < &pmc_clk_rst 0 &pmc_clk_rst 1
501+ &pmc_clk_rst 2 &pmc_clk_rst 3
502+ &pmc_clk_rst 4 &pmc_clk_rst 5
503+ &pmc_clk_rst 6 &pmc_clk_rst 7
504+ &pmc_clk_rst 8 &pmc_clk_rst 9
505+ &pmc_clk_rst 10 &pmc_clk_rst 11
506+ &pmc_clk_rst 12 &pmc_clk_rst 13
507+ &pmc_clk_rst 14 &pmc_clk_rst 15
508+ &pmc_clk_rst 16 &pmc_clk_rst 17
509+ &pmc_clk_rst 18 &pmc_clk_rst 19
510+ &pmc_clk_rst 20 &pmc_clk_rst 21
511+ &pmc_clk_rst 22 &pmc_clk_rst 23
512+ &pmc_clk_rst 24 &pmc_clk_rst 25
513+ &pmc_clk_rst 26 &pmc_clk_rst 27
514+ &pmc_clk_rst 28 &pmc_clk_rst 29
515+ >;
516+ };
517+ psm0: rp_psm0@0 {
518+ compatible = "remote-port-gpio";
519+ remote-ports = <&ps_pmc_rp 8>;
520+ #interrupt-cells = <1>;
521+ interrupt-controller;
522+ };
523+#ifdef MM_NPI_DDRMC_MAIN_0
524+ ddrmc_ub0: rp_ddrmc@0 {
525+ compatible = "remote-port-gpio";
526+ remote-ports = <&ps_pmc_rp 9>;
527+ #interrupt-cells = <1>;
528+ interrupt-controller;
529+ };
530+ rp_npi_ddrmc_ub0: rp_npi_ddrmc_ub@0 {
531+ compatible = "remote-port-gpio";
532+ remote-ports = <&ps_pmc_rp 11>;
533+ gpios = < &npi_ddrmc_ub0 0 >;
534+ };
535+#endif
536+#ifdef MM_NPI_DDRMC_MAIN_1
537+ ddrmc_ub1: rp_ddrmc@1 {
538+ compatible = "remote-port-gpio";
539+ remote-ports = <&ps_pmc_rp 10>;
540+ #interrupt-cells = <1>;
541+ interrupt-controller;
542+ };
543+ rp_npi_ddrmc_ub1: rp_npi_ddrmc_ub@1 {
544+ compatible = "remote-port-gpio";
545+ remote-ports = <&ps_pmc_rp 12>;
546+ gpios = < &npi_ddrmc_ub1 0 >;
547+ };
548+#endif
549+ rp_lmb_psm: rp_lmb_psm@0 {
550+ compatible = "remote-port-memory-slave";
551+ remote-ports = <&ps_pmc_rp 13>;
552+ mr = <&lmb_psm>;
553+ };
554+
555+#define RPU_INTC_REDIRECT(NCPU, PSMOUT, RPUN) \
556+glue(rpu_intc_redirect_, NCPU): glue(rpu_intc_redirect, NCPU)@NCPU { \
557+ #interrupt-cells = <1>; \
558+ compatible = "xlnx,zynqmp-intc-redirect"; \
559+ interrupt-controller; \
560+ interrupts-extended = <glue(&rpu_cpu,NCPU) 0>; \
561+ gpios = <&psm_global PSMOUT &rpu_ctrl RPUN>; \
562+};
563+
564+ amba_rpu: amba_rpu@0 {
565+ RPU_INTC_REDIRECT(0, 4, 6)
566+ RPU_INTC_REDIRECT(1, 5, 7)
567+ };
568+
569+#else
570+ /* Single ARCH PS board has no PPU MicroBlazes. */
571+ pmc_ppu0: dummy_ppu0@0 {
572+ #interrupt-cells = <1>;
573+ };
574+ pmc_ppu1: dummy_ppu1@0 {
575+ #interrupt-cells = <1>;
576+ };
577+ psm0: dummy_ppu0@0 {
578+ #interrupt-cells = <1>;
579+ };
580+ ddrmc_ub0: dummy_ddrmc0@0 {
581+ #interrupt-cells = <1>;
582+ };
583+ ddrmc_ub1: dummy_ddrmc1@0 {
584+ #interrupt-cells = <1>;
585+ };
586+#endif
587+
588+ /* FIXME: Once we add the NOC, these should be attached to it. */
589+ MEM_REGION(ddr, 0x0, MM_TOP_DDR, 0x00000000, MM_TOP_DDR_SIZE, &ddr_mem) // 2 GB
590+ MEM_SPEC(ddr_2, MM_TOP_DDR_2_H, MM_TOP_DDR_2_L, MM_TOP_DDR_2,
591+ MM_TOP_DDR_2_SIZE_H, MM_TOP_DDR_2_SIZE_L, &ddr_2_mem) // 32 GB
592+ mdio0: mdio {
593+ #address-cells = <1>;
594+ #size-cells = <0>;
595+ #priority-cells = <0>;
596+ compatible="mdio";
597+ phy0: phy@1 {
598+ compatible = "dp83867";
599+ device_type = "ethernet-phy";
600+ reg = <1>;
601+ };
602+ phy1: phy@2 {
603+ compatible = "88e1118r";
604+ device_type = "ethernet-phy";
605+ reg = <2>;
606+ };
607+ };
608+};
609+
610+/*
611+ * One flash for each SPI-master to match prebuilt system.dtb in BSP
612+ * xilinx-versal-virt-2019.1
613+ */
614+#define BDEV_SPI_FLASH(_NAME, _COMPAT, _SIZEM, _REGVAL) \
615+_NAME: _NAME@0 { \
616+ #address-cells = <1>; \
617+ #size-cells = <1>; \
618+ #priority-cells = <0>; \
619+ #bus-cells = <1>; \
620+ compatible = _COMPAT, "st,m25p80"; \
621+ spi-max-frequency = <50000000>; \
622+ reg = <_REGVAL>; \
623+ blockdev-node-name = #_NAME; \
624+ _NAME@0x00000000 { \
625+ label = #_NAME; \
626+ reg = <0x00000000 _SIZEM>; \
627+ }; \
628+};
629+
630+&spi0 {
631+ BDEV_SPI_FLASH(spi0_flash0, "m25p80", 0x00100000, 0x0 0x0)
632+};
633+
634+&spi1 {
635+ BDEV_SPI_FLASH(spi1_flash0, "m25p80", 0x00100000, 0x0 0x0)
636+};
637+
638+/*
639+ * Use 2Gbit QSPI flashes to allow verification of Image-searching
640+ * in ROM upto 256MB.
641+ */
642+#define DI_SPI_FLASH(_DI, _NAME, _COMPAT, _SIZEM, _REGVAL) \
643+_NAME: _NAME@0 { \
644+ #address-cells = <1>; \
645+ #size-cells = <1>; \
646+ #priority-cells = <0>; \
647+ #bus-cells = <1>; \
648+ compatible = _COMPAT, "st,m25p80"; \
649+ spi-max-frequency = <50000000>; \
650+ reg = <_REGVAL>; \
651+ drive-index = <_DI>; \
652+ _NAME@0x00000000 { \
653+ label = #_NAME; \
654+ reg = <0x00000000 _SIZEM>; \
655+ }; \
656+};
657+
658+&pmc_qspi_0 {
659+ DI_SPI_FLASH(0, qspi_flash_lcs_lb, "m25qu02gcbb", 0x02000000, 0x0 0x0)
660+ DI_SPI_FLASH(1, qspi_flash_lcs_ub, "m25qu02gcbb", 0x02000000, 0x2 0x1)
661+ DI_SPI_FLASH(2, qspi_flash_ucs_lb, "m25qu02gcbb", 0x02000000, 0x1 0x0)
662+ DI_SPI_FLASH(3, qspi_flash_ucs_ub, "m25qu02gcbb", 0x02000000, 0x3 0x1)
663+};
664+
665+&ospi {
666+ DI_SPI_FLASH(4, ospi_flash_lcs_lb, "mt35xu01gbba", 0x02000000, 0x0 0x0)
667+ DI_SPI_FLASH(5, ospi_flash_lcs_ub, "mt35xu01gbba", 0x02000000, 0x1 0x0)
668+ DI_SPI_FLASH(6, ospi_flash_ucs_lb, "mt35xu01gbba", 0x02000000, 0x2 0x0)
669+ DI_SPI_FLASH(7, ospi_flash_ucs_ub, "mt35xu01gbba", 0x02000000, 0x3 0x0)
670+};
671+
672+&gem0 {
673+ mdio = <&mdio0>;
674+};
675+
676+&gem1 {
677+ mdio = <&mdio0>;
678+};
679+
680+&pmc_tap {
681+ /*
682+ * Default device: xcvc1902
683+ */
684+ idcode = <0x14CA8093>;
685+};
686+#endif
687diff --git a/versal-pmc-alt.dtsi b/versal-pmc-alt.dtsi
688new file mode 100644
689index 00000000..8236911b
690--- /dev/null
691+++ b/versal-pmc-alt.dtsi
692@@ -0,0 +1,40 @@
693+/*
694+ * Versal PMC
695+ *
696+ * Copyright (c) 2016, Xilinx Inc.
697+ * All rights reserved.
698+ *
699+ * Redistribution and use in source and binary forms, with or without
700+ * modification, are permitted provided that the following conditions are met:
701+ * * Redistributions of source code must retain the above copyright
702+ * notice, this list of conditions and the following disclaimer.
703+ * * Redistributions in binary form must reproduce the above copyright
704+ * notice, this list of conditions and the following disclaimer in the
705+ * documentation and/or other materials provided with the distribution.
706+ * * Neither the name of the <organization> nor the
707+ * names of its contributors may be used to endorse or promote products
708+ * derived from this software without specific prior written permission.
709+ *
710+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
711+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
712+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
713+ * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
714+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
715+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
716+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
717+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
718+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
719+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
720+ */
721+
722+#include "versal.dtsh"
723+
724+#include "versal-icnt.dtsi"
725+#include "versal-rams.dtsi"
726+#include "versal-pmc-ppu-alt.dtsi"
727+#include "versal-pmc-iou.dtsi"
728+#include "versal-pmc-sys.dtsi"
729+#include "versal-pmc-sec.dtsi"
730+#include "versal-pmc-npi.dtsi"
731+#include "versal-pmc-pl.dtsi"
732+#include "versal-pmc-bat.dtsi"
733diff --git a/versal-pmc-ppu-alt.dtsi b/versal-pmc-ppu-alt.dtsi
734new file mode 100644
735index 00000000..726413f4
736--- /dev/null
737+++ b/versal-pmc-ppu-alt.dtsi
738@@ -0,0 +1,252 @@
739+/*
740+ * Versal PMC PPU block
741+ *
742+ * Copyright (c) 2016, Xilinx Inc.
743+ * All rights reserved.
744+ *
745+ * Redistribution and use in source and binary forms, with or without
746+ * modification, are permitted provided that the following conditions are met:
747+ * * Redistributions of source code must retain the above copyright
748+ * notice, this list of conditions and the following disclaimer.
749+ * * Redistributions in binary form must reproduce the above copyright
750+ * notice, this list of conditions and the following disclaimer in the
751+ * documentation and/or other materials provided with the distribution.
752+ * * Neither the name of the <organization> nor the
753+ * names of its contributors may be used to endorse or promote products
754+ * derived from this software without specific prior written permission.
755+ *
756+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
757+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
758+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
759+ * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
760+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
761+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
762+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
763+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
764+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
765+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
766+ */
767+
768+#include "versal.dtsh"
769+
770+#define CREATE_PPU_IOMOD(X) \
771+ pmc_ppu ## X ## _io_module: io-module@00 { \
772+ doc-status = "complete"; \
773+ #address-cells = <2>; \
774+ #size-cells = <1>; \
775+ #priority-cells = <0>; \
776+ compatible = "xlnx,iomodule-1.02.a", "syscon", "simple-bus"; \
777+ container = <&lmb_pmc_ppu ## X>; \
778+ priority = <0xffffffff>; \
779+ xlnx,freq = <0x47868c0>; \
780+ xlnx,instance = "iomodule_1"; \
781+ xlnx,io-mask = <0xfffe0000>; \
782+ xlnx,lmb-awidth = <0x20>; \
783+ xlnx,lmb-dwidth = <0x20>; \
784+ xlnx,mask = <0xffffff80>; \
785+ xlnx,use-io-bus = <0x1>; \
786+ \
787+ pmc_ppu ## X ## _io_intc: pmc_ppu ## X ## _intc@0C { \
788+ #interrupt-cells = <1>; \
789+ compatible = "xlnx,io-intc-1.02.a", "xlnx,io_intc"; \
790+ interrupt-controller ; \
791+ interrupts-extended = <&pmc_ppu ## X 0>; \
792+ reg = <0x0 MM_PMC_PPU ## X ## _IOM(0C) 0x4 0x0 MM_PMC_PPU ## X ## _IOM(30) 0x10 0x0 MM_PMC_PPU ## X ## _IOM(80) 0x7C>; \
793+ xlnx,intc-addr-width = <0x20>; \
794+ xlnx,intc-base-vectors = <0x0>; \
795+ xlnx,intc-has-fast = <0x0>; \
796+ xlnx,intc-intr-size = <0x10>; \
797+ xlnx,intc-level-edge = <0x0>; \
798+ xlnx,intc-positive = <0xffff>; \
799+ xlnx,intc-use-ext-intr = <0x1>; \
800+ }; \
801+ \
802+ pmc_ppu ## X ## _io_gpi1: pmc_ppu ## X ## _gpi@20 { \
803+ #gpio-cells = <1>; \
804+ gpio-controller; \
805+ compatible = "xlnx,io-gpi-1.02.a", "xlnx,io_gpi"; \
806+ interrupt-parent = <&pmc_ppu ## X ## _io_intc>; \
807+ interrupts = <11>; \
808+ reg = <0x0 MM_PMC_PPU ## X ## _IOM(20) 0x4>; \
809+ xlnx,gpi-interrupt = <0x1>; \
810+ xlnx,gpi-size = <0x20>; \
811+ xlnx,use-gpi = <0x1>; \
812+ }; \
813+ pmc_ppu ## X ## _io_gpi2: pmc_ppu ## X ## _gpi@24 { \
814+ #gpio-cells = <1>; \
815+ gpio-controller; \
816+ compatible = "xlnx,io-gpi-1.02.a", "xlnx,io_gpi"; \
817+ interrupt-parent = <&pmc_ppu ## X ## _io_intc>; \
818+ interrupts = <12>; \
819+ reg = <0x0 MM_PMC_PPU ## X ## _IOM(24) 0x4>; \
820+ xlnx,gpi-interrupt = <0x1>; \
821+ xlnx,gpi-size = <0x20>; \
822+ xlnx,use-gpi = <0x1>; \
823+ }; \
824+ pmc_ppu ## X ## _io_gpi3: pmc_ppu ## X ## _gpi@28 { \
825+ #gpio-cells = <1>; \
826+ gpio-controller; \
827+ compatible = "xlnx,io-gpi-1.02.a", "xlnx,io_gpi"; \
828+ interrupt-parent = <&pmc_ppu ## X ## _io_intc>; \
829+ interrupts = <13>; \
830+ reg = <0x0 MM_PMC_PPU ## X ## _IOM(28) 0x4>; \
831+ xlnx,gpi-interrupt = <0x1>; \
832+ xlnx,gpi-size = <0x20>; \
833+ xlnx,use-gpi = <0x1>; \
834+ }; \
835+ pmc_ppu ## X ## _io_gpi4: pmc_ppu ## X ## _gpi@2c { \
836+ #gpio-cells = <1>; \
837+ gpio-controller; \
838+ compatible = "xlnx,io-gpi-1.02.a", "xlnx,io_gpi"; \
839+ interrupt-parent = <&pmc_ppu ## X ## _io_intc>; \
840+ interrupts = <14>; \
841+ reg = <0x0 MM_PMC_PPU ## X ## _IOM(2c) 0x4>; \
842+ xlnx,gpi-interrupt = <0x1>; \
843+ xlnx,gpi-size = <0x20>; \
844+ xlnx,use-gpi = <0x1>; \
845+ }; \
846+ \
847+ pmc_ppu ## X ## _io_gpo1: pmc_ppu ## X ## _gpo@10 { \
848+ #gpio-cells = <1>; \
849+ gpio-controller; \
850+ compatible = "xlnx,io-gpo-1.02.a", "xlnx,io_gpo"; \
851+ reg = <0x0 MM_PMC_PPU ## X ## _IOM(10) 0x4>; \
852+ xlnx,gpo-init = <0x0>; \
853+ xlnx,gpo-size = <0x9>; \
854+ xlnx,use-gpo = <0x1>; \
855+ }; \
856+ pmc_ppu ## X ## _io_gpo2: pmc_ppu ## X ## _gpo@14 { \
857+ #gpio-cells = <1>; \
858+ gpio-controller; \
859+ compatible = "xlnx,io-gpo-1.02.a", "xlnx,io_gpo"; \
860+ reg = <0x0 MM_PMC_PPU ## X ## _IOM(14) 0x4>; \
861+ xlnx,gpo-init = <0x0>; \
862+ xlnx,gpo-size = <0x20>; \
863+ xlnx,use-gpo = <0x1>; \
864+ }; \
865+ pmc_ppu ## X ## _io_gpo3: pmc_ppu ## X ## _gpo@18 { \
866+ #gpio-cells = <1>; \
867+ gpio-controller; \
868+ compatible = "xlnx,io-gpo-1.02.a", "xlnx,io_gpo"; \
869+ reg = <0x0 MM_PMC_PPU ## X ## _IOM(18) 0x4>; \
870+ xlnx,gpo-init = <0x0>; \
871+ xlnx,gpo-size = <0x20>; \
872+ xlnx,use-gpo = <0x1>; \
873+ }; \
874+ pmc_ppu ## X ## _io_gpo4: pmc_ppu ## X ## _gpo@1c { \
875+ #gpio-cells = <1>; \
876+ gpio-controller; \
877+ compatible = "xlnx,io-gpo-1.02.a", "xlnx,io_gpo"; \
878+ reg = <0x0 MM_PMC_PPU ## X ## _IOM(1c) 0x4>; \
879+ xlnx,gpo-init = <0x0>; \
880+ xlnx,gpo-size = <0x20>; \
881+ xlnx,use-gpo = <0x1>; \
882+ }; \
883+ \
884+ pmc_ppu ## X ## _io_pit1: pmc_ppu ## X ## _pit@40 { \
885+ compatible = "xlnx,io-pit-1.02.a", "xlnx,io_pit"; \
886+ interrupt-parent = <&pmc_ppu ## X ## _io_intc>; \
887+ interrupts = <3>; \
888+ reg = <0x0 MM_PMC_PPU ## X ## _IOM(40) 0xc>; \
889+ xlnx,pit-interrupt = <0x1>; \
890+ xlnx,pit-prescaler = <0x9>; \
891+ xlnx,pit-readable = <0x1>; \
892+ xlnx,pit-size = <0x20>; \
893+ xlnx,use-pit = <0x1>; \
894+ frequency = <460000000>; \
895+ gpios = <&pmc_ppu ## X ## _io_gpo1 1 &pmc_ppu ## X ## _io_pit2 0>; \
896+ gpio-names = "ps_config","ps_hit_in"; \
897+ gpio-controller; \
898+ #gpio-cells = <1>; \
899+ }; \
900+ pmc_ppu ## X ## _io_pit2: pmc_ppu ## X ## _pit@50 { \
901+ compatible = "xlnx,io-pit-1.02.a", "xlnx,io_pit"; \
902+ interrupt-parent = <&pmc_ppu ## X ## _io_intc>; \
903+ interrupts = <4>; \
904+ reg = <0x0 MM_PMC_PPU ## X ## _IOM(50) 0xc>; \
905+ xlnx,pit-interrupt = <0x1>; \
906+ xlnx,pit-prescaler = <0x9>; \
907+ xlnx,pit-readable = <0x1>; \
908+ xlnx,pit-size = <0x20>; \
909+ xlnx,use-pit = <0x1>; \
910+ frequency = <460000000>; \
911+ gpio-controller; \
912+ #gpio-cells = <1>; \
913+ }; \
914+ pmc_ppu ## X ## _io_pit3: pmc_ppu ## X ## _pit@60 { \
915+ compatible = "xlnx,io-pit-1.02.a", "xlnx,io_pit"; \
916+ interrupt-parent = <&pmc_ppu ## X ## _io_intc>; \
917+ interrupts = <5>; \
918+ reg = <0x0 MM_PMC_PPU ## X ## _IOM(60) 0xc>; \
919+ xlnx,pit-interrupt = <0x1>; \
920+ xlnx,pit-prescaler = <0x9>; \
921+ xlnx,pit-readable = <0x1>; \
922+ xlnx,pit-size = <0x20>; \
923+ xlnx,use-pit = <0x1>; \
924+ frequency = <460000000>; \
925+ gpios = <&pmc_ppu ## X ## _io_gpo1 6 &pmc_ppu ## X ## _io_pit4 0>; \
926+ gpio-names = "ps_config","ps_hit_in"; \
927+ gpio-controller; \
928+ #gpio-cells = <1>; \
929+ }; \
930+ pmc_ppu ## X ## _io_pit4: pmc_ppu ## X ## _pit@70 { \
931+ compatible = "xlnx,io-pit-1.02.a", "xlnx,io_pit"; \
932+ interrupt-parent = <&pmc_ppu ## X ## _io_intc>; \
933+ interrupts = <6>; \
934+ reg = <0x0 MM_PMC_PPU ## X ## _IOM(70) 0xc>; \
935+ xlnx,pit-interrupt = <0x1>; \
936+ xlnx,pit-prescaler = <0x9>; \
937+ xlnx,pit-readable = <0x1>; \
938+ xlnx,pit-size = <0x20>; \
939+ xlnx,use-pit = <0x1>; \
940+ frequency = <460000000>; \
941+ gpio-controller; \
942+ #gpio-cells = <1>; \
943+ }; \
944+ }
945+
946+/ {
947+ /* MDM UARTs. We put them here for instantiation ordering purposes
948+ * making sure that -serial command line options refer to these
949+ * first.
950+ */
951+ ppu0_mdm_uart@MM_PMC_PPU0_MDM_HSD {
952+ doc-status = "complete";
953+ compatible = "xlnx,xps-uartlite";
954+ reg-extended = <&lmb_pmc_ppu0 0x0 MM_PMC_PPU0_MDM_HSD 0x0 0x10 0x1>;
955+ chardev = "serial2";
956+ };
957+
958+ ppu1_mdm_uart@MM_PMC_PPU1_MDM_HSD {
959+ doc-status = "complete";
960+ compatible = "xlnx,xps-uartlite";
961+ reg-extended = <&lmb_pmc_ppu1 0x0 MM_PMC_PPU1_MDM_HSD 0x0 0x10 0x1>;
962+ chardev = "serial3";
963+ };
964+};
965+
966+&lmb_pmc_ppu0 {
967+ doc-name = "LMB PPU0";
968+ doc-status = "complete";
969+ CREATE_PPU_IOMOD(0);
970+};
971+
972+&lmb_pmc_ppu1 {
973+ doc-name = "LMB PPU1";
974+ doc-status = "complete";
975+ CREATE_PPU_IOMOD(1);
976+};
977+
978+&amba_pmc_ppu {
979+ pmc_gic_proxy: pmc_gic_proxy@0 {
980+ doc-status = "complete";
981+ #interrupt-cells = <3>;
982+ interrupt-controller;
983+
984+ compatible = "xlnx,zynqmp-gicp";
985+ reg = <0x0 MM_PMC_GIC_PROXY 0x0 MM_PMC_GIC_PROXY_SIZE 0x0>;
986+ interrupt-parent = <&pmc_ppu1_io_intc>;
987+ interrupts = <IRQ_PPU1_INTC_PMC_GICP>;
988+ };
989+};
990+
991diff --git a/versal-ps-iou-alt.dtsi b/versal-ps-iou-alt.dtsi
992new file mode 100644
993index 00000000..a6c22b86
994--- /dev/null
995+++ b/versal-ps-iou-alt.dtsi
996@@ -0,0 +1,467 @@
997+/*
998+ * Versal PS IOU
999+ *
1000+ * Copyright (C) 2016-2022, Xilinx, Inc.
1001+ * Copyright (C) 2023, Advanced Micro Devices, Inc.
1002+ * All rights reserved.
1003+ *
1004+ * Redistribution and use in source and binary forms, with or without
1005+ * modification, are permitted provided that the following conditions are met:
1006+ * * Redistributions of source code must retain the above copyright
1007+ * notice, this list of conditions and the following disclaimer.
1008+ * * Redistributions in binary form must reproduce the above copyright
1009+ * notice, this list of conditions and the following disclaimer in the
1010+ * documentation and/or other materials provided with the distribution.
1011+ * * Neither the name of the <organization> nor the
1012+ * names of its contributors may be used to endorse or promote products
1013+ * derived from this software without specific prior written permission.
1014+ *
1015+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
1016+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
1017+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
1018+ * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
1019+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
1020+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
1021+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
1022+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1023+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
1024+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1025+ */
1026+
1027+#include "versal.dtsh"
1028+
1029+#define GEM(g_name, g_base, g_size, g_dma, g_irq, rst_idx, pwr_idx) \
1030+g_name: ethernet@g_base { \
1031+ #address-cells = <1>; \
1032+ #size-cells = <0>; \
1033+ #priority-cells = <0>; \
1034+ compatible = "cdns,gem"; \
1035+ interrupts = <g_irq g_irq>; \
1036+ dma = <g_dma>; \
1037+ memattr = <& ## g_name ## _memattr_smid>; \
1038+ memattr-write = <& ## g_name ## _w_memattr_smid>; \
1039+ reg = <0x0 g_base 0x0 g_size 0x0>; \
1040+ num-priority-queues = <2>; \
1041+ reset-gpios = <&crl rst_idx>; \
1042+ power-gpios = <&psm_local pwr_idx>; \
1043+}
1044+
1045+// FIXME: Add support for SMIDs
1046+#define ZDMA_CHANNEL(zname, zdomain, zbase, zirq, zbuswidth, zdma, mid, num) \
1047+zname ## _mattr: zname ## mattr { \
1048+ compatible = "qemu:memory-transaction-attr"; \
1049+ requester-id = <mid>; \
1050+}; \
1051+ \
1052+zname: dma-controller@zbase { \
1053+ compatible = "xlnx,zdma"; \
1054+ reg = <0x0 zbase 0x0 MM_ADMA_CH0_SIZE 0x0>; \
1055+ bus-width = <zbuswidth>; \
1056+ has-parity = <1>; \
1057+ interrupts = <zirq>; \
1058+ #stream-id-cells = <0x1>; \
1059+ dma = <zdma>; \
1060+ memattr = <& ## zname ## _mattr>; \
1061+ reset-gpios = < &crl CRL_RST_ADMA >; \
1062+ #gpio-cells = <1>; \
1063+ gpio-names = "memattr-secure"; \
1064+ gpios = <&lpd_slcr_secure num>; \
1065+}
1066+
1067+/*
1068+ * Our XRAM model only has the correctable interrupt line.
1069+ * All instances connect to a single line in the GIC.
1070+ *
1071+ * To support shared memories for co-sim, we provide the
1072+ * actual RAMs externally and not from the XRAMC model.
1073+ */
1074+#define XRAM_CTRL(n) xram_ctrl_ ## n { \
1075+ compatible = "xlnx,versal-xramc"; \
1076+ reg = <0x0 (MM_XRAM + 0x## n ##0000) 0 0x10000 0x0 >; \
1077+ interrupts = <XRAM_IRQ_0>; \
1078+ alloc-ram = <0>; \
1079+}
1080+
1081+&amba_fpd {
1082+#ifdef MM_FPD_FPD_APU
1083+ apu_ctrl: apu_ctrl@MM_FPD_FPD_APU {
1084+ compatible = "xlnx,versal-apu-ctrl";
1085+ reg = <0x0 MM_FPD_FPD_APU 0x0 MM_FPD_FPD_APU_SIZE 0x0>;
1086+ cpu0 = <&cpu0>;
1087+ cpu1 = <&cpu1>;
1088+ #gpio-cells = <1>;
1089+ };
1090+#endif
1091+
1092+ afi_fm@MM_FPD_FPD_AFIFM0 {
1093+ compatible = "xlnx,versal-afi-fm";
1094+ reg = <0x0 MM_FPD_FPD_AFIFM0 0x0 MM_FPD_FPD_AFIFM0_SIZE 0x0>;
1095+ };
1096+
1097+ afi_fm@MM_FPD_FPD_AFIFM2 {
1098+ compatible = "xlnx,versal-afi-fm";
1099+ reg = <0x0 MM_FPD_FPD_AFIFM2 0x0 MM_FPD_FPD_AFIFM2_SIZE 0x0>;
1100+ };
1101+
1102+#ifdef MM_FPD_FPD_GPCCI
1103+ cci_reg@MM_FPD_FPD_GPCCI {
1104+ compatible = "xlnx,cci_reg";
1105+ reg = <0x0 MM_FPD_FPD_GPCCI 0x0 MM_FPD_FPD_MAINCCI_SIZE 0x0>;
1106+ };
1107+#endif
1108+
1109+#ifdef MM_FPD_FPD_MAINCCI
1110+ cci500@MM_FPD_FPD_MAINCCI {
1111+ compatible = "xlnx,cci500";
1112+ reg = <0x0 MM_FPD_FPD_MAINCCI 0x0 MM_FPD_FPD_MAINCCI_SIZE 0x0>;
1113+ };
1114+#endif
1115+
1116+ cpm_crcpm@MM_CPM_CPM_CRCPM {
1117+ compatible = "xlnx,versal_cpm_crcpm";
1118+ reg = <0x0 MM_CPM_CPM_CRCPM 0x0 MM_CPM_CPM_CRCPM_SIZE 0x0>;
1119+ };
1120+
1121+ cpm_pcsr@MM_CPM_CPM_PCSR {
1122+ compatible = "xlnx,versal_cpm_pcsr";
1123+ reg = <0x0 MM_CPM_CPM_PCSR 0x0 MM_CPM_CPM_PCSR_SIZE 0x0>;
1124+ };
1125+
1126+ cpm_slcr_secure@MM_CPM_CPM_SLCR_SECURE {
1127+ compatible = "xlnx.cpm_slcr_secure";
1128+ reg = <0x0 MM_CPM_CPM_SLCR_SECURE 0x0 MM_CPM_CPM_SLCR_SECURE_SIZE 0x0>;
1129+ };
1130+
1131+ fpd_slcr@MM_FPD_FPD_SLCR {
1132+ compatible = "xlnx,versal-fpd-slcr";
1133+ interrupts = <SLCR_FPD_APB_IRQ_0>;
1134+ reg = <0x0 MM_FPD_FPD_SLCR 0x0 MM_FPD_FPD_SLCR_SIZE 0x0>;
1135+ };
1136+
1137+ fpd_slcr_secure@MM_FPD_FPD_SLCR {
1138+ compatible = "xlnx,versal-fpd-slcr-secure";
1139+ interrupts = <SLCR_SECURE_FPD_APB_IRQ_0>;
1140+ reg = <0x0 MM_FPD_FPD_SLCR_SECURE 0x0 MM_FPD_FPD_SLCR_SECURE_SIZE 0x0>;
1141+ };
1142+
1143+#ifdef MM_FPD_FPD_WWDT
1144+ wwdt0: watchdog@MM_FPD_FPD_WWDT {
1145+ compatible = "xlnx,versal-wwdt";
1146+ reg = <0x0 MM_FPD_FPD_WWDT 0x0 MM_FPD_FPD_WWDT_SIZE 0x0>;
1147+ /* IRQ order must match the QEMU model */
1148+ interrupts = <FP_WDT_IRQ_0
1149+ FPD_WWDT_RST_PENDING_IRQ_0
1150+ FPD_GWDT_WS0_IRQ_0
1151+ FPD_GWDT_WS1_IRQ_0>;
1152+ pclk = <100000000>;
1153+ reset-gpios = <&crf 27>;
1154+ };
1155+#endif
1156+#ifdef MM_FPD_INTFPD_CONFIG
1157+ intfpd: intfpd@MM_FPD_INTFPD_CONFIG {
1158+ compatible = "xlnx-intfpd-config";
1159+ reg = <0x0 MM_FPD_INTFPD_CONFIG 0x0 MM_FPD_INTFPD_CONFIG_SIZE 0x0>;
1160+ interrupts = <
1161+ #if FPD_APB_INT_IRQ_0
1162+ FPD_APB_INT_IRQ_0
1163+ #elif INT_FPD_IRQ_0
1164+ INT_FPD_IRQ_0
1165+ #endif
1166+ >;
1167+ };
1168+#endif
1169+};
1170+
1171+&amba_lpd {
1172+ GEM(gem0, MM_GEM0, MM_GEM0_SIZE, &smmu_tbu0, GEM0_IRQ_0, CRL_RST_GEM0, PLR_PWR_GEM0);
1173+ GEM(gem1, MM_GEM1, MM_GEM1_SIZE, &smmu_tbu0, GEM1_IRQ_0, CRL_RST_GEM1, PLR_PWR_GEM1);
1174+
1175+ serial0: serial@MM_UART0 {
1176+ compatible = "pl011";
1177+ interrupts = <UART0_IRQ_0>;
1178+ reg = <0x0 MM_UART0 0x0 MM_UART0_SIZE 0x0 >;
1179+ reset-gpios = < &crl CRL_RST_UART0 >;
1180+ chardev = "serial0";
1181+ };
1182+ serial1: serial@MM_UART1 {
1183+ compatible = "pl011";
1184+ interrupts = <UART1_IRQ_0>;
1185+ reg = <0x0 MM_UART1 0x0 MM_UART1_SIZE 0x0 >;
1186+ reset-gpios = < &crl CRL_RST_UART1 >;
1187+ chardev = "serial1";
1188+ };
1189+
1190+ canfdbus0: canfdbus@0 {
1191+ compatible = "can-bus";
1192+ };
1193+
1194+ can0: can@MM_CANFD0 {
1195+ compatible = "xlnx,versal-canfd";
1196+ rx-fifo0 = <0x40>;
1197+ rx-fifo1 = <0x40>;
1198+ enable-rx-fifo1 = <0x1>;
1199+ canfdbus = <&canfdbus0>;
1200+ interrupts = <CAN0_IRQ_0>;
1201+ reg = <0x0 MM_CANFD0 0x0 MM_CANFD0_SIZE 0x0>;
1202+ reset-gpios = <&crl CRL_RST_CAN0>;
1203+ };
1204+ can1: can@MM_CANFD1 {
1205+ compatible = "xlnx,versal-canfd";
1206+ rx-fifo0 = <0x40>;
1207+ rx-fifo1 = <0x40>;
1208+ enable-rx-fifo1 = <0x1>;
1209+ canfdbus = <&canfdbus0>;
1210+ interrupts = <CAN1_IRQ_0>;
1211+ reg = <0x0 MM_CANFD1 0x0 MM_CANFD1_SIZE 0x0>;
1212+ reset-gpios = <&crl CRL_RST_CAN1>;
1213+ };
1214+
1215+ crl: crl@MM_CRL {
1216+ compatible = "xlnx,versal-crl";
1217+ reg = <0x0 MM_CRL 0x0 MM_CRL_SIZE 0x0>;
1218+ gpio-controller;
1219+ #gpio-cells = <1>;
1220+ };
1221+
1222+ lpd_iou_slcr: slcr@MM_LPD_IOU_SLCR {
1223+ compatible = "xlnx,versal-lpd-iou-slcr";
1224+ reg = <0x0 MM_LPD_IOU_SLCR 0x0 MM_LPD_IOU_SLCR_SIZE 0x0>;
1225+ };
1226+
1227+#ifdef MM_RPU
1228+ rpu_ctrl: rpu_ctrl@MM_RPU {
1229+ compatible = "xlnx,versal-rpu";
1230+ reg-extended = <&amba_lpd 0x0 MM_RPU 0x0 MM_RPU_SIZE 0x0
1231+ &amba_r5_0 0x0 0x0 0x0 0x80000 0x0
1232+ &amba 0x0 MM_R5_0_ATCM 0x0 0x60000 0x0
1233+ &amba_r5_1 0x0 0x0 0x0 0x80000 0x0
1234+ &amba 0x0 0xFFE90000 0x0 0x50000 0x0>;
1235+ rpu0 = <&rpu_cpu0>;
1236+ rpu1 = <&rpu_cpu1>;
1237+
1238+ gpio-controller;
1239+ #gpio-cells = <1>;
1240+
1241+ gpios = < &crl CRL_RST_CPU_R5_0 &crl CRL_RST_CPU_R5_1
1242+ &psm_local 42 &psm_local 43
1243+ >;
1244+ };
1245+#endif
1246+
1247+ ipi: ipi@MM_IPI {
1248+ compatible = "xlnx,versal-ipi";
1249+ reg = <0x0 MM_IPI 0x0 MM_IPI_SIZE 0x0>;
1250+
1251+ /* Interrupt ordering here needs to match
1252+ * QEMU's sysbus-irq output order. */
1253+ interrupts = <IPI_PSM_IRQ_0
1254+ IPI_PMC_IRQ_0
1255+ IPI0_IRQ_0 IPI1_IRQ_0
1256+ IPI2_IRQ_0 IPI3_IRQ_0
1257+ IPI4_IRQ_0 IPI5_IRQ_0
1258+ IPI6_IRQ_0
1259+ IPI_PMC_NOBUF_IRQ_0
1260+ IPI_APB_IRQ_0>;
1261+ reset-gpios = <&crl CRL_RST_IPI>;
1262+ };
1263+
1264+ spi0: spi@MM_SPI0 {
1265+ compatible = "cdns,spi-r1p6";
1266+ interrupts = <SPI0_IRQ_0>;
1267+ num-ss-bits = <4>;
1268+ reg = <0x0 MM_SPI0 0x0 MM_SPI0_SIZE 0x0 >;
1269+
1270+ #address-cells = <1>; /* For child; must match SPI_FLASH() */
1271+ #size-cells = <0>;
1272+ #bus-cells = <1>;
1273+ reset-gpios = <&crl CRL_RST_SPI0>;
1274+ };
1275+ spi1: spi@MM_SPI1 {
1276+ compatible = "cdns,spi-r1p6";
1277+ interrupts = <SPI1_IRQ_0>;
1278+ num-ss-bits = <4>;
1279+ reg = <0x0 MM_SPI1 0x0 MM_SPI1_SIZE 0x0 >;
1280+
1281+ #address-cells = <1>; /* For child; must match SPI_FLASH() */
1282+ #size-cells = <0>;
1283+ #bus-cells = <1>;
1284+ reset-gpios = <&crl CRL_RST_SPI1>;
1285+ };
1286+
1287+ dwc3_0: usb2@USB2_0_XHCI {
1288+ compatible = "usb_dwc3";
1289+ reg = <0x0 MM_USB_DWC3_0 0x0 MM_USB_DWC3_0_SIZE 0x0 0x0 MM_USB_XHCI 0x0 MM_USB_XHCI_SIZE 0x0>;
1290+ interrupts = <USB2_IRQ_0 USB2_IRQ_1 USB2_IRQ_2 USB2_IRQ_3>;
1291+ dma = <&smmu_tbu0>;
1292+ memattr = <&usb0_memattr>;
1293+ reset-gpios = <&crl CRL_RST_USB0>;
1294+ intrs = <4>;
1295+ slots = <2>;
1296+ };
1297+
1298+ ttc0: timer@MM_TTC0 {
1299+ compatible = "xlnx,ps7-ttc-1.00.a";
1300+ interrupts = <TTC0_IRQ_0 TTC0_IRQ_1 TTC0_IRQ_2>;
1301+ reg = <0x0 MM_TTC0 0x0 MM_TTC0_SIZE 0x0>;
1302+ width = <32>;
1303+ reset-gpios = < &crl CRL_RST_TTC0 >;
1304+ };
1305+ ttc1: timer@MM_TTC1 {
1306+ compatible = "xlnx,ps7-ttc-1.00.a";
1307+ interrupts = <TTC1_IRQ_0 TTC1_IRQ_1 TTC1_IRQ_2>;
1308+ reg = <0x0 MM_TTC1 0x0 MM_TTC1_SIZE 0x0>;
1309+ width = <32>;
1310+ reset-gpios = < &crl CRL_RST_TTC1 >;
1311+ };
1312+ ttc2: timer@MM_TTC2 {
1313+ compatible = "xlnx,ps7-ttc-1.00.a";
1314+ interrupts = <TTC2_IRQ_0 TTC2_IRQ_1 TTC2_IRQ_2>;
1315+ reg = <0x0 MM_TTC2 0x0 MM_TTC2_SIZE 0x0>;
1316+ width = <32>;
1317+ reset-gpios = < &crl CRL_RST_TTC2 >;
1318+ };
1319+ ttc3: timer@MM_TTC3 {
1320+ compatible = "xlnx,ps7-ttc-1.00.a";
1321+ interrupts = <TTC3_IRQ_0 TTC3_IRQ_1 TTC3_IRQ_2>;
1322+ reg = <0x0 MM_TTC3 0x0 MM_TTC3_SIZE 0x0>;
1323+ width = <32>;
1324+ reset-gpios = < &crl CRL_RST_TTC3 >;
1325+ };
1326+
1327+ ZDMA_CHANNEL(adma0, adma, MM_ADMA_CH0, ADMA_IRQ_0, 128, &smmu_tbu0, SMID_DMA0_CH0, 0x0);
1328+ ZDMA_CHANNEL(adma1, adma, MM_ADMA_CH1, ADMA_IRQ_1, 128, &smmu_tbu0, SMID_DMA0_CH1, 0x1);
1329+ ZDMA_CHANNEL(adma2, adma, MM_ADMA_CH2, ADMA_IRQ_2, 128, &smmu_tbu0, SMID_DMA0_CH2, 0x2);
1330+ ZDMA_CHANNEL(adma3, adma, MM_ADMA_CH3, ADMA_IRQ_3, 128, &smmu_tbu0, SMID_DMA0_CH3, 0x3);
1331+ ZDMA_CHANNEL(adma4, adma, MM_ADMA_CH4, ADMA_IRQ_4, 128, &smmu_tbu0, SMID_DMA0_CH4, 0x4);
1332+ ZDMA_CHANNEL(adma5, adma, MM_ADMA_CH5, ADMA_IRQ_5, 128, &smmu_tbu0, SMID_DMA0_CH5, 0x5);
1333+ ZDMA_CHANNEL(adma6, adma, MM_ADMA_CH6, ADMA_IRQ_6, 128, &smmu_tbu0, SMID_DMA0_CH6, 0x6);
1334+ ZDMA_CHANNEL(adma7, adma, MM_ADMA_CH7, ADMA_IRQ_7, 128, &smmu_tbu0, SMID_DMA0_CH7, 0x7);
1335+
1336+ afi_fm@MM_LPD_AFIFM4 {
1337+ compatible = "xlnx,versal-afi-fm";
1338+ reg = <0x0 MM_LPD_AFIFM4 0x0 MM_LPD_AFIFM4_SIZE 0x0>;
1339+ };
1340+
1341+ lpd_i2c_wrapper {
1342+#ifdef MM_PS_I2C0
1343+ ps_i2c0: ps_i2c0@MM_PS_I2C0 {
1344+ #address-cells = <1>;
1345+ #size-cells = <0>;
1346+ compatible = "xlnx,ps7-i2c-1.00.a", "cdns,i2c-r1p10";
1347+ interrupts = <I2C0_IRQ_0>;
1348+ reg-extended = <&amba_lpd 0x0 MM_PS_I2C0 0x0 MM_PS_I2C0_SIZE 0x0>;
1349+ reset-gpios = <&crl CRL_RST_I2C0>;
1350+ };
1351+ ps_i2c1: ps_i2c0@MM_PS_I2C1 {
1352+ #address-cells = <1>;
1353+ #size-cells = <0>;
1354+ compatible = "xlnx,ps7-i2c-1.00.a", "cdns,i2c-r1p10";
1355+ interrupts = <I2C1_IRQ_0>;
1356+ reg-extended = <&amba_lpd 0x0 MM_PS_I2C1 0x0 MM_PS_I2C1_SIZE 0x0>;
1357+ reset-gpios = <&crl CRL_RST_I2C1>;
1358+ };
1359+#endif
1360+ };
1361+
1362+ ocm_ctrl0: ocm_ctrl@OCM {
1363+ compatible = "xlnx,zynqmp-ocmc";
1364+ interrupts = <OCMINTR_IRQ_0>;
1365+ memsize = <MM_OCM_MEM_SIZE>;
1366+ reg = <0x0 MM_OCM 0x0 MM_OCM_SIZE 0x0>;
1367+ reset-gpios = <&crl CRL_RST_OCM>;
1368+ };
1369+
1370+#ifdef MM_XRAM_SLCR
1371+ xram_slcr@MM_XRAM_SLCR {
1372+ compatible = "xlnx,xram_slcr";
1373+ reg = <0x0 MM_XRAM_SLCR 0x0 MM_XRAM_SLCR_SIZE 0x0>;
1374+ };
1375+#endif
1376+
1377+ lpd_slcr@MM_LPD_SLCR {
1378+ compatible = "xlnx,versal-lpd-slcr";
1379+ reg = <0x0 MM_LPD_SLCR 0x0 MM_LPD_SLCR_SIZE 0x0>;
1380+ };
1381+
1382+ lpd_slcr_secure: lpd_slcr_secure@MM_LPD_SLCR_SECURE {
1383+ compatible = "xlnx,versal-lpd-slcr-secure";
1384+ reg = <0x0 MM_LPD_SLCR_SECURE 0x0 MM_LPD_SLCR_SECURE_SIZE 0x0>;
1385+ gpio-controller;
1386+ #gpio-cells = <1>;
1387+ };
1388+
1389+ lpd_iou_slcr_secure: lpd_iou_slcr_secure@MM_LPD_IOU_SECURE_SLCR {
1390+ compatible = "xlnx,versal-lpd-iou-slcr-secure";
1391+ reg = <0x0 MM_LPD_IOU_SECURE_SLCR 0x0 MM_LPD_IOU_SECURE_SLCR_SIZE 0x0>;
1392+ memattr-gem0 = <&gem0_memattr_smid>;
1393+ memattr-write-gem0 = <&gem0_w_memattr_smid>;
1394+ memattr-gem1 = <&gem1_memattr_smid>;
1395+ memattr-write-gem1 = <&gem1_w_memattr_smid>;
1396+ };
1397+
1398+#ifdef MM_WWDT
1399+ lpd_wwdt: wwdt@MM_WWDT {
1400+ compatible = "xlnx,versal-wwdt";
1401+ reg = <0x0 MM_WWDT 0x0 MM_WWDT_SIZE 0x0>;
1402+ /* IRQ order must match the QEMU model */
1403+ interrupts = <WWDT_IRQ_0
1404+ WWDT_RST_PENDING_IRQ_0
1405+ GWDT_WS0_IRQ_0
1406+ GWDT_WS1_IRQ_0>;
1407+ pclk = <100000000>;
1408+ reset-gpios = <&crl CRL_RST_SWDT>;
1409+ };
1410+#endif
1411+
1412+ lpd_gpio: lpd_gpio@MM_PS_GPIO {
1413+ #gpio-cells = <1>;
1414+ compatible = "xlnx,zynqmp-gpio";
1415+ gpio-controller;
1416+ interrupts = <GPIO_IRQ_0>;
1417+ reg = <0x0 MM_PS_GPIO 0x0 MM_PS_GPIO_SIZE 0x0>;
1418+ reset-gpios = < &crl CRL_RST_GPIO >;
1419+ };
1420+#ifdef MM_INTLPD_CONFIG
1421+ intlpd: intlpd@MM_INTLPD_CONFIG {
1422+ compatible = "xlnx-intlpd-config";
1423+ reg = <0x0 MM_INTLPD_CONFIG 0x0 MM_INTLPD_CONFIG_SIZE 0x0>;
1424+ interrupts = <INT_LPD_IRQ_0>;
1425+ };
1426+#endif
1427+};
1428+
1429+&amba_xram {
1430+ XRAM_CTRL(0);
1431+ XRAM_CTRL(1);
1432+ XRAM_CTRL(2);
1433+ XRAM_CTRL(3);
1434+};
1435+
1436+&amba_root {
1437+ /* These devices need to be created before the CPUs. */
1438+ crf: crf@MM_FPD_CRF {
1439+ compatible = "xlnx,versal-crf";
1440+ reg-extended = <&amba_fpd 0x0 MM_FPD_CRF 0x0 MM_FPD_CRF_SIZE 0x0>;
1441+ gpio-controller;
1442+ #gpio-cells = <1>;
1443+ };
1444+};
1445+
1446+/ {
1447+ /* Reset domains. */
1448+ lpd_reset_domain@0 {
1449+ compatible = "qemu,reset-domain";
1450+ mr0 = <&amba_lpd>;
1451+ reset-gpios = < &pmc_clk_rst CRP_RST_PS_PS_SRST
1452+ &pmc_clk_rst CRP_RST_PS_PS_POR >;
1453+ };
1454+
1455+ fpd_reset_domain@0 {
1456+ compatible = "qemu,reset-domain";
1457+ mr0 = <&amba_fpd>;
1458+ reset-gpios = < &pmc_clk_rst CRP_RST_PS_PS_SRST
1459+ &pmc_clk_rst CRP_RST_PS_PS_POR
1460+ &crl CRL_RST_FPD_POR
1461+ &crl CRL_RST_FPD_SRST >;
1462+ };
1463+};
1464--
14652.34.1
1466
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2026-07-20 06:55:10 +0000