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| author | Sivaprasad Addepalli <sivaprasad.addepalli@xilinx.com> | 2023-12-19 15:37:05 +0530 |
|---|---|---|
| committer | Siva Addepalli <sivaprasad.addepalli@xilinx.com> | 2023-12-19 19:14:10 +0530 |
| commit | d465072da0fd2fd3e4525cf523030aa5b8300b75 (patch) | |
| tree | 651c67919defe34d99b0b9213e11f1b4aab3a728 /meta-xilinx-core/dynamic-layers | |
| parent | 57df831e4e7dbe8e5591676e1647609736a55436 (diff) | |
| download | meta-xilinx-d465072da0fd2fd3e4525cf523030aa5b8300b75.tar.gz | |
linux-xlnx : Updated SRCREV for 2024.1_8467
Revert "firmware: xilinx: add support for Versal NET"
arm64: xilinx: Do not use _ in DT node names
arm64: zynqmp: Comment all iommus entries
arm64: zynqmp: Add L2 cache nodes
arm64: zynqmp: Describe interrupts by using macros
arm64: zynqmp: Replace all xilinx.com emails by amd.com
arm64: xilinx: Use bootph-all instead of u-boot,dm-pre-reloc
fpga: zynqmp-fpga: Adds status interface
firmware: xilinx: Add pm api function for PL config reg readback
Revert "fpga: mgr: Update the status for fpga-manager"
Diffstat (limited to 'meta-xilinx-core/dynamic-layers')
0 files changed, 0 insertions, 0 deletions