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| author | Addepalli, Siva <siva.addepalli@amd.com> | 2023-08-15 12:45:37 +0530 |
|---|---|---|
| committer | Siva Addepalli <siva.addepalli@amd.com> | 2023-08-15 13:37:13 +0530 |
| commit | 615327fe45ce4c393b16cb040ed8451c557cfc5a (patch) | |
| tree | b21b4c1923553c9436e2abf7b70639ba6db4dc0d /meta-xilinx-bsp | |
| parent | c38486bcf2512f3f5f56c735b4fdd65324480059 (diff) | |
| download | meta-xilinx-615327fe45ce4c393b16cb040ed8451c557cfc5a.tar.gz | |
arm-trusted-firmware : Updated SRCREV for 2023.2_7919
fix(versal-net): make pmc ipi channel as secure
fix(versal): make pmc ipi channel as secure
fix(versal-net): add redundant call to avoid glitches
fix(versal-net): change flag to increase security
chore(zynqmp): remove unused configuration from TSP
fix(zynqmp): resolve runtime error in TSP
chore(xilinx): reorder headers in assembly files
chore(xilinx): correct kernel doc warnings for missing functions
fix(xilinx): add headers to resolve compile time issue
fix(xilinx): remove clock_setrate and clock_getrate api
feat(versal-net): ddr address reservation in dtb at runtime
feat(versal): ddr address reservation in dtb at runtime
Signed-off-by: Siva Addepalli <siva.addepalli@amd.com>
Diffstat (limited to 'meta-xilinx-bsp')
0 files changed, 0 insertions, 0 deletions