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authorNathan Rossi <nathan.rossi@xilinx.com>2013-05-23 11:31:26 +1000
committerNathan Rossi <nathan.rossi@xilinx.com>2013-05-23 11:31:26 +1000
commitc93171bbbba4b8698d710807c5f1810bd49855df (patch)
treed1c5fca0f5c63e8b418d150d09172e7e4c13c04d /meta-kc705
parent815fae9c1c27f4afc906ba08af368d6e520abb52 (diff)
downloadmeta-xilinx-c93171bbbba4b8698d710807c5f1810bd49855df.tar.gz
meta-kc705: kc705-trd: Update configuration to match exact hardware
* Update configuration files and DTS to match the exact Targeted Reference Design configuration. Signed-off-by: Nathan Rossi <nathan.rossi@xilinx.com>
Diffstat (limited to 'meta-kc705')
-rw-r--r--meta-kc705/conf/machine/kc705-trd.conf2
-rw-r--r--meta-kc705/recipes-bsp/u-boot/files/config.mk8
-rw-r--r--meta-kc705/recipes-bsp/u-boot/files/xparameters.h34
-rw-r--r--meta-kc705/recipes-kernel/linux/linux-xlnx/defconfig4
-rw-r--r--meta-kc705/recipes-kernel/linux/linux-xlnx/kc705-trd.dts367
5 files changed, 243 insertions, 172 deletions
diff --git a/meta-kc705/conf/machine/kc705-trd.conf b/meta-kc705/conf/machine/kc705-trd.conf
index 764ab339..8f6b031c 100644
--- a/meta-kc705/conf/machine/kc705-trd.conf
+++ b/meta-kc705/conf/machine/kc705-trd.conf
@@ -6,6 +6,6 @@ TARGET_CPU = "microblazeel"
6MACHINE_FEATURES := "" 6MACHINE_FEATURES := ""
7 7
8require conf/machine/include/tune-microblaze.inc 8require conf/machine/include/tune-microblaze.inc
9TUNE_FEATURES_tune-microblaze += "v8.30 little-endian barrel-shift pattern-compare divide-hard multiply-high" 9TUNE_FEATURES_tune-microblaze += "v8.50 little-endian barrel-shift pattern-compare reorder divide-hard multiply-low"
10 10
11SERIAL_CONSOLE = "115200 ttyS0" 11SERIAL_CONSOLE = "115200 ttyS0"
diff --git a/meta-kc705/recipes-bsp/u-boot/files/config.mk b/meta-kc705/recipes-bsp/u-boot/files/config.mk
index a47cd176..50dafe00 100644
--- a/meta-kc705/recipes-bsp/u-boot/files/config.mk
+++ b/meta-kc705/recipes-bsp/u-boot/files/config.mk
@@ -1,9 +1,9 @@
1PLATFORM_CPPFLAGS += -mxl-pattern-compare 1PLATFORM_CPPFLAGS += -mxl-pattern-compare
2PLATFORM_CPPFLAGS += -mxl-barrel-shift 2PLATFORM_CPPFLAGS += -mxl-barrel-shift
3PLATFORM_CPPFLAGS += -mno-xl-soft-div 3PLATFORM_CPPFLAGS += -mxl-soft-div
4PLATFORM_CPPFLAGS += -mxl-multiply-high 4PLATFORM_CPPFLAGS += -mno-xl-multiply-high
5PLATFORM_CPPFLAGS += -mno-xl-soft-mul 5PLATFORM_CPPFLAGS += -mno-xl-soft-mul
6PLATFORM_CPPFLAGS += -mcpu=v8.50.a 6PLATFORM_CPPFLAGS += -mcpu=v8.50.a
7 7
8TEXT_BASE = 0x87c00000 8TEXT_BASE = 0xbfc00000
9CONFIG_SYS_TEXT_BASE = 0x87c00000 9CONFIG_SYS_TEXT_BASE = 0xbfc00000
diff --git a/meta-kc705/recipes-bsp/u-boot/files/xparameters.h b/meta-kc705/recipes-bsp/u-boot/files/xparameters.h
index a308d412..994a26e6 100644
--- a/meta-kc705/recipes-bsp/u-boot/files/xparameters.h
+++ b/meta-kc705/recipes-bsp/u-boot/files/xparameters.h
@@ -4,15 +4,15 @@
4#define XILINX_FSL_NUMBER 0 4#define XILINX_FSL_NUMBER 0
5#define XILINX_USE_ICACHE 1 5#define XILINX_USE_ICACHE 1
6#define XILINX_USE_DCACHE 1 6#define XILINX_USE_DCACHE 1
7#define XILINX_DCACHE_BYTE_SIZE 16384 7#define XILINX_DCACHE_BYTE_SIZE 8192
8 8
9/* Interrupt controller is microblaze_0_intc */ 9/* Interrupt controller is interrupt_cntlr */
10#define XILINX_INTC_BASEADDR 0x41200000 10#define XILINX_INTC_BASEADDR 0x40100000
11#define XILINX_INTC_NUM_INTR_INPUTS 5 11#define XILINX_INTC_NUM_INTR_INPUTS 8
12 12
13/* Timer pheriphery is system_timer */ 13/* Timer pheriphery is dual_timer_counter */
14#define XILINX_TIMER_BASEADDR 0x41c00000 14#define XILINX_TIMER_BASEADDR 0x40300000
15#define XILINX_TIMER_IRQ 2 15#define XILINX_TIMER_IRQ 3
16 16
17/* System Timer Clock Frequency */ 17/* System Timer Clock Frequency */
18#define XILINX_CLOCK_FREQ 100000000 18#define XILINX_CLOCK_FREQ 100000000
@@ -21,26 +21,28 @@
21#define XILINX_UART16550 21#define XILINX_UART16550
22#define XILINX_UART16550_BASEADDR 0x40400000 22#define XILINX_UART16550_BASEADDR 0x40400000
23#define XILINX_UART16550_CLOCK_HZ 100000000 23#define XILINX_UART16550_CLOCK_HZ 100000000
24#define XILINX_UARTLITE_BASEADDR 0x41400000 24#define XILINX_UARTLITE_BASEADDR 0x40200000
25#define CONFIG_CONS_INDEX 1 25#define CONFIG_CONS_INDEX 1
26 26
27/* IIC doesn't exist */ 27/* IIC pheriphery is iic_eeprom */
28#define XILINX_IIC_0_BASEADDR 0x40a00000
29#define XILINX_IIC_0_FREQ 100000
30#define XILINX_IIC_0_BIT 0
28 31
29/* GPIO is dip_switches_8bits*/ 32/* GPIO doesn't exist */
30#define XILINX_GPIO_BASEADDR 0x40060000
31 33
32/* SDIO doesn't exist */ 34/* SDIO doesn't exist */
33 35
34/* Main Memory is ddr3_sdram */ 36/* Main Memory is ddr3_sdram */
35#define XILINX_RAM_START 0x80000000 37#define XILINX_RAM_START 0x80000000
36#define XILINX_RAM_SIZE 0x08000000 38#define XILINX_RAM_SIZE 0x40000000
37 39
38/* Flash Memory is linear_flash */ 40/* Flash Memory is linear_flash */
39#define XILINX_FLASH_START 0xa0000000 41#define XILINX_FLASH_START 0x48000000
40#define XILINX_FLASH_SIZE 0x08000000 42#define XILINX_FLASH_SIZE 0x08000000
41 43
42/* Sysace doesn't exist */ 44/* Sysace doesn't exist */
43 45
44/* Ethernet controller is ethernet */ 46/* Ethernet controller is soft_ethernet_mac */
45#define XILINX_AXIEMAC_BASEADDR 0x44f40000 47#define XILINX_AXIEMAC_BASEADDR 0x50100000
46#define XILINX_AXIDMA_BASEADDR 0x41e00000 48#define XILINX_AXIDMA_BASEADDR 0x50000000
diff --git a/meta-kc705/recipes-kernel/linux/linux-xlnx/defconfig b/meta-kc705/recipes-kernel/linux/linux-xlnx/defconfig
index 283955c5..630ff778 100644
--- a/meta-kc705/recipes-kernel/linux/linux-xlnx/defconfig
+++ b/meta-kc705/recipes-kernel/linux/linux-xlnx/defconfig
@@ -196,8 +196,8 @@ CONFIG_XILINX_MICROBLAZE0_FAMILY="kintex7"
196CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR=1 196CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR=1
197CONFIG_XILINX_MICROBLAZE0_USE_PCMP_INSTR=1 197CONFIG_XILINX_MICROBLAZE0_USE_PCMP_INSTR=1
198CONFIG_XILINX_MICROBLAZE0_USE_BARREL=1 198CONFIG_XILINX_MICROBLAZE0_USE_BARREL=1
199CONFIG_XILINX_MICROBLAZE0_USE_DIV=1 199CONFIG_XILINX_MICROBLAZE0_USE_DIV=0
200CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL=2 200CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL=1
201CONFIG_XILINX_MICROBLAZE0_USE_FPU=0 201CONFIG_XILINX_MICROBLAZE0_USE_FPU=0
202CONFIG_XILINX_MICROBLAZE0_HW_VER="8.50.a" 202CONFIG_XILINX_MICROBLAZE0_HW_VER="8.50.a"
203 203
diff --git a/meta-kc705/recipes-kernel/linux/linux-xlnx/kc705-trd.dts b/meta-kc705/recipes-kernel/linux/linux-xlnx/kc705-trd.dts
index 233d76db..00ae72a0 100644
--- a/meta-kc705/recipes-kernel/linux/linux-xlnx/kc705-trd.dts
+++ b/meta-kc705/recipes-kernel/linux/linux-xlnx/kc705-trd.dts
@@ -3,59 +3,58 @@
3 #address-cells = <1>; 3 #address-cells = <1>;
4 #size-cells = <1>; 4 #size-cells = <1>;
5 compatible = "xlnx,microblaze"; 5 compatible = "xlnx,microblaze";
6 hard-reset-gpios = < &reset_gpio 0 1 >;
7 model = "Xilinx-KC705-TRD"; 6 model = "Xilinx-KC705-TRD";
8 aliases { 7 aliases {
9 ethernet0 = &ethernet; 8 ethernet0 = &soft_ethernet_mac;
10 serial0 = &rs232_uart_1; 9 serial0 = &rs232_uart_1;
11 } ; 10 } ;
12 chosen { 11 chosen {
13 bootargs = "console=ttyS0,115200 root=/dev/ram rw"; 12 bootargs = "console=ttyS0,115200 root=/dev/ram rw";
14 linux,stdout-path = "/axi@1/serial@40400000"; 13 linux,stdout-path = "/axi@2/serial@40400000";
15 } ; 14 } ;
16 cpus { 15 cpus {
17 #address-cells = <1>; 16 #address-cells = <1>;
18 #cpus = <0x1>; 17 #cpus = <0x1>;
19 #size-cells = <0>; 18 #size-cells = <0>;
20 microblaze_0: cpu@0 { 19 microblaze_0: cpu@0 {
21 clock-frequency = <100000000>; 20 clock-frequency = <150000000>;
22 compatible = "xlnx,microblaze-8.50.a"; 21 compatible = "xlnx,microblaze-8.50.a";
23 d-cache-baseaddr = <0x80000000>; 22 d-cache-baseaddr = <0x80000000>;
24 d-cache-highaddr = <0x87ffffff>; 23 d-cache-highaddr = <0xffffffff>;
25 d-cache-line-size = <0x10>; 24 d-cache-line-size = <0x20>;
26 d-cache-size = <0x4000>; 25 d-cache-size = <0x2000>;
27 device_type = "cpu"; 26 device_type = "cpu";
28 i-cache-baseaddr = <0x80000000>; 27 i-cache-baseaddr = <0x80000000>;
29 i-cache-highaddr = <0x87ffffff>; 28 i-cache-highaddr = <0xffffffff>;
30 i-cache-line-size = <0x10>; 29 i-cache-line-size = <0x20>;
31 i-cache-size = <0x4000>; 30 i-cache-size = <0x2000>;
32 model = "microblaze,8.50.a"; 31 model = "microblaze,8.50.a";
33 reg = <0>; 32 reg = <0>;
34 timebase-frequency = <100000000>; 33 timebase-frequency = <150000000>;
35 xlnx,addr-tag-bits = <0xd>; 34 xlnx,addr-tag-bits = <0x12>;
36 xlnx,allow-dcache-wr = <0x1>; 35 xlnx,allow-dcache-wr = <0x1>;
37 xlnx,allow-icache-wr = <0x1>; 36 xlnx,allow-icache-wr = <0x1>;
38 xlnx,area-optimized = <0x0>; 37 xlnx,area-optimized = <0x0>;
39 xlnx,avoid-primitives = <0x0>; 38 xlnx,avoid-primitives = <0x0>;
40 xlnx,base-vectors = <0x0>; 39 xlnx,base-vectors = <0x0>;
41 xlnx,branch-target-cache-size = <0x0>; 40 xlnx,branch-target-cache-size = <0x0>;
42 xlnx,cache-byte-size = <0x4000>; 41 xlnx,cache-byte-size = <0x2000>;
43 xlnx,d-axi = <0x1>; 42 xlnx,d-axi = <0x1>;
44 xlnx,d-lmb = <0x1>; 43 xlnx,d-lmb = <0x1>;
45 xlnx,d-plb = <0x0>; 44 xlnx,d-plb = <0x0>;
46 xlnx,data-size = <0x20>; 45 xlnx,data-size = <0x20>;
47 xlnx,dcache-addr-tag = <0xd>; 46 xlnx,dcache-addr-tag = <0x12>;
48 xlnx,dcache-always-used = <0x1>; 47 xlnx,dcache-always-used = <0x1>;
49 xlnx,dcache-byte-size = <0x4000>; 48 xlnx,dcache-byte-size = <0x2000>;
50 xlnx,dcache-data-width = <0x0>; 49 xlnx,dcache-data-width = <0x0>;
51 xlnx,dcache-force-tag-lutram = <0x0>; 50 xlnx,dcache-force-tag-lutram = <0x1>;
52 xlnx,dcache-interface = <0x0>; 51 xlnx,dcache-interface = <0x0>;
53 xlnx,dcache-line-len = <0x4>; 52 xlnx,dcache-line-len = <0x8>;
54 xlnx,dcache-use-fsl = <0x0>; 53 xlnx,dcache-use-fsl = <0x0>;
55 xlnx,dcache-use-writeback = <0x0>; 54 xlnx,dcache-use-writeback = <0x0>;
56 xlnx,dcache-victims = <0x0>; 55 xlnx,dcache-victims = <0x0>;
57 xlnx,debug-enabled = <0x1>; 56 xlnx,debug-enabled = <0x1>;
58 xlnx,div-zero-exception = <0x1>; 57 xlnx,div-zero-exception = <0x0>;
59 xlnx,dynamic-bus-sizing = <0x1>; 58 xlnx,dynamic-bus-sizing = <0x1>;
60 xlnx,ecc-use-ce-exception = <0x0>; 59 xlnx,ecc-use-ce-exception = <0x0>;
61 xlnx,edge-is-positive = <0x1>; 60 xlnx,edge-is-positive = <0x1>;
@@ -63,18 +62,18 @@
63 xlnx,family = "kintex7"; 62 xlnx,family = "kintex7";
64 xlnx,fault-tolerant = <0x0>; 63 xlnx,fault-tolerant = <0x0>;
65 xlnx,fpu-exception = <0x0>; 64 xlnx,fpu-exception = <0x0>;
66 xlnx,freq = <0x5f5e100>; 65 xlnx,freq = <0x8f0d180>;
67 xlnx,fsl-data-size = <0x20>; 66 xlnx,fsl-data-size = <0x20>;
68 xlnx,fsl-exception = <0x0>; 67 xlnx,fsl-exception = <0x0>;
69 xlnx,fsl-links = <0x0>; 68 xlnx,fsl-links = <0x0>;
70 xlnx,i-axi = <0x1>; 69 xlnx,i-axi = <0x0>;
71 xlnx,i-lmb = <0x1>; 70 xlnx,i-lmb = <0x1>;
72 xlnx,i-plb = <0x0>; 71 xlnx,i-plb = <0x0>;
73 xlnx,icache-always-used = <0x1>; 72 xlnx,icache-always-used = <0x1>;
74 xlnx,icache-data-width = <0x0>; 73 xlnx,icache-data-width = <0x0>;
75 xlnx,icache-force-tag-lutram = <0x0>; 74 xlnx,icache-force-tag-lutram = <0x1>;
76 xlnx,icache-interface = <0x0>; 75 xlnx,icache-interface = <0x0>;
77 xlnx,icache-line-len = <0x4>; 76 xlnx,icache-line-len = <0x8>;
78 xlnx,icache-streams = <0x0>; 77 xlnx,icache-streams = <0x0>;
79 xlnx,icache-use-fsl = <0x0>; 78 xlnx,icache-use-fsl = <0x0>;
80 xlnx,icache-victims = <0x0>; 79 xlnx,icache-victims = <0x0>;
@@ -84,7 +83,7 @@
84 xlnx,interrupt-is-edge = <0x0>; 83 xlnx,interrupt-is-edge = <0x0>;
85 xlnx,lockstep-slave = <0x0>; 84 xlnx,lockstep-slave = <0x0>;
86 xlnx,mmu-dtlb-size = <0x2>; 85 xlnx,mmu-dtlb-size = <0x2>;
87 xlnx,mmu-itlb-size = <0x4>; 86 xlnx,mmu-itlb-size = <0x2>;
88 xlnx,mmu-privileged-instr = <0x0>; 87 xlnx,mmu-privileged-instr = <0x0>;
89 xlnx,mmu-tlb-access = <0x3>; 88 xlnx,mmu-tlb-access = <0x3>;
90 xlnx,mmu-zones = <0x2>; 89 xlnx,mmu-zones = <0x2>;
@@ -104,12 +103,12 @@
104 xlnx,use-barrel = <0x1>; 103 xlnx,use-barrel = <0x1>;
105 xlnx,use-branch-target-cache = <0x0>; 104 xlnx,use-branch-target-cache = <0x0>;
106 xlnx,use-dcache = <0x1>; 105 xlnx,use-dcache = <0x1>;
107 xlnx,use-div = <0x1>; 106 xlnx,use-div = <0x0>;
108 xlnx,use-ext-brk = <0x1>; 107 xlnx,use-ext-brk = <0x1>;
109 xlnx,use-ext-nm-brk = <0x1>; 108 xlnx,use-ext-nm-brk = <0x1>;
110 xlnx,use-extended-fsl-instr = <0x0>; 109 xlnx,use-extended-fsl-instr = <0x0>;
111 xlnx,use-fpu = <0x0>; 110 xlnx,use-fpu = <0x0>;
112 xlnx,use-hw-mul = <0x2>; 111 xlnx,use-hw-mul = <0x1>;
113 xlnx,use-icache = <0x1>; 112 xlnx,use-icache = <0x1>;
114 xlnx,use-interrupt = <0x1>; 113 xlnx,use-interrupt = <0x1>;
115 xlnx,use-mmu = <0x3>; 114 xlnx,use-mmu = <0x3>;
@@ -121,22 +120,56 @@
121 } ; 120 } ;
122 ddr3_sdram: memory@80000000 { 121 ddr3_sdram: memory@80000000 {
123 device_type = "memory"; 122 device_type = "memory";
124 reg = < 0x80000000 0x8000000 >; 123 reg = < 0x80000000 0x40000000 >;
125 } ;
126 axi4_0: axi@0 {
127 #address-cells = <1>;
128 #size-cells = <1>;
129 compatible = "xlnx,axi-interconnect-1.06.a", "simple-bus";
130 ranges ;
131 } ; 124 } ;
132 axi4lite_0: axi@1 { 125 axi4lite_0: axi@2 {
133 #address-cells = <1>; 126 #address-cells = <1>;
134 #size-cells = <1>; 127 #size-cells = <1>;
135 compatible = "xlnx,axi-interconnect-1.06.a", "simple-bus"; 128 compatible = "xlnx,axi-interconnect-1.06.a", "simple-bus";
136 ranges ; 129 ranges ;
137 debug_module: serial@41400000 { 130 axi_dma_ethernet: axi-dma@50000000 {
131 axistream-connected = <&soft_ethernet_mac>;
132 axistream-control-connected = <&soft_ethernet_mac>;
133 compatible = "xlnx,axi-dma-6.03.a", "xlnx,axi-dma-1.00.a";
134 interrupt-parent = <&interrupt_cntlr>;
135 interrupts = < 0 2 1 2 >;
136 reg = < 0x50000000 0x10000 >;
137 xlnx,dlytmr-resolution = <0x4e2>;
138 xlnx,enable-multi-channel = <0x0>;
139 xlnx,family = "kintex7";
140 xlnx,generic = <0x0>;
141 xlnx,include-mm2s = <0x1>;
142 xlnx,include-mm2s-dre = <0x1>;
143 xlnx,include-mm2s-sf = <0x1>;
144 xlnx,include-s2mm = <0x1>;
145 xlnx,include-s2mm-dre = <0x1>;
146 xlnx,include-s2mm-sf = <0x1>;
147 xlnx,include-sg = <0x1>;
148 xlnx,instance = "AXI_DMA_Ethernet";
149 xlnx,mm2s-burst-size = <0x10>;
150 xlnx,num-mm2s-channels = <0x1>;
151 xlnx,num-s2mm-channels = <0x1>;
152 xlnx,prmry-is-aclk-async = <0x1>;
153 xlnx,s2mm-burst-size = <0x10>;
154 xlnx,sg-include-desc-queue = <0x1>;
155 xlnx,sg-include-stscntrl-strm = <0x1>;
156 xlnx,sg-length-width = <0x10>;
157 xlnx,sg-use-stsapp-length = <0x1>;
158 } ;
159 axi_xadc_0: axi-xadc@40d00000 {
160 compatible = "xlnx,axi-xadc-1.00.a";
161 interrupt-parent = <&interrupt_cntlr>;
162 interrupts = < 7 2 >;
163 reg = < 0x40d00000 0x10000 >;
164 xlnx,family = "kintex7";
165 xlnx,has-temp-bus = <0x1>;
166 xlnx,include-intr = <0x1>;
167 xlnx,instance = "axi_xadc_0";
168 xlnx,sim-monitor-file = "Sysmon_Design.txt";
169 } ;
170 debug_module: serial@40200000 {
138 compatible = "xlnx,mdm-2.10.a", "xlnx,xps-uartlite-1.00.a"; 171 compatible = "xlnx,mdm-2.10.a", "xlnx,xps-uartlite-1.00.a";
139 reg = < 0x41400000 0x10000 >; 172 reg = < 0x40200000 0x10000 >;
140 xlnx,family = "kintex7"; 173 xlnx,family = "kintex7";
141 xlnx,interconnect = <0x2>; 174 xlnx,interconnect = <0x2>;
142 xlnx,jtag-chain = <0x2>; 175 xlnx,jtag-chain = <0x2>;
@@ -144,11 +177,11 @@
144 xlnx,use-bscan = <0x0>; 177 xlnx,use-bscan = <0x0>;
145 xlnx,use-uart = <0x1>; 178 xlnx,use-uart = <0x1>;
146 } ; 179 } ;
147 dip_switches_8bits: gpio@40060000 { 180 dip_switches_4bits: gpio@40700000 {
148 #gpio-cells = <2>; 181 #gpio-cells = <2>;
149 compatible = "xlnx,axi-gpio-1.01.b", "xlnx,xps-gpio-1.00.a"; 182 compatible = "xlnx,axi-gpio-1.01.b", "xlnx,xps-gpio-1.00.a";
150 gpio-controller ; 183 gpio-controller ;
151 reg = < 0x40060000 0x10000 >; 184 reg = < 0x40700000 0x10000 >;
152 xlnx,all-inputs = <0x1>; 185 xlnx,all-inputs = <0x1>;
153 xlnx,all-inputs-2 = <0x0>; 186 xlnx,all-inputs-2 = <0x0>;
154 xlnx,dout-default = <0x0>; 187 xlnx,dout-default = <0x0>;
@@ -156,85 +189,72 @@
156 xlnx,family = "kintex7"; 189 xlnx,family = "kintex7";
157 xlnx,gpio-width = <0x4>; 190 xlnx,gpio-width = <0x4>;
158 xlnx,gpio2-width = <0x20>; 191 xlnx,gpio2-width = <0x20>;
159 xlnx,instance = "DIP_Switches_8Bits"; 192 xlnx,instance = "DIP_Switches_4Bits";
160 xlnx,interrupt-present = <0x0>; 193 xlnx,interrupt-present = <0x1>;
161 xlnx,is-dual = <0x0>; 194 xlnx,is-dual = <0x0>;
162 xlnx,tri-default = <0xffffffff>; 195 xlnx,tri-default = <0xffffffff>;
163 xlnx,tri-default-2 = <0xffffffff>; 196 xlnx,tri-default-2 = <0xffffffff>;
164 } ; 197 } ;
165 ethernet: axi-ethernet@44f40000 { 198 dual_timer_counter: system-timer@40300000 {
166 axistream-connected = <&ethernet_dma>;
167 axistream-control-connected = <&ethernet_dma>;
168 clock-frequency = <100000000>; 199 clock-frequency = <100000000>;
169 compatible = "xlnx,axi-ethernet-3.01.a", "xlnx,axi-ethernet-1.00.a"; 200 compatible = "xlnx,axi-timer-1.03.a", "xlnx,xps-timer-1.00.a";
170 device_type = "network"; 201 interrupt-parent = <&interrupt_cntlr>;
171 interrupt-parent = <&microblaze_0_intc>;
172 interrupts = < 3 2 >; 202 interrupts = < 3 2 >;
173 local-mac-address = [ 00 0a 35 00 d9 4e ]; 203 reg = < 0x40300000 0x10000 >;
174 phy-handle = <&phy0>; 204 xlnx,count-width = <0x20>;
175 reg = < 0x44f40000 0x40000 >; 205 xlnx,family = "kintex7";
176 xlnx,avb = <0x0>; 206 xlnx,gen0-assert = <0x1>;
177 xlnx,halfdup = <0x0>; 207 xlnx,gen1-assert = <0x1>;
178 xlnx,include-io = <0x1>; 208 xlnx,instance = "Dual_Timer_Counter";
179 xlnx,mcast-extend = <0x0>; 209 xlnx,one-timer-only = <0x0>;
180 xlnx,phy-type = <0x1>; 210 xlnx,trig0-assert = <0x1>;
181 xlnx,phyaddr = "0B00001"; 211 xlnx,trig1-assert = <0x1>;
182 xlnx,rxcsum = <0x0>;
183 xlnx,rxmem = <0x1000>;
184 xlnx,rxvlan-strp = <0x0>;
185 xlnx,rxvlan-tag = <0x0>;
186 xlnx,rxvlan-tran = <0x0>;
187 xlnx,stats = <0x0>;
188 xlnx,txcsum = <0x0>;
189 xlnx,txmem = <0x1000>;
190 xlnx,txvlan-strp = <0x0>;
191 xlnx,txvlan-tag = <0x0>;
192 xlnx,txvlan-tran = <0x0>;
193 xlnx,type = <0x1>;
194 mdio {
195 #address-cells = <1>;
196 #size-cells = <0>;
197 phy0: phy@7 {
198 compatible = "marvell,88e1111";
199 device_type = "ethernet-phy";
200 reg = <7>;
201 } ;
202 } ;
203 } ; 212 } ;
204 ethernet_dma: axi-dma@41e00000 { 213 iic_eeprom: i2c@40a00000 {
205 axistream-connected = <&ethernet>; 214 compatible = "xlnx,axi-iic-1.02.a", "xlnx,xps-iic-2.00.a";
206 axistream-control-connected = <&ethernet>; 215 interrupt-parent = <&interrupt_cntlr>;
207 compatible = "xlnx,axi-dma-6.03.a", "xlnx,axi-dma-1.00.a"; 216 interrupts = < 4 2 >;
208 interrupt-parent = <&microblaze_0_intc>; 217 reg = < 0x40a00000 0x10000 >;
209 interrupts = < 1 2 0 2 >;
210 reg = < 0x41e00000 0x10000 >;
211 xlnx,dlytmr-resolution = <0x4e2>;
212 xlnx,enable-multi-channel = <0x0>;
213 xlnx,family = "kintex7"; 218 xlnx,family = "kintex7";
214 xlnx,generic = <0x0>; 219 xlnx,gpo-width = <0x1>;
215 xlnx,include-mm2s = <0x1>; 220 xlnx,iic-freq = <0x186a0>;
216 xlnx,include-mm2s-dre = <0x1>; 221 xlnx,instance = "IIC_EEPROM";
217 xlnx,include-mm2s-sf = <0x1>; 222 xlnx,scl-inertial-delay = <0x0>;
218 xlnx,include-s2mm = <0x1>; 223 xlnx,sda-inertial-delay = <0x0>;
219 xlnx,include-s2mm-dre = <0x1>; 224 xlnx,sda-level = <0x1>;
220 xlnx,include-s2mm-sf = <0x1>; 225 xlnx,ten-bit-adr = <0x0>;
221 xlnx,include-sg = <0x1>; 226 } ;
222 xlnx,instance = "ETHERNET_dma"; 227 interrupt_cntlr: interrupt-controller@40100000 {
223 xlnx,mm2s-burst-size = <0x10>; 228 #interrupt-cells = <0x2>;
224 xlnx,num-mm2s-channels = <0x1>; 229 compatible = "xlnx,axi-intc-1.03.a", "xlnx,xps-intc-1.00.a";
225 xlnx,num-s2mm-channels = <0x1>; 230 interrupt-controller ;
226 xlnx,prmry-is-aclk-async = <0x0>; 231 reg = < 0x40100000 0x10000 >;
227 xlnx,s2mm-burst-size = <0x10>; 232 xlnx,kind-of-intr = <0x0>;
228 xlnx,sg-include-desc-queue = <0x1>; 233 xlnx,num-intr-inputs = <0x8>;
229 xlnx,sg-include-stscntrl-strm = <0x1>;
230 xlnx,sg-length-width = <0x10>;
231 xlnx,sg-use-stsapp-length = <0x1>;
232 } ; 234 } ;
233 leds_8bits: gpio@40040000 { 235 lcd_gpio: gpio@40800000 {
234 #gpio-cells = <2>; 236 #gpio-cells = <2>;
235 compatible = "xlnx,axi-gpio-1.01.b", "xlnx,xps-gpio-1.00.a"; 237 compatible = "xlnx,axi-gpio-1.01.b", "xlnx,xps-gpio-1.00.a";
236 gpio-controller ; 238 gpio-controller ;
237 reg = < 0x40040000 0x10000 >; 239 reg = < 0x40800000 0x10000 >;
240 xlnx,all-inputs = <0x0>;
241 xlnx,all-inputs-2 = <0x0>;
242 xlnx,dout-default = <0x0>;
243 xlnx,dout-default-2 = <0x0>;
244 xlnx,family = "kintex7";
245 xlnx,gpio-width = <0x7>;
246 xlnx,gpio2-width = <0x20>;
247 xlnx,instance = "LCD_GPIO";
248 xlnx,interrupt-present = <0x0>;
249 xlnx,is-dual = <0x0>;
250 xlnx,tri-default = <0xffffffff>;
251 xlnx,tri-default-2 = <0xffffffff>;
252 } ;
253 leds_8bits: gpio@40600000 {
254 #gpio-cells = <2>;
255 compatible = "xlnx,axi-gpio-1.01.b", "xlnx,xps-gpio-1.00.a";
256 gpio-controller ;
257 reg = < 0x40600000 0x10000 >;
238 xlnx,all-inputs = <0x0>; 258 xlnx,all-inputs = <0x0>;
239 xlnx,all-inputs-2 = <0x0>; 259 xlnx,all-inputs-2 = <0x0>;
240 xlnx,dout-default = <0x0>; 260 xlnx,dout-default = <0x0>;
@@ -243,25 +263,38 @@
243 xlnx,gpio-width = <0x8>; 263 xlnx,gpio-width = <0x8>;
244 xlnx,gpio2-width = <0x20>; 264 xlnx,gpio2-width = <0x20>;
245 xlnx,instance = "LEDs_8Bits"; 265 xlnx,instance = "LEDs_8Bits";
246 xlnx,interrupt-present = <0x0>; 266 xlnx,interrupt-present = <0x1>;
247 xlnx,is-dual = <0x0>; 267 xlnx,is-dual = <0x0>;
248 xlnx,tri-default = <0xffffffff>; 268 xlnx,tri-default = <0xffffffff>;
249 xlnx,tri-default-2 = <0xffffffff>; 269 xlnx,tri-default-2 = <0xffffffff>;
250 } ; 270 } ;
251 microblaze_0_intc: interrupt-controller@41200000 { 271 logisdhc_0: logisdhc@40b00000 {
252 #interrupt-cells = <0x2>; 272 compatible = "xlnx,logisdhc-1.06.c";
253 compatible = "xlnx,axi-intc-1.03.a", "xlnx,xps-intc-1.00.a"; 273 interrupt-parent = <&interrupt_cntlr>;
254 interrupt-controller ; 274 interrupts = < 6 2 >;
255 reg = < 0x41200000 0x10000 >; 275 reg = < 0x40b00000 0x10000 >;
256 xlnx,kind-of-intr = <0x0>; 276 xlnx,byte-per-pixel = <0x4>;
257 xlnx,num-intr-inputs = <0x5>; 277 xlnx,convert-endianess = <0x0>;
278 xlnx,dma-type = <0x1>;
279 xlnx,family = "kintex7";
280 xlnx,ip-license-type = <0x1>;
281 xlnx,ip-major-revision = <0x1>;
282 xlnx,ip-minor-revision = <0x6>;
283 xlnx,ip-patch-level = <0x2>;
284 xlnx,mem-burst = <0x4>;
285 xlnx,mem-data-bus-width = <0x20>;
286 xlnx,mem-interface = <0x1>;
287 xlnx,regs-interface = <0x2>;
288 xlnx,row-stride = <0x400>;
289 xlnx,sd-base-clock-freq = <0x64>;
290 xlnx,use-dma = <0x0>;
258 } ; 291 } ;
259 primary_flash: flash@a0000000 { 292 primary_flash: flash@48000000 {
260 #address-cells = <1>; 293 #address-cells = <1>;
261 #size-cells = <1>; 294 #size-cells = <1>;
262 bank-width = <2>; 295 bank-width = <2>;
263 compatible = "xlnx,axi-emc-1.03.b", "cfi-flash"; 296 compatible = "xlnx,axi-emc-1.03.b", "cfi-flash";
264 reg = < 0xa0000000 0x8000000 >; 297 reg = < 0x48000000 0x8000000 >;
265 xlnx,axi-clk-period-ps = <0x2710>; 298 xlnx,axi-clk-period-ps = <0x2710>;
266 xlnx,family = "kintex7"; 299 xlnx,family = "kintex7";
267 xlnx,include-datawidth-matching-0 = <0x1>; 300 xlnx,include-datawidth-matching-0 = <0x1>;
@@ -306,7 +339,7 @@
306 xlnx,tcedv-ps-mem-1 = <0x3a98>; 339 xlnx,tcedv-ps-mem-1 = <0x3a98>;
307 xlnx,tcedv-ps-mem-2 = <0x3a98>; 340 xlnx,tcedv-ps-mem-2 = <0x3a98>;
308 xlnx,tcedv-ps-mem-3 = <0x3a98>; 341 xlnx,tcedv-ps-mem-3 = <0x3a98>;
309 xlnx,thzce-ps-mem-0 = <0x1b58>; 342 xlnx,thzce-ps-mem-0 = <0x88b8>;
310 xlnx,thzce-ps-mem-1 = <0x1b58>; 343 xlnx,thzce-ps-mem-1 = <0x1b58>;
311 xlnx,thzce-ps-mem-2 = <0x1b58>; 344 xlnx,thzce-ps-mem-2 = <0x1b58>;
312 xlnx,thzce-ps-mem-3 = <0x1b58>; 345 xlnx,thzce-ps-mem-3 = <0x1b58>;
@@ -314,7 +347,7 @@
314 xlnx,thzoe-ps-mem-1 = <0x1b58>; 347 xlnx,thzoe-ps-mem-1 = <0x1b58>;
315 xlnx,thzoe-ps-mem-2 = <0x1b58>; 348 xlnx,thzoe-ps-mem-2 = <0x1b58>;
316 xlnx,thzoe-ps-mem-3 = <0x1b58>; 349 xlnx,thzoe-ps-mem-3 = <0x1b58>;
317 xlnx,tlzwe-ps-mem-0 = <0xc350>; 350 xlnx,tlzwe-ps-mem-0 = <0x88b8>;
318 xlnx,tlzwe-ps-mem-1 = <0x0>; 351 xlnx,tlzwe-ps-mem-1 = <0x0>;
319 xlnx,tlzwe-ps-mem-2 = <0x0>; 352 xlnx,tlzwe-ps-mem-2 = <0x0>;
320 xlnx,tlzwe-ps-mem-3 = <0x0>; 353 xlnx,tlzwe-ps-mem-3 = <0x0>;
@@ -322,11 +355,11 @@
322 xlnx,tpacc-ps-flash-1 = <0x61a8>; 355 xlnx,tpacc-ps-flash-1 = <0x61a8>;
323 xlnx,tpacc-ps-flash-2 = <0x61a8>; 356 xlnx,tpacc-ps-flash-2 = <0x61a8>;
324 xlnx,tpacc-ps-flash-3 = <0x61a8>; 357 xlnx,tpacc-ps-flash-3 = <0x61a8>;
325 xlnx,twc-ps-mem-0 = <0x13880>; 358 xlnx,twc-ps-mem-0 = <0x11170>;
326 xlnx,twc-ps-mem-1 = <0x3a98>; 359 xlnx,twc-ps-mem-1 = <0x3a98>;
327 xlnx,twc-ps-mem-2 = <0x3a98>; 360 xlnx,twc-ps-mem-2 = <0x3a98>;
328 xlnx,twc-ps-mem-3 = <0x3a98>; 361 xlnx,twc-ps-mem-3 = <0x3a98>;
329 xlnx,twp-ps-mem-0 = <0x13880>; 362 xlnx,twp-ps-mem-0 = <0x11170>;
330 xlnx,twp-ps-mem-1 = <0x2ee0>; 363 xlnx,twp-ps-mem-1 = <0x2ee0>;
331 xlnx,twp-ps-mem-2 = <0x2ee0>; 364 xlnx,twp-ps-mem-2 = <0x2ee0>;
332 xlnx,twp-ps-mem-3 = <0x2ee0>; 365 xlnx,twp-ps-mem-3 = <0x2ee0>;
@@ -340,30 +373,30 @@
340 xlnx,wr-rec-time-mem-3 = <0x186a0>; 373 xlnx,wr-rec-time-mem-3 = <0x186a0>;
341 partition@0x00000000 { 374 partition@0x00000000 {
342 label = "fpga"; 375 label = "fpga";
343 reg = <0x00000000 0x00b00000>; 376 reg = <0x00000000 0x00200000>;
344 }; 377 };
345 partition@0x00b00000 { 378 partition@0x00200000 {
346 label = "boot"; 379 label = "boot";
347 reg = <0x00b00000 0x00040000>; 380 reg = <0x00200000 0x00040000>;
348 }; 381 };
349 partition@0x00b40000 { 382 partition@0x00240000 {
350 label = "bootenv"; 383 label = "bootenv";
351 reg = <0x00b40000 0x00020000>; 384 reg = <0x00240000 0x00020000>;
352 }; 385 };
353 partition@0x00b60000 { 386 partition@0x00260000 {
354 label = "image"; 387 label = "image";
355 reg = <0x00b60000 0x00c00000>; 388 reg = <0x00260000 0x00c00000>;
356 }; 389 };
357 partition@0x01760000 { 390 partition@0x00e60000 {
358 label = "spare"; 391 label = "spare";
359 reg = <0x01760000 0x00000000>; 392 reg = <0x00e60000 0x00000000>;
360 }; 393 };
361 } ; 394 } ;
362 push_buttons_5bits: gpio@40020000 { 395 push_buttons_5bits: gpio@40500000 {
363 #gpio-cells = <2>; 396 #gpio-cells = <2>;
364 compatible = "xlnx,axi-gpio-1.01.b", "xlnx,xps-gpio-1.00.a"; 397 compatible = "xlnx,axi-gpio-1.01.b", "xlnx,xps-gpio-1.00.a";
365 gpio-controller ; 398 gpio-controller ;
366 reg = < 0x40020000 0x10000 >; 399 reg = < 0x40500000 0x10000 >;
367 xlnx,all-inputs = <0x1>; 400 xlnx,all-inputs = <0x1>;
368 xlnx,all-inputs-2 = <0x0>; 401 xlnx,all-inputs-2 = <0x0>;
369 xlnx,dout-default = <0x0>; 402 xlnx,dout-default = <0x0>;
@@ -372,24 +405,24 @@
372 xlnx,gpio-width = <0x5>; 405 xlnx,gpio-width = <0x5>;
373 xlnx,gpio2-width = <0x20>; 406 xlnx,gpio2-width = <0x20>;
374 xlnx,instance = "Push_Buttons_5Bits"; 407 xlnx,instance = "Push_Buttons_5Bits";
375 xlnx,interrupt-present = <0x0>; 408 xlnx,interrupt-present = <0x1>;
376 xlnx,is-dual = <0x0>; 409 xlnx,is-dual = <0x0>;
377 xlnx,tri-default = <0xffffffff>; 410 xlnx,tri-default = <0xffffffff>;
378 xlnx,tri-default-2 = <0xffffffff>; 411 xlnx,tri-default-2 = <0xffffffff>;
379 } ; 412 } ;
380 reset_gpio: gpio@40000000 { 413 rotary_gpio: gpio@40900000 {
381 #gpio-cells = <2>; 414 #gpio-cells = <2>;
382 compatible = "xlnx,axi-gpio-1.01.b", "xlnx,xps-gpio-1.00.a"; 415 compatible = "xlnx,axi-gpio-1.01.b", "xlnx,xps-gpio-1.00.a";
383 gpio-controller ; 416 gpio-controller ;
384 reg = < 0x40000000 0x10000 >; 417 reg = < 0x40900000 0x10000 >;
385 xlnx,all-inputs = <0x0>; 418 xlnx,all-inputs = <0x1>;
386 xlnx,all-inputs-2 = <0x0>; 419 xlnx,all-inputs-2 = <0x0>;
387 xlnx,dout-default = <0x0>; 420 xlnx,dout-default = <0x0>;
388 xlnx,dout-default-2 = <0x0>; 421 xlnx,dout-default-2 = <0x0>;
389 xlnx,family = "kintex7"; 422 xlnx,family = "kintex7";
390 xlnx,gpio-width = <0x1>; 423 xlnx,gpio-width = <0x3>;
391 xlnx,gpio2-width = <0x20>; 424 xlnx,gpio2-width = <0x20>;
392 xlnx,instance = "Reset_GPIO"; 425 xlnx,instance = "ROTARY_GPIO";
393 xlnx,interrupt-present = <0x0>; 426 xlnx,interrupt-present = <0x0>;
394 xlnx,is-dual = <0x0>; 427 xlnx,is-dual = <0x0>;
395 xlnx,tri-default = <0xffffffff>; 428 xlnx,tri-default = <0xffffffff>;
@@ -400,8 +433,8 @@
400 compatible = "xlnx,axi-uart16550-1.01.a", "xlnx,xps-uart16550-2.00.a", "ns16550a"; 433 compatible = "xlnx,axi-uart16550-1.01.a", "xlnx,xps-uart16550-2.00.a", "ns16550a";
401 current-speed = <115200>; 434 current-speed = <115200>;
402 device_type = "serial"; 435 device_type = "serial";
403 interrupt-parent = <&microblaze_0_intc>; 436 interrupt-parent = <&interrupt_cntlr>;
404 interrupts = < 4 2 >; 437 interrupts = < 5 2 >;
405 reg = < 0x40400000 0x10000 >; 438 reg = < 0x40400000 0x10000 >;
406 reg-offset = <0x1000>; 439 reg-offset = <0x1000>;
407 reg-shift = <2>; 440 reg-shift = <2>;
@@ -414,20 +447,56 @@
414 xlnx,use-modem-ports = <0x0>; 447 xlnx,use-modem-ports = <0x0>;
415 xlnx,use-user-ports = <0x0>; 448 xlnx,use-user-ports = <0x0>;
416 } ; 449 } ;
417 system_timer: system-timer@41c00000 { 450 soft_ethernet_mac: axi-ethernet@50100000 {
451 axistream-connected = <&axi_dma_ethernet>;
452 axistream-control-connected = <&axi_dma_ethernet>;
418 clock-frequency = <100000000>; 453 clock-frequency = <100000000>;
419 compatible = "xlnx,axi-timer-1.03.a", "xlnx,xps-timer-1.00.a"; 454 compatible = "xlnx,axi-ethernet-3.01.a", "xlnx,axi-ethernet-1.00.a";
420 interrupt-parent = <&microblaze_0_intc>; 455 device_type = "network";
456 interrupt-parent = <&interrupt_cntlr>;
421 interrupts = < 2 2 >; 457 interrupts = < 2 2 >;
422 reg = < 0x41c00000 0x10000 >; 458 local-mac-address = [ 00 0a 35 00 d9 4e ];
423 xlnx,count-width = <0x20>; 459 phy-handle = <&phy0>;
424 xlnx,family = "kintex7"; 460 reg = < 0x50100000 0x40000 >;
425 xlnx,gen0-assert = <0x1>; 461 xlnx,avb = <0x0>;
426 xlnx,gen1-assert = <0x1>; 462 xlnx,halfdup = <0x0>;
427 xlnx,instance = "system_timer"; 463 xlnx,include-io = <0x1>;
428 xlnx,one-timer-only = <0x0>; 464 xlnx,mcast-extend = <0x0>;
429 xlnx,trig0-assert = <0x1>; 465 xlnx,phy-type = <0x1>;
430 xlnx,trig1-assert = <0x1>; 466 xlnx,phyaddr = <0x1>;
467 xlnx,rxcsum = <0x0>;
468 xlnx,rxmem = <0x1000>;
469 xlnx,rxvlan-strp = <0x0>;
470 xlnx,rxvlan-tag = <0x0>;
471 xlnx,rxvlan-tran = <0x0>;
472 xlnx,stats = <0x0>;
473 xlnx,txcsum = <0x0>;
474 xlnx,txmem = <0x1000>;
475 xlnx,txvlan-strp = <0x0>;
476 xlnx,txvlan-tag = <0x0>;
477 xlnx,txvlan-tran = <0x0>;
478 xlnx,type = <0x1>;
479 mdio {
480 #address-cells = <1>;
481 #size-cells = <0>;
482 phy0: phy@7 {
483 compatible = "marvell,88e1111";
484 device_type = "ethernet-phy";
485 reg = <7>;
486 } ;
487 } ;
488 } ;
489 } ;
490 axi_mm_mb: axi@1 {
491 #address-cells = <1>;
492 #size-cells = <1>;
493 compatible = "xlnx,axi-interconnect-1.06.a", "simple-bus";
494 ranges ;
495 axi4_0: axi@0 {
496 #address-cells = <1>;
497 #size-cells = <1>;
498 compatible = "xlnx,axi-interconnect-1.06.a", "simple-bus";
499 ranges = < 0x80000000 0x80000000 0x40000000 >;
431 } ; 500 } ;
432 } ; 501 } ;
433} ; 502} ;
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2026-04-21 20:32:59 +0000