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| author | Sivaprasad Addepalli <sivaprasad.addepalli@xilinx.com> | 2023-06-21 12:47:00 +0530 |
|---|---|---|
| committer | Siva Addepalli <sivaprasad.addepalli@xilinx.com> | 2023-06-21 15:37:10 +0530 |
| commit | ecfc108ebf007ddd6d02f8d5012f25daf153cded (patch) | |
| tree | 43ae4ec6e9daa886e358ffaeb4e4487882c0d8fa /README.building.md | |
| parent | bf745fd482cac2d4149a6bad52c0d6e77857a36b (diff) | |
| download | meta-xilinx-ecfc108ebf007ddd6d02f8d5012f25daf153cded.tar.gz | |
Updated SRCREV of u-boot-xlnx for 2023.2_8771
net: zynq_gem: Don't hardcode the MDC clock divisor
spi: zynqmp_qspi: Workaround for small data cache issue
spi: zynqmp_qspi: Change flush cache to invalidate cache
arm64: versal-net: Add LPD-WWDT to versal-net.dtsi
include: dt-bindings: power: Add TCM,RPU nodes for Versal NET
arm64: versal: Add DT description for CPM5 Root port for Versal Premium
arm64: versal: Add missing DT properties to cpm_pciea
arm64: versal: rename CPM interrupt-controller
arm64: versal-net: Add support for VNX board
arm64: versal: Switch to new wwdt DT binding
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
Diffstat (limited to 'README.building.md')
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