xrt, zocl: Update commit id

Changelog:
   Initial implementation of HIP apis and objects (#7940)
   VITIS-11348 Refactor how the platform path is found per OS (#7953)
   Vitis 6479 - Changing profiling to use correct clock frequencies for compute units and monitors (#7952)
   VITIS-11415 Remove dynamic region report for Ryzen devices (#7950)
   CR-1189595: Fixed issue where memory module events are not configured correctly (#7948)
   Further support of memory module DMA events on Edge devices (#7947)
   VITIS-11339 Remove AIE start column parameter from query. Remove AIE information query from alveo device shim
   Support for memory module DMA events on client devices (#7928)
   add tct all column test (#7942)
   CR-1188254 Disable xbutil reset and program in RyzenAI 1.1 ARC2 (#7932)
   Xcl Api Replacement (#7915)
   Add iterations to df-bw to increase throughput (#7939)
   Fix incorrect return value for xclRead (#7914)

Signed-off-by: saumya garg <saumya.garg@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>

1 files changed, 1 insertions, 1 deletions

diff --git a/meta-xilinx-core/recipes-xrt/xrt/xrt.inc b/meta-xilinx-core/recipes-xrt/xrt/xrt.inc
index 1941d633..89dc87cc 100644
--- a/meta-xilinx-core/recipes-xrt/xrt/xrt.inc
+++ b/meta-xilinx-core/recipes-xrt/xrt/xrt.inc
@@ -3,7 +3,7 @@ BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '
 SRC_URI = "${REPO};${BRANCHARG};name=xrt"
 
 BRANCH= "master"
-SRCREV_xrt = "41f4221433c6b173316b61cb2e7e3ee5152d8075"
+SRCREV_xrt = "8426f5733c01018acbd8d12745bc9e5ffc4535e6"
 PV = "202320.2.17.0"
 
 SRC_URI += "git://github.com/Xilinx/dma_ip_drivers.git;branch=master;name=dma_ip_drivers;destsuffix=git/src/runtime_src/core/pcie/driver/linux/xocl/lib/libqdma;protocol=https"