summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorAppana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>2023-01-21 00:06:47 +0530
committerMark Hatle <mark.hatle@amd.com>2023-01-23 12:13:36 -0600
commitc7e45dd678d4dae2e8f7b27aa5ce13647377308d (patch)
tree8f7cb73e014f011c6343498409d722eb697dd818
parent07dbcd95be5bc3d0c40a1ca04460442cad1381e7 (diff)
downloadmeta-xilinx-c7e45dd678d4dae2e8f7b27aa5ce13647377308d.tar.gz
lopper: Update srcrev for 2023
Below are the updates lopper: lops: lop-domain-a72-prune.dts: Delete unneeded nodes from a72 domain sanity: make temporary file management cross platform safe Implementation of lopper plugin for generating config object Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com> Signed-off-by: Mark Hatle <mark.hatle@amd.com>
Diffstat
-rw-r--r--meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper/0001-lopper-Implementation-of-lopper-plugin-for-generatin.patch1106
-rw-r--r--meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper_git.bbappend3
2 files changed, 1 insertions, 1108 deletions
diff --git a/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper/0001-lopper-Implementation-of-lopper-plugin-for-generatin.patch b/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper/0001-lopper-Implementation-of-lopper-plugin-for-generatin.patch
deleted file mode 100644
index e1fc44be..00000000
--- a/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper/0001-lopper-Implementation-of-lopper-plugin-for-generatin.patch
+++ /dev/null
@@ -1,1106 +0,0 @@
1From f8af7d17252a0705687cb7c4bfe27eefdb17a986 Mon Sep 17 00:00:00 2001
2From: Madhav Bhatt <madhav.bhatt@xilinx.com>
3Date: Tue, 3 Jan 2023 11:43:37 -0800
4Subject: [PATCH] lopper: Implementation of lopper plugin for generating config
5 object
6
7Signed-off-by: Madhav Bhatt <madhav.bhatt@amd.com>
8---
9 .../assists/cfg_obj/modules/cfg_data_tpl.py | 1 +
10 .../cfg_obj/modules/cfgobj_hard_coding.py | 277 +++++++++
11 lopper/assists/cfg_obj/modules/sdtinfo.py | 193 ++++++
12 lopper/assists/cfg_obj/modules/section.py | 35 ++
13 lopper/assists/generate_config_object.py | 547 ++++++++++++++++++
14 5 files changed, 1053 insertions(+)
15 create mode 100644 lopper/assists/cfg_obj/modules/cfg_data_tpl.py
16 create mode 100644 lopper/assists/cfg_obj/modules/cfgobj_hard_coding.py
17 create mode 100644 lopper/assists/cfg_obj/modules/sdtinfo.py
18 create mode 100644 lopper/assists/cfg_obj/modules/section.py
19 create mode 100644 lopper/assists/generate_config_object.py
20
21diff --git a/lopper/assists/cfg_obj/modules/cfg_data_tpl.py b/lopper/assists/cfg_obj/modules/cfg_data_tpl.py
22new file mode 100644
23index 0000000..8b0a865
24--- /dev/null
25+++ b/lopper/assists/cfg_obj/modules/cfg_data_tpl.py
26@@ -0,0 +1 @@
27+config_object_template = '/******************************************************************************\n* Copyright (c) 2017 - 2021 Xilinx, Inc. All rights reserved.\n* SPDX-License-Identifier: MIT\n******************************************************************************/\n\n#include "xil_types.h"\n#include "pm_defs.h"\n\n#define PM_CONFIG_MASTER_SECTION_ID 0x101U\n#define PM_CONFIG_SLAVE_SECTION_ID 0x102U\n#define PM_CONFIG_PREALLOC_SECTION_ID 0x103U\n#define PM_CONFIG_POWER_SECTION_ID 0x104U\n#define PM_CONFIG_RESET_SECTION_ID 0x105U\n#define PM_CONFIG_SHUTDOWN_SECTION_ID 0x106U\n#define PM_CONFIG_SET_CONFIG_SECTION_ID 0x107U\n#define PM_CONFIG_GPO_SECTION_ID 0x108U\n\n#define PM_SLAVE_FLAG_IS_SHAREABLE 0x1U\n#define PM_MASTER_USING_SLAVE_MASK 0x2U\n\n#define PM_CONFIG_GPO1_MIO_PIN_34_MAP (1U << 10U)\n#define PM_CONFIG_GPO1_MIO_PIN_35_MAP (1U << 11U)\n#define PM_CONFIG_GPO1_MIO_PIN_36_MAP (1U << 12U)\n#define PM_CONFIG_GPO1_MIO_PIN_37_MAP (1U << 13U)\n\n#define PM_CONFIG_GPO1_BIT_2_MASK (1U << 2U)\n#define PM_CONFIG_GPO1_BIT_3_MASK (1U << 3U)\n#define PM_CONFIG_GPO1_BIT_4_MASK (1U << 4U)\n#define PM_CONFIG_GPO1_BIT_5_MASK (1U << 5U)\n\n#define SUSPEND_TIMEOUT 0xFFFFFFFFU\n\n#define PM_CONFIG_OBJECT_TYPE_BASE 0x1U\n\n<<MASTER_IPI_MASK_DEF>>\n\n#if defined (__ICCARM__)\n#pragma language=save\n#pragma language=extended\n#endif\n#if defined (__GNUC__)\n const u32 XPm_ConfigObject[] __attribute__((used, section(".sys_cfg_data"))) =\n#elif defined (__ICCARM__)\n#pragma location = ".sys_cfg_data"\n__root const u32 XPm_ConfigObject[] =\n#endif\n{\n /**********************************************************************/\n /* HEADER */\n 2, /* Number of remaining words in the header */\n 8, /* Number of sections included in config object */\n PM_CONFIG_OBJECT_TYPE_BASE, /* Type of config object as base */\n /**********************************************************************/\n /* MASTER SECTION */\n<<MASTER_SECTION_DATA>>\n /**********************************************************************/\n /* SLAVE SECTION */\n<<SLAVE_SECTION_DATA>>\n /**********************************************************************/\n /* PREALLOC SECTION */\n<<PREALLOC_SECTION_DATA>>\n /**********************************************************************/\n /* POWER SECTION */\n<<POWER_SECTION_DATA>>\n /**********************************************************************/\n /* RESET SECTION */\n<<RESET_SECTION_DATA>>\n /**********************************************************************/\n /* SET CONFIG SECTION */\n<<SET_CONFIG_SECTION_DATA>>\n /**********************************************************************/\n /* SHUTDOWN SECTION */\n<<SHUTDOWN_SECTION_DATA>>\n /**********************************************************************/\n /* GPO SECTION */\n<<GPO_SECTION_DATA>>\n};\n#if defined (__ICCARM__)\n#pragma language=restore\n#endif'
28diff --git a/lopper/assists/cfg_obj/modules/cfgobj_hard_coding.py b/lopper/assists/cfg_obj/modules/cfgobj_hard_coding.py
29new file mode 100644
30index 0000000..1d05977
31--- /dev/null
32+++ b/lopper/assists/cfg_obj/modules/cfgobj_hard_coding.py
33@@ -0,0 +1,277 @@
34+# /*
35+# * Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
36+# *
37+# * Author:
38+# * Madhav Bhatt <madhav.bhatt@amd.com>
39+# *
40+# * SPDX-License-Identifier: BSD-3-Clause
41+# */
42+
43+rpu0_as_power_management_master = True
44+rpu1_as_power_management_master = True
45+apu_as_power_management_master = True
46+rpu0_as_reset_management_master = True
47+rpu1_as_reset_management_master = True
48+apu_as_reset_management_master = True
49+rpu0_as_overlay_config_master = False
50+rpu1_as_overlay_config_master = False
51+apu_as_overlay_config_master = False
52+
53+subsys_str = "PMU Firmware:PMU|Secure Subsystem:"
54+
55+node_map = {
56+ "NODE_APU" : { "label" : "NODE_APU", "periph" : "psu_cortexa53_0", "type" : "processor" },
57+ "NODE_APU_0" : { "label" : "NODE_APU_0", "periph" : "psu_cortexa53_0", "type" : "processor" },
58+ "NODE_APU_1" : { "label" : "NODE_APU_1", "periph" : "psu_cortexa53_1", "type" : "processor" },
59+ "NODE_APU_2" : { "label" : "NODE_APU_2", "periph" : "psu_cortexa53_2", "type" : "processor" },
60+ "NODE_APU_3" : { "label" : "NODE_APU_3", "periph" : "psu_cortexa53_3", "type" : "processor" },
61+ "NODE_RPU" : { "label" : "NODE_RPU", "periph" : "psu_cortexr5_0", "type" : "processor" },
62+ "NODE_RPU_0" : { "label" : "NODE_RPU_0", "periph" : "psu_cortexr5_0", "type" : "processor" },
63+ "NODE_RPU_1" : { "label" : "NODE_RPU_1", "periph" : "psu_cortexr5_1", "type" : "processor" },
64+ "NODE_PLD" : { "label" : "NODE_PLD", "periph" : "NA", "type" : "power" },
65+ "NODE_FPD" : { "label" : "NODE_FPD", "periph" : "NA", "type" : "power" },
66+ "NODE_OCM_BANK_0" : { "label" : "NODE_OCM_BANK_0", "periph" : "psu_ocm_0", "type" : "memory", "base_addr" : [0xfffc0000]},
67+ "NODE_OCM_BANK_1" : { "label" : "NODE_OCM_BANK_1", "periph" : "psu_ocm_1", "type" : "memory", "base_addr" : [0xfffd0000]},
68+ "NODE_OCM_BANK_2" : { "label" : "NODE_OCM_BANK_2", "periph" : "psu_ocm_2", "type" : "memory", "base_addr" : [0xfffe0000]},
69+ "NODE_OCM_BANK_3" : { "label" : "NODE_OCM_BANK_3", "periph" : "psu_ocm_3", "type" : "memory", "base_addr" : [0xffff0000]},
70+ "NODE_TCM_0_A" : { "label" : "NODE_TCM_0_A", "periph" : "psu_r5_0_atcm_global", "type" : "memory", "base_addr" : [0xffe00000] },
71+ "NODE_TCM_0_B" : { "label" : "NODE_TCM_0_B", "periph" : "psu_r5_0_btcm_global", "type" : "memory", "base_addr" : [0xffe20000] },
72+ "NODE_TCM_1_A" : { "label" : "NODE_TCM_1_A", "periph" : "psu_r5_1_atcm_global", "type" : "memory", "base_addr" : [0xffe90000] },
73+ "NODE_TCM_1_B" : { "label" : "NODE_TCM_1_B", "periph" : "psu_r5_1_btcm_global", "type" : "memory", "base_addr" : [0xffeb0000] },
74+ "NODE_L2" : { "label" : "NODE_L2", "periph" : "NA", "type" : "others" },
75+ "NODE_GPU_PP_0" : { "label" : "NODE_GPU_PP_0", "periph" : "psu_gpu", "type" : "slave", "base_addr" : [0xfd4b0000] },
76+ "NODE_GPU_PP_1" : { "label" : "NODE_GPU_PP_1", "periph" : "psu_gpu", "type" : "slave", "base_addr" : [0xfd4b0000] },
77+ "NODE_USB_0" : { "label" : "NODE_USB_0", "periph" : "psu_usb_0", "type" : "slave", "base_addr" : [0xff9d0000] },
78+ "NODE_USB_1" : { "label" : "NODE_USB_1", "periph" : "psu_usb_1", "type" : "slave", "base_addr" : [0xff9e0000] },
79+ "NODE_TTC_0" : { "label" : "NODE_TTC_0", "periph" : "psu_ttc_0", "type" : "slave", "base_addr" : [0xff110000] },
80+ "NODE_TTC_1" : { "label" : "NODE_TTC_1", "periph" : "psu_ttc_1", "type" : "slave", "base_addr" : [0xff120000] },
81+ "NODE_TTC_2" : { "label" : "NODE_TTC_2", "periph" : "psu_ttc_2", "type" : "slave", "base_addr" : [0xff130000 ] },
82+ "NODE_TTC_3" : { "label" : "NODE_TTC_3", "periph" : "psu_ttc_3", "type" : "slave", "base_addr" : [0xff140000] },
83+ "NODE_SATA" : { "label" : "NODE_SATA", "periph" : "psu_sata", "type" : "slave", "base_addr" : [0xfd0c0000] },
84+ "NODE_ETH_0" : { "label" : "NODE_ETH_0", "periph" : "psu_ethernet_0", "type" : "slave", "base_addr" : [0xff0b0000] },
85+ "NODE_ETH_1" : { "label" : "NODE_ETH_1", "periph" : "psu_ethernet_1", "type" : "slave", "base_addr" : [0xff0c0000] },
86+ "NODE_ETH_2" : { "label" : "NODE_ETH_2", "periph" : "psu_ethernet_2", "type" : "slave", "base_addr" : [0xff0d0000] },
87+ "NODE_ETH_3" : { "label" : "NODE_ETH_3", "periph" : "psu_ethernet_3", "type" : "slave", "base_addr" : [0xff0e0000] },
88+ "NODE_UART_0" : { "label" : "NODE_UART_0", "periph" : "psu_uart_0", "type" : "slave", "base_addr" : [0xff000000] },
89+ "NODE_UART_1" : { "label" : "NODE_UART_1", "periph" : "psu_uart_1", "type" : "slave", "base_addr" : [0xff010000] },
90+ "NODE_SPI_0" : { "label" : "NODE_SPI_0", "periph" : "psu_spi_0", "type" : "slave", "base_addr" : [0xff040000] },
91+ "NODE_SPI_1" : { "label" : "NODE_SPI_1", "periph" : "psu_spi_1", "type" : "slave", "base_addr" : [0xff050000] },
92+ "NODE_I2C_0" : { "label" : "NODE_I2C_0", "periph" : "psu_i2c_0", "type" : "slave", "base_addr" : [0xff020000] },
93+ "NODE_I2C_1" : { "label" : "NODE_I2C_1", "periph" : "psu_i2c_1", "type" : "slave", "base_addr" : [0xff030000] },
94+ "NODE_SD_0" : { "label" : "NODE_SD_0", "periph" : "psu_sd_0", "type" : "slave", "base_addr" : [0xff160000] },
95+ "NODE_SD_1" : { "label" : "NODE_SD_1", "periph" : "psu_sd_1", "type" : "slave", "base_addr" : [0xff170000] },
96+ "NODE_DP" : { "label" : "NODE_DP", "periph" : "psu_dp", "type" : "slave", "base_addr" : [0xfd4a0000] },
97+ "NODE_GDMA" : { "label" : "NODE_GDMA", "periph" : "psu_gdma_0", "type" : "slave", "base_addr" : [0xfd500000] },
98+ "NODE_ADMA" : { "label" : "NODE_ADMA", "periph" : "psu_adma_0", "type" : "slave", "base_addr" : [0xffa80000] },
99+ "NODE_NAND" : { "label" : "NODE_NAND", "periph" : "psu_nand_0", "type" : "slave", "base_addr" : [0xff100000] },
100+ "NODE_QSPI" : { "label" : "NODE_QSPI", "periph" : "psu_qspi_0", "type" : "slave", "base_addr" : [0xff0f0000] },
101+ "NODE_GPIO" : { "label" : "NODE_GPIO", "periph" : "psu_gpio_0", "type" : "slave", "base_addr" : [0xff0a0000] },
102+ "NODE_CAN_0" : { "label" : "NODE_CAN_0", "periph" : "psu_can_0", "type" : "slave", "base_addr" : [0xff060000] },
103+ "NODE_CAN_1" : { "label" : "NODE_CAN_1", "periph" : "psu_can_1", "type" : "slave", "base_addr" : [0xff070000] },
104+ "NODE_EXTERN" : { "label" : "NODE_EXTERN", "periph" : "NA", "type" : "others" },
105+ "NODE_DDR" : { "label" : "NODE_DDR", "periph" : "psu_ddr", "type" : "memory", "base_addr" : [0x100000,0x0] },
106+ "NODE_IPI_APU" : { "label" : "NODE_IPI_APU", "periph" : "NA", "type" : "ipi" },
107+ "NODE_IPI_RPU_0" : { "label" : "NODE_IPI_RPU_0", "periph" : "NA", "type" : "ipi" },
108+ "NODE_IPI_RPU_1" : { "label" : "NODE_IPI_RPU_1", "periph" : "NA", "type" : "ipi" },
109+ "NODE_GPU" : { "label" : "NODE_GPU", "periph" : "psu_gpu", "type" : "slave", "base_addr" : [0xfd4b0000] },
110+ "NODE_PCIE" : { "label" : "NODE_PCIE", "periph" : "psu_pcie", "type" : "slave", "base_addr" : [0xfd0e0000] },
111+ "NODE_PCAP" : { "label" : "NODE_PCAP", "periph" : "NA", "type" : "slave" },
112+ "NODE_RTC" : { "label" : "NODE_RTC", "periph" : "psu_rtc", "type" : "slave", "base_addr" : [0xffa60000] },
113+ "NODE_VCU" : { "label" : "NODE_VCU", "periph" : "vcu_0", "type" : "slave" },
114+ "NODE_PL" : { "label" : "NODE_PL", "periph" : "NA", "type" : "others" },
115+}
116+
117+masters = {
118+ "psu_cortexa53_0" : {'name' : 'APU'},
119+ "psu_cortexr5_0" : {'name' : 'RPU0'},
120+ "psu_cortexr5_1" : {'name' : 'RPU1'}
121+ }
122+
123+ocm_map = {
124+ "psu_ocm_0" : { "label" : "OCM_BANK_0", "base" : 0xFFFC0000, "high" : 0xFFFCFFFF },
125+ "psu_ocm_1" : { "label" : "OCM_BANK_1", "base" : 0xFFFD0000, "high" : 0xFFFDFFFF },
126+ "psu_ocm_2" : { "label" : "OCM_BANK_2", "base" : 0xFFFE0000, "high" : 0xFFFEFFFF },
127+ "psu_ocm_3" : { "label" : "OCM_BANK_3", "base" : 0xFFFF0000, "high" : 0xFFFFFFFF }
128+}
129+
130+apu_prealloc_list = [
131+ "NODE_DDR",
132+ "NODE_L2",
133+ "NODE_OCM_BANK_0",
134+ "NODE_OCM_BANK_1",
135+ "NODE_OCM_BANK_2",
136+ "NODE_OCM_BANK_3",
137+ "NODE_I2C_0",
138+ "NODE_I2C_1",
139+ "NODE_SD_1",
140+ "NODE_QSPI",
141+ "NODE_PL"
142+ ]
143+
144+rpu_0_prealloc_list = [
145+ "NODE_TCM_0_A",
146+ "NODE_TCM_0_B",
147+ "NODE_TCM_1_A",
148+ "NODE_TCM_1_B"
149+ ]
150+
151+rpu_0_prealloc_conditional_list = [
152+ "NODE_DDR",
153+ "NODE_OCM_BANK_0",
154+ "NODE_OCM_BANK_1",
155+ "NODE_OCM_BANK_2",
156+ "NODE_OCM_BANK_3",
157+ "NODE_I2C_0",
158+ "NODE_I2C_1",
159+ "NODE_SD_1",
160+ "NODE_QSPI",
161+ "NODE_PL",
162+ "NODE_ADMA"
163+ ]
164+
165+rpu_1_prealloc_list = [
166+ "NODE_TCM_1_A",
167+ "NODE_TCM_1_B"
168+ ]
169+
170+hardcoded_proc_type = "psu_cortexa53_0"
171+
172+power_node_list = [
173+ "NODE_APU",
174+ "NODE_RPU",
175+ "NODE_FPD",
176+ "NODE_PLD"
177+ ]
178+
179+power_perms = {
180+ "NODE_APU" : [ "psu_cortexr5_0", "psu_cortexr5_1" ],
181+ "NODE_RPU" : [ "psu_cortexa53_0", "psu_cortexr5_0", "psu_cortexr5_1" ],
182+ "NODE_FPD" : [ "psu_cortexr5_0", "psu_cortexr5_1" ],
183+ "NODE_PLD" : [ "psu_cortexa53_0", "psu_cortexr5_0", "psu_cortexr5_1" ],
184+}
185+
186+reset_line_map = {
187+ "XILPM_RESET_PCIE_CFG" : { "label" : "XILPM_RESET_PCIE_CFG", "type" : "rst_periph", "node" : "NODE_PCIE" },
188+ "XILPM_RESET_PCIE_BRIDGE" : { "label" : "XILPM_RESET_PCIE_BRIDGE", "type" : "rst_periph", "node" : "NODE_PCIE" },
189+ "XILPM_RESET_PCIE_CTRL" : { "label" : "XILPM_RESET_PCIE_CTRL", "type" : "rst_periph", "node" : "NODE_PCIE" },
190+ "XILPM_RESET_DP" : { "label" : "XILPM_RESET_DP", "type" : "rst_periph", "node" : "NODE_DP" },
191+ "XILPM_RESET_SWDT_CRF" : { "label" : "XILPM_RESET_SWDT_CRF", "type" : "normal" },
192+ "XILPM_RESET_AFI_FM5" : { "label" : "XILPM_RESET_AFI_FM5", "type" : "normal" },
193+ "XILPM_RESET_AFI_FM4" : { "label" : "XILPM_RESET_AFI_FM4", "type" : "normal" },
194+ "XILPM_RESET_AFI_FM3" : { "label" : "XILPM_RESET_AFI_FM3", "type" : "normal" },
195+ "XILPM_RESET_AFI_FM2" : { "label" : "XILPM_RESET_AFI_FM2", "type" : "normal" },
196+ "XILPM_RESET_AFI_FM1" : { "label" : "XILPM_RESET_AFI_FM1", "type" : "normal" },
197+ "XILPM_RESET_AFI_FM0" : { "label" : "XILPM_RESET_AFI_FM0", "type" : "normal" },
198+ "XILPM_RESET_GDMA" : { "label" : "XILPM_RESET_GDMA", "type" : "rst_periph", "node" : "NODE_GDMA" },
199+ "XILPM_RESET_GPU_PP1" : { "label" : "XILPM_RESET_GPU_PP1", "type" : "rst_periph", "node" : "NODE_GPU_PP_1" },
200+ "XILPM_RESET_GPU_PP0" : { "label" : "XILPM_RESET_GPU_PP0", "type" : "rst_periph", "node" : "NODE_GPU_PP_0" },
201+ "XILPM_RESET_GPU" : { "label" : "XILPM_RESET_GPU", "type" : "rst_periph", "node" : "NODE_GPU" },
202+ "XILPM_RESET_GT" : { "label" : "XILPM_RESET_GT", "type" : "normal" },
203+ "XILPM_RESET_SATA" : { "label" : "XILPM_RESET_SATA", "type" : "rst_periph", "node" : "NODE_SATA" },
204+ "XILPM_RESET_ACPU3_PWRON" : { "label" : "XILPM_RESET_ACPU3_PWRON", "type" : "rst_proc", "proc" : "APU" },
205+ "XILPM_RESET_ACPU2_PWRON" : { "label" : "XILPM_RESET_ACPU2_PWRON", "type" : "rst_proc", "proc" : "APU" },
206+ "XILPM_RESET_ACPU1_PWRON" : { "label" : "XILPM_RESET_ACPU1_PWRON", "type" : "rst_proc", "proc" : "APU" },
207+ "XILPM_RESET_ACPU0_PWRON" : { "label" : "XILPM_RESET_ACPU0_PWRON", "type" : "rst_proc", "proc" : "APU" },
208+ "XILPM_RESET_APU_L2" : { "label" : "XILPM_RESET_APU_L2", "type" : "rst_proc", "proc" : "APU" },
209+ "XILPM_RESET_ACPU3" : { "label" : "XILPM_RESET_ACPU3", "type" : "rst_proc", "proc" : "APU" },
210+ "XILPM_RESET_ACPU2" : { "label" : "XILPM_RESET_ACPU2", "type" : "rst_proc", "proc" : "APU" },
211+ "XILPM_RESET_ACPU1" : { "label" : "XILPM_RESET_ACPU1", "type" : "rst_proc", "proc" : "APU" },
212+ "XILPM_RESET_ACPU0" : { "label" : "XILPM_RESET_ACPU0", "type" : "rst_proc", "proc" : "APU" },
213+ "XILPM_RESET_DDR" : { "label" : "XILPM_RESET_DDR", "type" : "rst_periph", "node" : "NODE_DDR" },
214+ "XILPM_RESET_APM_FPD" : { "label" : "XILPM_RESET_APM_FPD", "type" : "normal" },
215+ "XILPM_RESET_SOFT" : { "label" : "XILPM_RESET_SOFT", "type" : "rst_shared" },
216+ "XILPM_RESET_GEM0" : { "label" : "XILPM_RESET_GEM0", "type" : "rst_periph", "node" : "NODE_ETH_0" },
217+ "XILPM_RESET_GEM1" : { "label" : "XILPM_RESET_GEM1", "type" : "rst_periph", "node" : "NODE_ETH_1" },
218+ "XILPM_RESET_GEM2" : { "label" : "XILPM_RESET_GEM2", "type" : "rst_periph", "node" : "NODE_ETH_2" },
219+ "XILPM_RESET_GEM3" : { "label" : "XILPM_RESET_GEM3", "type" : "rst_periph", "node" : "NODE_ETH_3" },
220+ "XILPM_RESET_QSPI" : { "label" : "XILPM_RESET_QSPI", "type" : "rst_periph", "node" : "NODE_QSPI" },
221+ "XILPM_RESET_UART0" : { "label" : "XILPM_RESET_UART0", "type" : "rst_periph", "node" : "NODE_UART_0" },
222+ "XILPM_RESET_UART1" : { "label" : "XILPM_RESET_UART1", "type" : "rst_periph", "node" : "NODE_UART_1" },
223+ "XILPM_RESET_SPI0" : { "label" : "XILPM_RESET_SPI0", "type" : "rst_periph", "node" : "NODE_SPI_0" },
224+ "XILPM_RESET_SPI1" : { "label" : "XILPM_RESET_SPI1", "type" : "rst_periph", "node" : "NODE_SPI_1" },
225+ "XILPM_RESET_SDIO0" : { "label" : "XILPM_RESET_SDIO0", "type" : "normal" },
226+ "XILPM_RESET_SDIO1" : { "label" : "XILPM_RESET_SDIO1", "type" : "normal" },
227+ "XILPM_RESET_CAN0" : { "label" : "XILPM_RESET_CAN0", "type" : "rst_periph", "node" : "NODE_CAN_0" },
228+ "XILPM_RESET_CAN1" : { "label" : "XILPM_RESET_CAN1", "type" : "rst_periph", "node" : "NODE_CAN_1" },
229+ "XILPM_RESET_I2C0" : { "label" : "XILPM_RESET_I2C0", "type" : "rst_periph", "node" : "NODE_I2C_0" },
230+ "XILPM_RESET_I2C1" : { "label" : "XILPM_RESET_I2C1", "type" : "rst_periph", "node" : "NODE_I2C_1" },
231+ "XILPM_RESET_TTC0" : { "label" : "XILPM_RESET_TTC0", "type" : "rst_periph", "node" : "NODE_TTC_0" },
232+ "XILPM_RESET_TTC1" : { "label" : "XILPM_RESET_TTC1", "type" : "rst_periph", "node" : "NODE_TTC_1" },
233+ "XILPM_RESET_TTC2" : { "label" : "XILPM_RESET_TTC2", "type" : "rst_periph", "node" : "NODE_TTC_2" },
234+ "XILPM_RESET_TTC3" : { "label" : "XILPM_RESET_TTC3", "type" : "rst_periph", "node" : "NODE_TTC_3" },
235+ "XILPM_RESET_SWDT_CRL" : { "label" : "XILPM_RESET_SWDT_CRL", "type" : "normal" },
236+ "XILPM_RESET_NAND" : { "label" : "XILPM_RESET_NAND", "type" : "rst_periph", "node" : "NODE_NAND" },
237+ "XILPM_RESET_ADMA" : { "label" : "XILPM_RESET_ADMA", "type" : "rst_periph", "node" : "NODE_ADMA" },
238+ "XILPM_RESET_GPIO" : { "label" : "XILPM_RESET_GPIO", "type" : "normal" },
239+ "XILPM_RESET_IOU_CC" : { "label" : "XILPM_RESET_IOU_CC", "type" : "normal" },
240+ "XILPM_RESET_TIMESTAMP" : { "label" : "XILPM_RESET_TIMESTAMP", "type" : "normal" },
241+ "XILPM_RESET_RPU_R50" : { "label" : "XILPM_RESET_RPU_R50", "type" : "rst_proc", "proc" : "RPU_0" },
242+ "XILPM_RESET_RPU_R51" : { "label" : "XILPM_RESET_RPU_R51", "type" : "rst_proc", "proc" : "RPU_1" },
243+ "XILPM_RESET_RPU_AMBA" : { "label" : "XILPM_RESET_RPU_AMBA", "type" : "rst_proc", "proc" : "RPU" },
244+ "XILPM_RESET_OCM" : { "label" : "XILPM_RESET_OCM", "type" : "rst_periph", "node" : "NODE_OCM_BANK_0" },
245+ "XILPM_RESET_RPU_PGE" : { "label" : "XILPM_RESET_RPU_PGE", "type" : "rst_proc", "proc" : "RPU" },
246+ "XILPM_RESET_USB0_CORERESET" : { "label" : "XILPM_RESET_USB0_CORERESET", "type" : "rst_periph", "node" : "NODE_USB_0" },
247+ "XILPM_RESET_USB1_CORERESET" : { "label" : "XILPM_RESET_USB1_CORERESET", "type" : "rst_periph", "node" : "NODE_USB_1" },
248+ "XILPM_RESET_USB0_HIBERRESET" : { "label" : "XILPM_RESET_USB0_HIBERRESET", "type" : "rst_periph", "node" : "NODE_USB_0" },
249+ "XILPM_RESET_USB1_HIBERRESET" : { "label" : "XILPM_RESET_USB1_HIBERRESET", "type" : "rst_periph", "node" : "NODE_USB_1" },
250+ "XILPM_RESET_USB0_APB" : { "label" : "XILPM_RESET_USB0_APB", "type" : "rst_periph", "node" : "NODE_USB_0" },
251+ "XILPM_RESET_USB1_APB" : { "label" : "XILPM_RESET_USB1_APB", "type" : "rst_periph", "node" : "NODE_USB_1" },
252+ "XILPM_RESET_IPI" : { "label" : "XILPM_RESET_IPI", "type" : "rst_shared" },
253+ "XILPM_RESET_APM_LPD" : { "label" : "XILPM_RESET_APM_LPD", "type" : "normal" },
254+ "XILPM_RESET_RTC" : { "label" : "XILPM_RESET_RTC", "type" : "rst_periph", "node" : "NODE_RTC" },
255+ "XILPM_RESET_SYSMON" : { "label" : "XILPM_RESET_SYSMON", "type" : "NA" },
256+ "XILPM_RESET_AFI_FM6" : { "label" : "XILPM_RESET_AFI_FM6", "type" : "normal" },
257+ "XILPM_RESET_LPD_SWDT" : { "label" : "XILPM_RESET_LPD_SWDT", "type" : "normal" },
258+ "XILPM_RESET_FPD" : { "label" : "XILPM_RESET_FPD", "type" : "rpu_only" },
259+ "XILPM_RESET_RPU_DBG1" : { "label" : "XILPM_RESET_RPU_DBG1", "type" : "rst_proc", "proc" : "RPU" },
260+ "XILPM_RESET_RPU_DBG0" : { "label" : "XILPM_RESET_RPU_DBG0", "type" : "rst_proc", "proc" : "RPU" },
261+ "XILPM_RESET_DBG_LPD" : { "label" : "XILPM_RESET_DBG_LPD", "type" : "normal" },
262+ "XILPM_RESET_DBG_FPD" : { "label" : "XILPM_RESET_DBG_FPD", "type" : "normal" },
263+ "XILPM_RESET_APLL" : { "label" : "XILPM_RESET_APLL", "type" : "rst_proc", "proc" : "APU" },
264+ "XILPM_RESET_DPLL" : { "label" : "XILPM_RESET_DPLL", "type" : "rst_shared" },
265+ "XILPM_RESET_VPLL" : { "label" : "XILPM_RESET_VPLL", "type" : "rst_shared" },
266+ "XILPM_RESET_IOPLL" : { "label" : "XILPM_RESET_IOPLL", "type" : "rst_shared" },
267+ "XILPM_RESET_RPLL" : { "label" : "XILPM_RESET_RPLL", "type" : "rst_proc", "proc" : "RPU" },
268+ "XILPM_RESET_GPO3_PL_0" : { "label" : "XILPM_RESET_GPO3_PL_0", "type" : "normal" },
269+ "XILPM_RESET_GPO3_PL_1" : { "label" : "XILPM_RESET_GPO3_PL_1", "type" : "normal" },
270+ "XILPM_RESET_GPO3_PL_2" : { "label" : "XILPM_RESET_GPO3_PL_2", "type" : "normal" },
271+ "XILPM_RESET_GPO3_PL_3" : { "label" : "XILPM_RESET_GPO3_PL_3", "type" : "normal" },
272+ "XILPM_RESET_GPO3_PL_4" : { "label" : "XILPM_RESET_GPO3_PL_4", "type" : "normal" },
273+ "XILPM_RESET_GPO3_PL_5" : { "label" : "XILPM_RESET_GPO3_PL_5", "type" : "normal" },
274+ "XILPM_RESET_GPO3_PL_6" : { "label" : "XILPM_RESET_GPO3_PL_6", "type" : "normal" },
275+ "XILPM_RESET_GPO3_PL_7" : { "label" : "XILPM_RESET_GPO3_PL_7", "type" : "normal" },
276+ "XILPM_RESET_GPO3_PL_8" : { "label" : "XILPM_RESET_GPO3_PL_8", "type" : "normal" },
277+ "XILPM_RESET_GPO3_PL_9" : { "label" : "XILPM_RESET_GPO3_PL_9", "type" : "normal" },
278+ "XILPM_RESET_GPO3_PL_10" : { "label" : "XILPM_RESET_GPO3_PL_10", "type" : "normal" },
279+ "XILPM_RESET_GPO3_PL_11" : { "label" : "XILPM_RESET_GPO3_PL_11", "type" : "normal" },
280+ "XILPM_RESET_GPO3_PL_12" : { "label" : "XILPM_RESET_GPO3_PL_12", "type" : "normal" },
281+ "XILPM_RESET_GPO3_PL_13" : { "label" : "XILPM_RESET_GPO3_PL_13", "type" : "normal" },
282+ "XILPM_RESET_GPO3_PL_14" : { "label" : "XILPM_RESET_GPO3_PL_14", "type" : "normal" },
283+ "XILPM_RESET_GPO3_PL_15" : { "label" : "XILPM_RESET_GPO3_PL_15", "type" : "normal" },
284+ "XILPM_RESET_GPO3_PL_16" : { "label" : "XILPM_RESET_GPO3_PL_16", "type" : "normal" },
285+ "XILPM_RESET_GPO3_PL_17" : { "label" : "XILPM_RESET_GPO3_PL_17", "type" : "normal" },
286+ "XILPM_RESET_GPO3_PL_18" : { "label" : "XILPM_RESET_GPO3_PL_18", "type" : "normal" },
287+ "XILPM_RESET_GPO3_PL_19" : { "label" : "XILPM_RESET_GPO3_PL_19", "type" : "normal" },
288+ "XILPM_RESET_GPO3_PL_20" : { "label" : "XILPM_RESET_GPO3_PL_20", "type" : "normal" },
289+ "XILPM_RESET_GPO3_PL_21" : { "label" : "XILPM_RESET_GPO3_PL_21", "type" : "normal" },
290+ "XILPM_RESET_GPO3_PL_22" : { "label" : "XILPM_RESET_GPO3_PL_22", "type" : "normal" },
291+ "XILPM_RESET_GPO3_PL_23" : { "label" : "XILPM_RESET_GPO3_PL_23", "type" : "normal" },
292+ "XILPM_RESET_GPO3_PL_24" : { "label" : "XILPM_RESET_GPO3_PL_24", "type" : "normal" },
293+ "XILPM_RESET_GPO3_PL_25" : { "label" : "XILPM_RESET_GPO3_PL_25", "type" : "normal" },
294+ "XILPM_RESET_GPO3_PL_26" : { "label" : "XILPM_RESET_GPO3_PL_26", "type" : "normal" },
295+ "XILPM_RESET_GPO3_PL_27" : { "label" : "XILPM_RESET_GPO3_PL_27", "type" : "normal" },
296+ "XILPM_RESET_GPO3_PL_28" : { "label" : "XILPM_RESET_GPO3_PL_28", "type" : "normal" },
297+ "XILPM_RESET_GPO3_PL_29" : { "label" : "XILPM_RESET_GPO3_PL_29", "type" : "normal" },
298+ "XILPM_RESET_GPO3_PL_30" : { "label" : "XILPM_RESET_GPO3_PL_30", "type" : "normal" },
299+ "XILPM_RESET_GPO3_PL_31" : { "label" : "XILPM_RESET_GPO3_PL_31", "type" : "normal" },
300+ "XILPM_RESET_RPU_LS" : { "label" : "XILPM_RESET_RPU_LS", "type" : "rst_proc", "proc" : "RPU" },
301+ "XILPM_RESET_PS_ONLY" : { "label" : "XILPM_RESET_PS_ONLY", "type" : "normal" },
302+ "XILPM_RESET_PL" : { "label" : "XILPM_RESET_PL", "type" : "normal" },
303+ "XILPM_RESET_GPIO5_EMIO_92" : { "label" : "XILPM_RESET_GPIO5_EMIO_92", "type" : "normal" },
304+ "XILPM_RESET_GPIO5_EMIO_93" : { "label" : "XILPM_RESET_GPIO5_EMIO_93", "type" : "normal" },
305+ "XILPM_RESET_GPIO5_EMIO_94" : { "label" : "XILPM_RESET_GPIO5_EMIO_94", "type" : "normal" },
306+ "XILPM_RESET_GPIO5_EMIO_95" : { "label" : "XILPM_RESET_GPIO5_EMIO_95", "type" : "normal" },
307+}
308+
309+gpo_nums = [2,3,4,5]
310+
311diff --git a/lopper/assists/cfg_obj/modules/sdtinfo.py b/lopper/assists/cfg_obj/modules/sdtinfo.py
312new file mode 100644
313index 0000000..9417b0c
314--- /dev/null
315+++ b/lopper/assists/cfg_obj/modules/sdtinfo.py
316@@ -0,0 +1,193 @@
317+# /*
318+# * Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
319+# *
320+# * Author:
321+# * Madhav Bhatt <madhav.bhatt@amd.com>
322+# *
323+# * SPDX-License-Identifier: BSD-3-Clause
324+# */
325+
326+import cfgobj_hard_coding as chc
327+
328+class SdtInfo:
329+ __sdt__ = None
330+ masters = {}
331+ ocm_high_value = None
332+ ocm_base_value = None
333+ gpos = {}
334+ rpu0_as_power_management_master = False
335+ rpu1_as_power_management_master = False
336+ apu_as_power_management_master = False
337+ rpu0_as_reset_management_master = False
338+ rpu1_as_reset_management_master = False
339+ apu_as_reset_management_master = False
340+ rpu0_as_overlay_config_master = False
341+ rpu1_as_overlay_config_master = False
342+ apu_as_overlay_config_master = False
343+ subsys_str = None
344+ existing_proc_type = None
345+ proc_type = None
346+
347+ def __get_cpu_name(self, node):
348+ try:
349+ cpu_name = node["xlnx,cpu-name"].value
350+ except:
351+ cpu_name = ""
352+ return cpu_name
353+
354+ def __is_master_defined(self, master):
355+ found_master = False
356+ subsys_str = self.subsys_str
357+ subsys_list = subsys_str.split("|")
358+ for subsys in subsys_list:
359+ if master in subsys.split(":")[1].split(";"):
360+ found_master = True
361+ return found_master
362+
363+ def __get_masters(self):
364+ masters_tmp = {}
365+ for master in chc.masters.keys():
366+ for node in self.__sdt__.tree:
367+ if chc.masters[master]["name"] in self.__get_cpu_name(node):
368+ if self.__is_master_defined(master):
369+ master_tmp[master] = chc.masters[master]
370+ if len(masters_tmp) != 0:
371+ self.masters = maaster_tmp
372+ else:
373+ self.masters = chc.masters
374+ return
375+
376+
377+ def __get_ip_name(self, node):
378+ try:
379+ ip_name = node['xlnx,ip-name'].value
380+ except:
381+ ip_name = None
382+ return ip_name
383+
384+ def __parse_ipi_bit_pos(self):
385+ ip_name = []
386+ for node in self.__sdt__.tree:
387+ ip_name = self.__get_ip_name(node)
388+ if ip_name != None and "psu_ipi" in ip_name:
389+ for master in self.masters:
390+ if self.masters[master]["name"] in self.__get_cpu_name(node):
391+ self.masters[master]["ipi_bit_pos"] = node["xlnx,bit-position"].value[0]
392+ self.masters[master]["is_ipi_present"] = True
393+ return
394+
395+
396+ def __parse_gpo_info(self):
397+ ip_name = []
398+ for node in self.__sdt__.tree:
399+ ip_name = self.__get_ip_name(node)
400+ if ip_name != None and "psu_pmu_iomodule" in ip_name:
401+ for num in chc.gpo_nums:
402+ gpo_tmp = {}
403+ enable_prop_str = "xlnx,gpo" + str(num) + "-enable"
404+ polarity_prop_str = "xlnx,gpo" + str(num) + "-polarity"
405+ try:
406+ gpo_tmp["enable"] = node[enable_prop_str].value[0]
407+ except:
408+ gpo_tmp["enable"] = 0
409+ if 1 == gpo_tmp["enable"]:
410+ gpo_tmp["polarity"] = node[polarity_prop_str].value[0]
411+ else:
412+ gpo_tmp["polarity"] = 0
413+ self.gpos["gpo" + str(num)] = gpo_tmp
414+ break
415+ return
416+
417+ def __parse_ocm_base_high(self):
418+ ip_name = []
419+ for node in self.__sdt__.tree:
420+ if len(node.child_nodes) > 0:
421+ for child_node in node.child_nodes.values():
422+ ip_name = self.__get_ip_name(child_node)
423+ if ip_name != None and "psu_ocm_ram_0" in ip_name:
424+ base = child_node["reg"].value[1]
425+ size = child_node["reg"].value[3]
426+ self.ocm_base_value = base
427+ self.ocm_high_value = base + size - 1
428+ break
429+ return
430+
431+ def __parse_slaves_for_master(self):
432+ nodes_temp = self.__sdt__.tree
433+ nodelist = {}
434+ for node in nodes_temp:
435+ temp = node.name.split('@')
436+ try:
437+ nodelist[int(temp[1], 16)] = temp[0]
438+ except:
439+ None
440+ nodes = self.__sdt__.tree.nodes('/cpu.*')
441+ for node in nodes:
442+ slaves = []
443+ try:
444+ if node.propval('reg') != '':
445+ if 'cpus,cluster' in node["compatible"].value:
446+ cnt = 0
447+ addr_cell_size = node["#ranges-address-cells"].value[0]
448+ size_cell_size = node["#ranges-size-cells"].value[0]
449+ while cnt < len(node["address-map"].value):
450+ addr = 0
451+ for cell_num in range(addr_cell_size):
452+ addr = addr << 16 | node["address-map"].value[cnt + cell_num]
453+ cnt += (2 * addr_cell_size) + size_cell_size + 1
454+ for key in chc.node_map.keys():
455+ try:
456+ for base_addr in chc.node_map[key]["base_addr"]:
457+ if base_addr == addr:
458+ periph = ""
459+ if "psu_ocm_" in chc.node_map[key]["periph"]:
460+ periph = "psu_ocm_ram_0"
461+ elif "psu_ddr" in chc.node_map[key]["periph"]:
462+ if "cpus-a53" in node.name:
463+ periph = "psu_ddr_0"
464+ elif "cpus-r5" in node.name:
465+ periph = "psu_r5_ddr_0"
466+ else:
467+ periph = chc.node_map[key]["periph"]
468+ if periph not in slaves:
469+ slaves.append(periph)
470+ except:
471+ None
472+ if node.name == "cpus-a53@0":
473+ self.masters["psu_cortexa53_0"]["slaves"] = slaves
474+ elif node.name == "cpus-r5@1":
475+ self.masters["psu_cortexr5_0"]["slaves"] = slaves
476+ elif node.name == "cpus-r5@2":
477+ self.masters["psu_cortexr5_1"]["slaves"] = slaves
478+ except:
479+ None
480+
481+ def __get_proc_type(self, options):
482+ try:
483+ self.proc_type = options['args'][1]
484+ except:
485+ self.proc_type = chc.hardcoded_proc_type
486+ return
487+
488+ def __init__(self, sdt, options):
489+ self.__sdt__ = sdt
490+ self.__get_proc_type(options)
491+
492+ # Hard coded values
493+ self.rpu0_as_power_management_master = chc.rpu0_as_power_management_master
494+ self.rpu1_as_power_management_master = chc.rpu1_as_power_management_master
495+ self.apu_as_power_management_master = chc.apu_as_power_management_master
496+ self.rpu0_as_reset_management_master = chc.rpu0_as_reset_management_master
497+ self.rpu1_as_reset_management_master = chc.rpu1_as_reset_management_master
498+ self.apu_as_reset_management_master = chc.apu_as_reset_management_master
499+ self.rpu0_as_overlay_config_master = chc.rpu0_as_overlay_config_master
500+ self.rpu1_as_overlay_config_master = chc.rpu1_as_overlay_config_master
501+ self.apu_as_overlay_config_master = chc.apu_as_overlay_config_master
502+ self.subsys_str = chc.subsys_str
503+
504+ # Parsing values from SDT
505+ self.__get_masters()
506+ self.__parse_slaves_for_master()
507+ self.__parse_ipi_bit_pos()
508+ self.__parse_ocm_base_high()
509+ self.__parse_gpo_info()
510diff --git a/lopper/assists/cfg_obj/modules/section.py b/lopper/assists/cfg_obj/modules/section.py
511new file mode 100644
512index 0000000..912edfd
513--- /dev/null
514+++ b/lopper/assists/cfg_obj/modules/section.py
515@@ -0,0 +1,35 @@
516+# /*
517+# * Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
518+# *
519+# * Author:
520+# * Madhav Bhatt <madhav.bhatt@amd.com>
521+# *
522+# * SPDX-License-Identifier: BSD-3-Clause
523+# */
524+
525+class Section:
526+ __section_identifier = ""
527+ __section_file_name = None
528+ __section_parsing_cb = None
529+ __sdtinfo_obj = None
530+
531+ def __init__(self, identifier, section_parsing_cb, sdtinfo_obj):
532+ self.__section_identifier = identifier
533+ self.__section_parsing_cb = section_parsing_cb
534+ self.__sdtinfo_obj = sdtinfo_obj
535+
536+ def replace_section(self, out_lines):
537+ data_lines = self.__section_parsing_cb(self.__sdtinfo_obj)
538+ line_num = 0
539+ #print(out_lines)
540+ for out_line in out_lines:
541+ if self.__section_identifier in out_line:
542+ out_lines.pop(line_num)
543+ break
544+ line_num += 1
545+ if line_num == len(out_lines):
546+ return out_lines
547+ for data_line in data_lines:
548+ out_lines.insert(line_num, data_line)
549+ line_num += 1
550+ return out_lines
551diff --git a/lopper/assists/generate_config_object.py b/lopper/assists/generate_config_object.py
552new file mode 100644
553index 0000000..81b1b78
554--- /dev/null
555+++ b/lopper/assists/generate_config_object.py
556@@ -0,0 +1,547 @@
557+# /*
558+# * Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
559+# *
560+# * Author:
561+# * Madhav Bhatt <madhav.bhatt@amd.com>
562+# *
563+# * SPDX-License-Identifier: BSD-3-Clause
564+# */
565+
566+import sys
567+import os
568+import re
569+
570+sys.path.append(os.path.dirname(__file__))
571+sys.path.append(os.path.dirname(__file__) + "/cfg_obj/modules/")
572+
573+from section import Section
574+import cfgobj_hard_coding as chc
575+from sdtinfo import SdtInfo
576+import cfg_data_tpl
577+
578+def props():
579+ return ["id", "file_ext"]
580+
581+def id():
582+ return "xlnx,output,cfgobj"
583+
584+def file_ext():
585+ return ".c"
586+
587+def is_compat(node, compat_id):
588+ if re.search("module,generate_config_object", compat_id):
589+ return cfg_obj_write
590+ return ""
591+
592+def get_slaves_for_master(sdtinfo_obj, master):
593+ try:
594+ slave_list = sdtinfo_obj.masters[master]["slaves"]
595+ except:
596+ slave_list = []
597+ return slave_list
598+
599+def is_rpu_lockstep(sdtinfo_obj):
600+ subsys_str = sdtinfo_obj.subsys_str
601+ found_rpu0 = False
602+ found_rpu1 = False
603+
604+ subsys_list = subsys_str.split("|")
605+ for subsys in subsys_list:
606+ if "RPU0" in subsys.split(":")[1].split(";"):
607+ found_rpu0 = True
608+ if "RPU1" in subsys.split(":")[1].split(";"):
609+ found_rpu1 = True
610+ if found_rpu0 == True and found_rpu1 == False:
611+ return True
612+ else:
613+ return False
614+
615+def mask_to_str(mask):
616+ return "0x%08X"%mask
617+
618+def is_ipi_present(master, sdtinfo_obj):
619+ try:
620+ if sdtinfo_obj.masters[master]["is_ipi_present"] == True:
621+ return True
622+ else:
623+ return False
624+ except:
625+ return False
626+
627+def get_ipi_mask(master, sdtinfo_obj):
628+ if is_ipi_present(master, sdtinfo_obj) == True:
629+ bit_pos = sdtinfo_obj.masters[master]["ipi_bit_pos"]
630+ return (1<<bit_pos)
631+ else:
632+ return 0
633+
634+def get_ipi_mask_txt(master, sdtinfo_obj):
635+ if is_ipi_present(master, sdtinfo_obj) == True:
636+ return "PM_CONFIG_IPI_" + master.upper() + "_MASK"
637+ else:
638+ return ""
639+
640+def get_all_masters_mask_txt(sdtinfo_obj):
641+ macro_list = []
642+ for master in sdtinfo_obj.masters.keys():
643+ if is_ipi_present(master, sdtinfo_obj) == True:
644+ macro_list.append(get_ipi_mask_txt(master, sdtinfo_obj))
645+ if len(macro_list) > 0:
646+ return " | ".join(macro_list)
647+ else:
648+ return "0U"
649+
650+def get_all_other_masters_mask_txt(master_name, sdtinfo_obj):
651+ macro_list = []
652+ for master in sdtinfo_obj.masters.keys():
653+ if (master != master_name) and (is_ipi_present(master, sdtinfo_obj) == True):
654+ if "psu_cortexa53_0" == master_name:
655+ if sdtinfo_obj.rpu0_as_power_management_master == False and \
656+ "psu_cortexr5_0" == master:
657+ continue
658+ if sdtinfo_obj.rpu1_as_power_management_master == False and \
659+ False == is_rpu_lockstep(sdtinfo_obj) and "psu_cortexr5_1" == master:
660+ continue
661+ elif "psu_cortexr5_0" == master_name:
662+ if sdtinfo_obj.apu_as_power_management_master == False and \
663+ "psu_cortexa53_0" == master:
664+ continue
665+ if sdtinfo_obj.rpu1_as_power_management_master == False and \
666+ False == is_rpu_lockstep(sdtinfo_obj) and "psu_cortexr5_1" == master:
667+ continue
668+ elif False == is_rpu_lockstep(sdtinfo_obj) and "psu_cortexr5_1" == master_name:
669+ if sdtinfo_obj.apu_as_power_management_master == False and \
670+ "psu_cortexa53_0" == master:
671+ continue
672+ if sdtinfo_obj.rpu0_as_power_management_master == False and \
673+ "psu_cortexr5_0" == master:
674+ continue
675+ macro_list.append(get_ipi_mask_txt(master, sdtinfo_obj))
676+ if len(macro_list) > 0:
677+ return " | ".join(macro_list)
678+ else:
679+ return "0U"
680+
681+def get_slave_perm_mask_txt(periph, sdtinfo_obj):
682+ macro_list = []
683+ for master in sdtinfo_obj.masters.keys():
684+ slave_list = get_slaves_for_master(sdtinfo_obj, master)
685+ for slave in slave_list:
686+ if periph == slave and (is_ipi_present(master, sdtinfo_obj) == True):
687+ macro_list.append(get_ipi_mask_txt(master, sdtinfo_obj))
688+ if len(macro_list) > 0:
689+ return " | ".join(macro_list)
690+ else:
691+ return "0U"
692+
693+
694+def get_slave_perm_mask(periph, sdtinfo_obj):
695+ perm_mask = 0x00000000
696+ for master in sdtinfo_obj.masters.keys():
697+ slave_list = get_slaves_for_master(sdtinfo_obj, master)
698+ for slave in slave_list:
699+ if re.search(periph,slave) != None and (is_ipi_present(master, sdtinfo_obj) == True):
700+ perm_mask = perm_mask | get_ipi_mask(master, sdtinfo_obj)
701+ return perm_mask
702+
703+def get_tcm_r5_perm_mask(r5_proc, tcm_bank, sdtinfo_obj):
704+ perm_mask = 0x00000000
705+ if "psu_cortexr5_0" == r5_proc:
706+ if is_rpu_lockstep(sdtinfo_obj) == True:
707+ perm_mask = get_ipi_mask(r5_proc, sdtinfo_obj)
708+ else:
709+ if tcm_bank == "psu_r5_0_atcm_global" or tcm_bank == "psu_r5_0_btcm_global":
710+ perm_mask = get_ipi_mask(r5_proc, sdtinfo_obj)
711+ elif r5_proc == "psu_cortexr5_1":
712+ if is_rpu_lockstep(sdtinfo_obj) == True:
713+ perm_mask = 0x00000000
714+ else:
715+ if tcm_bank == "psu_r5_1_atcm_global" or tcm_bank == "psu_r5_1_btcm_global":
716+ perm_mask = get_ipi_mask(r5_proc, sdtinfo_obj)
717+ else:
718+ perm_mask = 0x00000000
719+ return perm_mask
720+
721+def convert_ipi_mask_to_txt(ipi_mask, sdtinfo_obj):
722+ macro_list = []
723+ for master in sdtinfo_obj.masters.keys():
724+ if ((ipi_mask & get_ipi_mask(master, sdtinfo_obj)) != 0) and is_ipi_present(master, sdtinfo_obj) == True:
725+ macro_list.append(get_ipi_mask_txt(master, sdtinfo_obj))
726+ if len(macro_list) > 0:
727+ return " | ".join(macro_list)
728+ else:
729+ return "0U"
730+
731+def get_tcm_perm_mask(tcm, sdtinfo_obj):
732+ perm_mask = 0x00000000
733+ for master in sdtinfo_obj.masters.keys():
734+ if re.search("psu_cortexr5_*", master) != None:
735+ perm_mask = perm_mask | get_tcm_r5_perm_mask(master, tcm, sdtinfo_obj)
736+ else:
737+ slave_list = get_slaves_for_master(sdtinfo_obj, master)
738+ for slave in slave_list:
739+ if tcm == slave:
740+ perm_mask = perm_mask | get_ipi_mask(master, sdtinfo_obj)
741+ return perm_mask
742+
743+def get_ocm_perm_mask(ocm, sdtinfo_obj):
744+ perm_mask = 0x00000000
745+ island_base = sdtinfo_obj.ocm_base_value
746+ island_high = sdtinfo_obj.ocm_high_value
747+ for master in sdtinfo_obj.masters.keys():
748+ if "psu_ocm_ram_0" in get_slaves_for_master(sdtinfo_obj, master):
749+ base_val = sdtinfo_obj.ocm_base_value
750+ high_val = sdtinfo_obj.ocm_high_value
751+ if ((island_base >= base_val) and (island_base <= high_val)) or ((island_high >= base_val) and (island_high <= high_val)):
752+ perm_mask = perm_mask | get_ipi_mask(master, sdtinfo_obj)
753+ return perm_mask
754+
755+def get_mem_perm_mask(mem, sdtinfo_obj):
756+ perm_mask = 0x00000000
757+ if "psu_ddr" in mem:
758+ perm_mask = get_slave_perm_mask("psu_ddr_", sdtinfo_obj) | get_slave_perm_mask("psu_r5_ddr_", sdtinfo_obj)
759+ elif "psu_ocm_" in mem:
760+ perm_mask = get_ocm_perm_mask(mem, sdtinfo_obj)
761+ elif re.search("psu_r5_.*tcm_global", mem) != None:
762+ perm_mask = get_tcm_perm_mask(mem, sdtinfo_obj)
763+ else:
764+ perm_mask = 0x00
765+ return perm_mask
766+
767+def get_power_domain_perm_mask_txt(pwr_domain, sdtinfo_obj):
768+ macro_list = []
769+ pwr_perm_masters = chc.power_perms[pwr_domain]
770+ for master in pwr_perm_masters:
771+ if master in sdtinfo_obj.masters.keys() and is_ipi_present(master, sdtinfo_obj) == True:
772+ if (sdtinfo_obj.apu_as_power_management_master == False) and ("psu_cortexa53_0" == master):
773+ continue
774+ elif (sdtinfo_obj.rpu0_as_power_management_master == False) and ("psu_cortexr5_0" == master):
775+ continue
776+ elif (sdtinfo_obj.rpu1_as_power_management_master == False) and ("psu_cortexr5_1" == master):
777+ continue
778+ macro_list.append(get_ipi_mask_txt(master, sdtinfo_obj))
779+ if (pwr_domain == "NODE_FPD" or pwr_domain == "NODE_APU") and (len(macro_list) == 0):
780+ macro_list.append("psu_cortexa53_0")
781+ if len(macro_list) > 0:
782+ return " | ".join(macro_list)
783+ else:
784+ return "0U"
785+
786+def is_all_master_enabled(master_type, sdtinfo_obj):
787+ if "power" == master_type:
788+ rpu0_as_master = sdtinfo_obj.rpu0_as_power_management_master
789+ rpu1_as_master = sdtinfo_obj.rpu1_as_power_management_master
790+ apu_as_master = sdtinfo_obj.apu_as_power_management_master
791+ elif "reset" == master_type:
792+ rpu0_as_master = sdtinfo_obj.rpu0_as_reset_management_master
793+ rpu1_as_master = sdtinfo_obj.rpu1_as_reset_management_master
794+ apu_as_master = sdtinfo_obj.apu_as_reset_management_master
795+ else:
796+ return -1
797+ if rpu0_as_master == True and apu_as_master == True:
798+ if is_rpu_lockstep(sdtinfo_obj) == False:
799+ if rpu1_as_master == True:
800+ return 1
801+ else:
802+ return 0
803+ else:
804+ return 1
805+ else:
806+ return 0
807+
808+
809+def get_list_of_management_master(master_type, sdtinfo_obj):
810+ macro_list = []
811+ if "power" == master_type:
812+ rpu0_as_master = sdtinfo_obj.rpu0_as_power_management_master
813+ rpu1_as_master = sdtinfo_obj.rpu1_as_power_management_master
814+ apu_as_master = sdtinfo_obj.apu_as_power_management_master
815+ elif "reset" == master_type:
816+ rpu0_as_master = sdtinfo_obj.rpu0_as_reset_management_master
817+ rpu1_as_master = sdtinfo_obj.rpu1_as_reset_management_master
818+ apu_as_master = sdtinfo_obj.apu_as_reset_management_master
819+ elif "overlay_config" == master_type:
820+ rpu0_as_master = sdtinfo_obj.rpu0_as_overlay_config_master
821+ rpu1_as_master = sdtinfo_obj.rpu1_as_overlay_config_master
822+ apu_as_master = sdtinfo_obj.apu_as_overlay_config_master
823+ else:
824+ return "0U"
825+ for master in sdtinfo_obj.masters.keys():
826+ if is_ipi_present(master, sdtinfo_obj) != 0:
827+ if (apu_as_master == False) and ("psu_cortexa53_0" == master):
828+ continue
829+ elif (rpu0_as_master == False) and ("psu_cortexr5_0" == master):
830+ continue
831+ elif (rpu1_as_master == False) and ("psu_cortexr5_1" == master):
832+ continue
833+ macro_list.append(get_ipi_mask_txt(master, sdtinfo_obj))
834+ if len(macro_list) > 0:
835+ return " | ".join(macro_list)
836+ else:
837+ return "0U"
838+
839+def generate_master_ipi_mask_def(sdtinfo_obj):
840+ out_lines = ["\n"]
841+ for master in sdtinfo_obj.masters.keys():
842+ if is_ipi_present(master, sdtinfo_obj) == True:
843+ out_lines.append("#define " + get_ipi_mask_txt(master, sdtinfo_obj) + " " + mask_to_str(get_ipi_mask(master, sdtinfo_obj)) + "\n")
844+ out_lines.append("\n\n")
845+ return out_lines
846+
847+def get_prealloc_for_master_txt(master_name, prealloc_list, sdtinfo_obj):
848+ node_count = 0
849+ master_prealloc_txt = []
850+ if is_ipi_present(master_name, sdtinfo_obj) != "":
851+ master_mask = get_ipi_mask_txt(master_name, sdtinfo_obj)
852+ master_prealloc_txt.append("\t/* Prealloc for " + master_name + " */\n")
853+ master_prealloc_txt.append("\t" + master_mask + ",\n")
854+ for key in prealloc_list:
855+ periph_perms = chc.node_map[key]['perms']
856+ periph_name = chc.node_map[key]['periph']
857+ periph_type = chc.node_map[key]['type']
858+ periph_label = chc.node_map[key]['label']
859+ if master_mask in periph_perms:
860+ master_prealloc_txt.append("\t" + periph_label + ",\n")
861+ master_prealloc_txt.append("\tPM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */\n")
862+ master_prealloc_txt.append("\tPM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */\n")
863+ master_prealloc_txt.append("\tPM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */\n")
864+ master_prealloc_txt.append("\n")
865+ node_count += 1
866+ master_prealloc_txt.insert(2, "\t" + str(node_count) + ",\n")
867+ master_prealloc_txt.append("\n")
868+ return master_prealloc_txt
869+
870+
871+def generate_master_section_data(sdtinfo_obj):
872+ out_lines = []
873+ out_lines.append("\tPM_CONFIG_MASTER_SECTION_ID, /* Master SectionID */" + "\n")
874+ master_count = len(sdtinfo_obj.masters.keys())
875+ out_lines.append("\t" + str(master_count) + "U, /* No. of Masters*/" + "\n")
876+ out_lines.append("\n")
877+ for master in sdtinfo_obj.masters.keys():
878+ if sdtinfo_obj.masters[master]["name"] == "RPU0":
879+ if is_rpu_lockstep(sdtinfo_obj) == True:
880+ master_node = "NODE_RPU"
881+ else:
882+ master_node = "NODE_RPU_0"
883+ elif sdtinfo_obj.masters[master]["name"] == "RPU1":
884+ master_node = "NODE_RPU_1"
885+ elif sdtinfo_obj.masters[master]["name"] == "APU":
886+ master_node = "NODE_APU"
887+ out_lines.append("\t" + master_node + ", /* Master Node ID */" + "\n")
888+ if is_ipi_present(master, sdtinfo_obj) == True:
889+ out_lines.append("\t" + get_ipi_mask_txt(master, sdtinfo_obj) + ", /* IPI Mask of this master */" + "\n")
890+ else:
891+ out_lines.append("\t0U, /* IPI Mask of this master */" + "\n")
892+ out_lines.append("\tSUSPEND_TIMEOUT, /* Suspend timeout */" + "\n")
893+ out_lines.append("\t" + get_all_other_masters_mask_txt(master, sdtinfo_obj) + ", /* Suspend permissions */" + "\n")
894+ out_lines.append("\t" + get_all_other_masters_mask_txt(master, sdtinfo_obj) + ", /* Wake permissions */" + "\n")
895+ out_lines.append("\n")
896+ out_lines.append("\n")
897+ return out_lines
898+
899+def generate_slave_section_data(sdtinfo_obj):
900+ out_lines = ["\n\n\tPM_CONFIG_SLAVE_SECTION_ID,\t/* Section ID */\n"]
901+ slave_count = 0
902+ for key in chc.node_map:
903+ periph_name = chc.node_map[key]['periph']
904+ periph_type = chc.node_map[key]['type']
905+ periph_label = chc.node_map[key]['label']
906+ if periph_type == "slave":
907+ chc.node_map[key]['perms'] = get_slave_perm_mask_txt(periph_name, sdtinfo_obj)
908+ elif (periph_type == "memory") and (periph_type != "NA"):
909+ chc.node_map[key]['perms'] = convert_ipi_mask_to_txt(get_mem_perm_mask(periph_name, sdtinfo_obj), sdtinfo_obj)
910+ elif periph_type == "others":
911+ chc.node_map[key]['perms'] = get_all_masters_mask_txt(sdtinfo_obj)
912+
913+ if ("slave" == periph_type) or ("memory" == periph_type and "NA" != periph_type) or ("others" == periph_type):
914+ if chc.node_map[key]['perms'] == "0U":
915+ continue
916+ slave_count += 1
917+ out_lines.append("\t" + periph_label + ",\n")
918+ out_lines.append("\tPM_SLAVE_FLAG_IS_SHAREABLE,\n")
919+ out_lines.append("\t" + chc.node_map[key]['perms']+ ", /* IPI Mask */\n\n")
920+
921+ ipi_perm = ""
922+ if periph_type == "ipi":
923+ if periph_label == "NODE_IPI_APU":
924+ if "psu_cortexa53_0" in sdtinfo_obj.masters.keys() and is_ipi_present("psu_cortexa53_0", sdtinfo_obj) != "":
925+ ipi_perm = get_ipi_mask_txt("psu_cortexa53_0", sdtinfo_obj)
926+ else:
927+ ipi_perm = ""
928+ elif periph_label == "NODE_IPI_RPU_0":
929+ if "psu_cortexr5_0" in sdtinfo_obj.masters.keys() and is_ipi_present("psu_cortexr5_0", sdtinfo_obj) != "":
930+ ipi_perm = get_ipi_mask_txt("psu_cortexr5_0", sdtinfo_obj)
931+ else:
932+ ipi_perm = ""
933+ elif periph_label == "NODE_IPI_RPU_1":
934+ if "psu_cortexr5_1" in sdtinfo_obj.masters.keys() and is_ipi_present("psu_cortexr5_1", sdtinfo_obj) != "":
935+ ipi_perm = get_ipi_mask_txt("psu_cortexr5_1", sdtinfo_obj)
936+ else:
937+ ipi_perm = ""
938+ else:
939+ ipi_perm = ""
940+ if ipi_perm != "":
941+ slave_count += 1
942+ chc.node_map[key]['perms'] = ipi_perm
943+ out_lines.append("\t" + periph_label + ",\n")
944+ out_lines.append("\t0U,\n")
945+ out_lines.append("\t" + chc.node_map[key]['perms']+ ", /* IPI Mask */\n\n")
946+
947+ out_lines.insert(1, "\t" + str(slave_count) + ",\t\t\t\t/* Number of slaves */\n\n")
948+ out_lines.append("\n")
949+ return out_lines
950+
951+def generate_prealloc_section_data(sdtinfo_obj):
952+ out_lines = ["\n"]
953+ master_count = 0
954+ proc_type = sdtinfo_obj.proc_type
955+ if is_ipi_present("psu_cortexa53_0", sdtinfo_obj) != "":
956+ chc.apu_prealloc_list.append("NODE_IPI_APU")
957+ if proc_type == "psu_cortexr5_0":
958+ chc.rpu_0_prealloc_list.extend(chc.rpu_0_prealloc_conditional_list)
959+ if is_ipi_present("psu_cortexr5_0", sdtinfo_obj) != "":
960+ chc.rpu_0_prealloc_list.append("NODE_IPI_RPU_0")
961+ if is_ipi_present("psu_cortexr5_1", sdtinfo_obj) != "":
962+ chc.rpu_1_prealloc_list.append("NODE_IPI_RPU_1")
963+ out_lines.append("\tPM_CONFIG_PREALLOC_SECTION_ID, /* Preallaoc SectionID */\n")
964+ for master in sdtinfo_obj.masters.keys():
965+ if is_ipi_present(master, sdtinfo_obj) == True:
966+ master_count += 1
967+ out_lines.append("\t" + str(master_count) + "U, /* No. of Masters*/\n")
968+ out_lines.append("\n")
969+ if "psu_cortexa53_0" in sdtinfo_obj.masters.keys() and is_ipi_present("psu_cortexa53_0", sdtinfo_obj):
970+ out_lines.extend(get_prealloc_for_master_txt("psu_cortexa53_0", chc.apu_prealloc_list, sdtinfo_obj))
971+ if "psu_cortexr5_0" in sdtinfo_obj.masters.keys() and is_ipi_present("psu_cortexr5_0", sdtinfo_obj):
972+ out_lines.extend(get_prealloc_for_master_txt("psu_cortexr5_0", chc.rpu_0_prealloc_list, sdtinfo_obj))
973+ if "psu_cortexr5_1" in sdtinfo_obj.masters.keys() and is_ipi_present("psu_cortexr5_1", sdtinfo_obj):
974+ out_lines.extend(get_prealloc_for_master_txt("psu_cortexr5_1", chc.rpu_1_prealloc_list, sdtinfo_obj))
975+ out_lines.append("\t\n")
976+ return out_lines
977+
978+def generate_power_section_data(sdtinfo_obj):
979+ out_lines = ["\n"]
980+ out_lines.append("\tPM_CONFIG_POWER_SECTION_ID, /* Power Section ID */\n")
981+ out_lines.append("\t" + str(len(chc.power_node_list)) + "U, /* Number of power nodes */\n")
982+ out_lines.append("\n")
983+ for node in chc.power_node_list:
984+ out_lines.append("\t" + node + ", /* Power node ID */\n")
985+ out_lines.append("\t" + get_power_domain_perm_mask_txt(node, sdtinfo_obj) + ", /* Force power down permissions */\n")
986+ out_lines.append("\n")
987+ out_lines.append("\n")
988+ return out_lines
989+
990+def generate_reset_section_data(sdtinfo_obj):
991+ out_lines = ["\n"]
992+ reset_management_master_list = get_list_of_management_master("reset", sdtinfo_obj)
993+ out_lines.append("\tPM_CONFIG_RESET_SECTION_ID, /* Reset Section ID */\n")
994+ out_lines.append("\t" + str(len(chc.reset_line_map)) + "U, /* Number of resets */\n")
995+ out_lines.append("\n")
996+ for reset_line in chc.reset_line_map:
997+ line_name = chc.reset_line_map[reset_line]["label"]
998+ line_type = chc.reset_line_map[reset_line]["type"]
999+ if line_type == "normal":
1000+ out_lines.append("\t" + line_name + ", " + get_all_masters_mask_txt(sdtinfo_obj) + ",\n")
1001+ elif line_type == "rpu_only":
1002+ if ("psu_cortexr5_0" in sdtinfo_obj.masters.keys()) and (is_ipi_present("psu_cortexr5_0", sdtinfo_obj) != ""):
1003+ out_lines.append("\t" + line_name + ", " + get_ipi_mask_txt("psu_cortexr5_0", sdtinfo_obj) + ",\n")
1004+ else:
1005+ out_lines.append("\t" + line_name + ", 0,\n")
1006+ elif (1 == is_all_master_enabled("reset", sdtinfo_obj)) and ((line_type == "rst_periph") or (line_type == "rst_shared" ) or (line_type == "rst_proc")) :
1007+ out_lines.append("\t" + line_name + ", " + get_all_masters_mask_txt(sdtinfo_obj) + ",\n")
1008+ elif (0 == is_all_master_enabled("reset", sdtinfo_obj)) and ((line_type == "rst_periph") or (line_type == "rst_shared" ) or (line_type == "rst_proc")) :
1009+ if line_type == "rst_periph":
1010+ perms = get_periph_perm_mask_txt_for_rst_line(reset_line)
1011+ out_lines.append("\t" + line_name + ", " + perms + ",\n")
1012+ elif line_type == "rst_shared":
1013+ out_lines.append("\t" + line_name + ", " + reset_management_master_list + ",\n")
1014+ elif line_type == "rst_proc":
1015+ line_proc = chc.reset_line_map[reset_line]["proc"]
1016+ macro_list = []
1017+ master_txt = []
1018+ if line_proc == "APU":
1019+ master_txt.append(get_ipi_mask_txt("psu_cortexa53_0", sdtinfo_obj))
1020+ elif (line_proc == "RPU_1") or (line_proc == "RPU" and is_rpu_lockstep(sdtinfo_obj)) or line_proc == "RPU_0" :
1021+ master_txt.append(get_ipi_mask_txt("psu_cortexr5_0", sdtinfo_obj))
1022+ elif line_proc == "RPU_1":
1023+ master_txt.append(get_ipi_mask_txt("psu_cortexr5_1", sdtinfo_obj))
1024+ elif line_proc == "RPU":
1025+ master_rpu_0 = get_ipi_mask_txt("psu_cortexr5_0", sdtinfo_obj)
1026+ master_rpu_1 = get_ipi_mask_txt("psu_cortexr5_1", sdtinfo_obj)
1027+ if ((master_rpu_0 in reset_management_master_list) and len(master_rpu_0) > 0) and \
1028+ ((master_rpu_1 in reset_management_master_list) and len(master_rpu_1) > 0):
1029+ master_txt.append(master_rpu_0 + " | " + master_rpu_1)
1030+ if (master_txt in reset_management_master_list) and len(master_txt) > 0:
1031+ macro_list.append(master_txt)
1032+ if "0U" == reset_management_master_list:
1033+ if len(macro_list) > 0:
1034+ macro_list.append(" | ")
1035+ macro_list.append(reset_management_master_list)
1036+ if len(macro_list) == 0:
1037+ out_lines.append("\t" + line_name + ", " + macro_list + ",\n")
1038+ else:
1039+ out_lines.append("\t" + line_name + ", 0,\n")
1040+ out_lines.append("\n")
1041+ return out_lines
1042+
1043+def generate_set_config_section_data(sdtinfo_obj):
1044+ out_lines = []
1045+ overlay_config_master_list = get_list_of_management_master("overlay_config", sdtinfo_obj)
1046+ out_lines.append("\tPM_CONFIG_SET_CONFIG_SECTION_ID,\t\t/* Set Config Section ID */\n")
1047+ out_lines.append("\t0U, /* Permissions to load base config object */\n")
1048+ out_lines.append("\t" + overlay_config_master_list + ", /* Permissions to load overlay config object */\n")
1049+ out_lines.append("\n")
1050+
1051+ return out_lines
1052+
1053+def generate_shutdown_section_data(sdtinfo_obj):
1054+ out_lines = ["\n"]
1055+ power_management_master_list = get_list_of_management_master("power", sdtinfo_obj)
1056+ out_lines.append("\tPM_CONFIG_SHUTDOWN_SECTION_ID, /* Shutdown Section ID */\n")
1057+ out_lines.append("\t" + power_management_master_list + ", /* System Shutdown/Restart Permission */\n")
1058+ out_lines.append("\n")
1059+ return out_lines
1060+
1061+def generate_gpo_section_data(sdtinfo_obj):
1062+ out_lines = []
1063+ out_lines.append("\tPM_CONFIG_GPO_SECTION_ID,\t\t/* GPO Section ID */\n")
1064+ for num in chc.gpo_nums:
1065+ if 1 == sdtinfo_obj.gpos["gpo" + str(num)]["polarity"]:
1066+ out_lines.append("\tPM_CONFIG_GPO1_BIT_" + str(num) + "_MASK |\n")
1067+ if 1 == sdtinfo_obj.gpos["gpo" + str(num)]["enable"]:
1068+ out_lines.append("\tPM_CONFIG_GPO1_MIO_PIN_"+ str(32+num) +"_MAP |\n")
1069+ out_lines.append("\t0,\t\t\t\t\t/* State of GPO pins */")
1070+ out_lines.append("\n")
1071+ return out_lines
1072+
1073+def generate_tpl_lines():
1074+ final_lines = cfg_data_tpl.config_object_template.split('\n')
1075+ for line_num in range(len(final_lines)):
1076+ final_lines[line_num] += '\n'
1077+ return final_lines
1078+
1079+def cfg_obj_write(root_node, sdt, options):
1080+ sdtinfo_obj = SdtInfo(sdt, options)
1081+
1082+ final_lines = generate_tpl_lines()
1083+
1084+ sections = [
1085+ {"identifier" : "<<MASTER_IPI_MASK_DEF>>", "handler" : generate_master_ipi_mask_def},
1086+ {"identifier" : "<<MASTER_SECTION_DATA>>", "handler" : generate_master_section_data},
1087+ {"identifier" : "<<SLAVE_SECTION_DATA>>", "handler" : generate_slave_section_data},
1088+ {"identifier" : "<<PREALLOC_SECTION_DATA>>", "handler" : generate_prealloc_section_data},
1089+ {"identifier" : "<<POWER_SECTION_DATA>>", "handler" : generate_power_section_data},
1090+ {"identifier" : "<<RESET_SECTION_DATA>>", "handler" : generate_reset_section_data},
1091+ {"identifier" : "<<SET_CONFIG_SECTION_DATA>>", "handler" : generate_set_config_section_data},
1092+ {"identifier" : "<<SHUTDOWN_SECTION_DATA>>", "handler" : generate_shutdown_section_data},
1093+ {"identifier" : "<<GPO_SECTION_DATA>>", "handler" : generate_gpo_section_data},
1094+ ]
1095+
1096+ for section in sections:
1097+ section_obj = Section(section["identifier"], section["handler"], sdtinfo_obj)
1098+ final_lines = section_obj.replace_section(final_lines)
1099+
1100+ outfile_name = options["args"][0]
1101+ outfile = open(outfile_name, 'w')
1102+ outfile.writelines(final_lines)
1103+ return True
1104--
11052.37.1 (Apple Git-137.1)
1106
diff --git a/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper_git.bbappend b/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper_git.bbappend
index 438d5498..ea4cbda9 100644
--- a/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper_git.bbappend
+++ b/meta-xilinx-core/dynamic-layers/virtualization-layer/recipes-kernel/lopper/lopper_git.bbappend
@@ -1,8 +1,7 @@
1SRC_URI = "git://github.com/devicetree-org/lopper.git;branch=master;protocol=https" 1SRC_URI = "git://github.com/devicetree-org/lopper.git;branch=master;protocol=https"
2SRCREV = "aa96fcc23ae332a826fa17eb9cf4986f44688f9b" 2SRCREV = "46a9d819b3b09e886076897879bf8dee4b1a70ca"
3 3
4FILESEXTRAPATHS:prepend := "${THISDIR}/lopper:" 4FILESEXTRAPATHS:prepend := "${THISDIR}/lopper:"
5SRC_URI += "file://0001-lopper-Implementation-of-lopper-plugin-for-generatin.patch"
6 5
7BASEVERSION = "1.1.0" 6BASEVERSION = "1.1.0"
8 7
generated by cgit v1.2.3-54-g00ecf (git 2.39.0) at 2026-07-22 02:38:43 +0000