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| author | Varalaxmi Bingi <varalaxmi.bingi@amd.com> | 2023-05-02 16:29:00 +0530 |
|---|---|---|
| committer | Mark Hatle <mark.hatle@amd.com> | 2023-05-02 14:35:18 -0500 |
| commit | b71c7a173b9500bb54f784b8a95f0dd646acc871 (patch) | |
| tree | 0ff3544ed6625f286b9530121ee3ab5d19d7d410 | |
| parent | ec9d3f44e72503edc7cdf104739c38d399ee598d (diff) | |
| download | meta-xilinx-b71c7a173b9500bb54f784b8a95f0dd646acc871.tar.gz | |
u-boot-xlnx-2023.2.inc:update branch and SRCREV for 2023.2
Changes from 2023.1 branch:
arm64: dts: versal-net: Fix msi controller node name
arm64: zynqmp: remove snps,enable_guctl1_resume_quirk quirk for usb
arm64: xilinx: Fix indentation and trailing spaces in dts
arm64: zynqmp: Assign TSU clock frequency for KV and KD boards
arm64: zynqmp: Assign TSU clock frequency for KR260
arm64: zynqmp: Remove interrupt/reg-names for AMS
arm64: zynqmp: Rename ams_ps/pl node names
arm64: zynqmp: Remove ltc2954 node from DT
arm64: zynqmp: Fix gpio comment about No of gpios
Revert "spi: zynqmp_qspi: Remove enabling interrupts code"
arm64: zynqmp: Update the i2c0 node for zcu1285
arm64: versal_net: Update RMII property
arm64: versal-net: Update spi-tx-bus-width to 4
arm64: versal-net: Update spi-max-freq to 150Mhz
arm64: versal-net: Add new parallel DT binding for tenzing se9 board
arm64: zynqmp: Add new parallel DT binding for ZC1751+DC1 board
arm64: versal: Enable ADIN ethernet phy
arm64: zynqmp: Enable ADIN ethernet phy
arm64: versal-net: dts: add cpuidle node
cmd: sf/nand: Print and return failure when 0 length is passed
arm64: zynqmp: Fix User MTD partition size
xilinx: dts: Fix open drain warning on Zynq, ZynqMP and Versal
arm: xilinx: Setting default i2c clock frequency to 400kHz
arm: dts: versal-net: add usb-wakeup interrupt in dwc-xilinx core
arm: dts: versal-net: add ref_clk property for REFCLKPER calculation
test: py: tests: Add test case for USB device
test: py: tests: Add dhcp abort test
test: py: tests: Add pxe command test
Signed-off-by: Varalaxmi Bingi <varalaxmi.bingi@amd.com>
Added changelog above.
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
| -rw-r--r-- | meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx-2023.2.inc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx-2023.2.inc b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx-2023.2.inc index 01082966..49959d28 100644 --- a/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx-2023.2.inc +++ b/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx-2023.2.inc | |||
| @@ -1,8 +1,8 @@ | |||
| 1 | UBOOT_VERSION = "v2023.01" | 1 | UBOOT_VERSION = "v2023.01" |
| 2 | 2 | ||
| 3 | UBRANCH = "xlnx_rebase_v2023.01" | 3 | UBRANCH = "xlnx_rel_2023.2-next" |
| 4 | 4 | ||
| 5 | SRCREV = "40a08d69e749c0472103551c85c02c41f979453d" | 5 | SRCREV = "9afbec02663ee0ddac4d7377cf36993adee2cb8a" |
| 6 | 6 | ||
| 7 | LICENSE = "GPL-2.0-or-later" | 7 | LICENSE = "GPL-2.0-or-later" |
| 8 | LIC_FILES_CHKSUM = "file://README;beginline=1;endline=4;md5=744e7e3bb0c94b4b9f6b3db3bf893897" | 8 | LIC_FILES_CHKSUM = "file://README;beginline=1;endline=4;md5=744e7e3bb0c94b4b9f6b3db3bf893897" |