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authorSivaprasad Addepalli <sivaprasad.addepalli@xilinx.com>2024-02-29 17:51:18 +0530
committerSiva Addepalli <sivaprasad.addepalli@xilinx.com>2024-02-29 19:17:09 +0530
commit9ce335dfe0ab6648f8346986856952e6991722a0 (patch)
treeb9dcf767f31a625e96e54e1a4bf44918f0cb088e
parentccca4a693e1236e1c15c80498a0912d5a400eab5 (diff)
downloadmeta-xilinx-9ce335dfe0ab6648f8346986856952e6991722a0.tar.gz
embeddedsw : Updated SRCREV for 2024.1_8135
Revert "sw_services: xilloader: Enhance Extract Metaheader command to get optional data" plm: versal_net: Ack In-Place PLM Update request only after Done sw_services:xilloader:Added Support for Infineon flash part v_sdirxss: SDT flow kcu116/vck190 apps restructure v_sditxss: Fix SDT flow pixco app name elaborate scugic: Fix compilation errors reported by C++ compiler i3c: Add Read/write FIFO depth config parameter i3c: Remove repeated start check and update XI3c_MasterRecvPolled i3c: Remove XI3c_ResetFifos from XI3C_BusInit and examples sw_services:xilsecure:Added enable configuration for ECC curve. qspips: src: Add missing parenthesis for macro expansions xilpm: versal_common: server: Remove XPm_IdleRestartHandler Warp Example App: Fix for interrupt callbacks sw_apps: imgsel: Fix zynqmp image selector app hang in usleep sw_services:xilocp:Add support for DME extension sw_services:xilcert:Add support for DME extension bsp:standalone: Add Xil_SChangeEndiannessAndCpy API lib: xlnx: Avoid mapping in MPU for region mapped by bsp sw_apps:versal_plm: Enabled PDI load status prints in debug level-0 sw_services: xilsecure: Update XPlmi_DmaXfr passing argument to word level scripts: pyesw: utils: Add support for read-only embeddedsw usecase sw_services: xilloader: Enhance Extract Metaheader command to get optional data xpsmfw:versal_net: fix assertion on event
-rw-r--r--meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass2
1 files changed, 1 insertions, 1 deletions
diff --git a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass
index fd253cc0..cb8fd5e5 100644
--- a/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass
+++ b/meta-xilinx-standalone/classes/xlnx-embeddedsw.bbclass
@@ -12,7 +12,7 @@ BRANCH ??= "${@d.getVarFlag('ESW_BRANCH', d.getVar('ESW_VER')) or '${ESW_VER}'}"
12ESW_REV[git] = "${AUTOREV}" 12ESW_REV[git] = "${AUTOREV}"
13ESW_REV[2023.1] = "af784f742dad0ca6e69e05baf8de51152c396b9a" 13ESW_REV[2023.1] = "af784f742dad0ca6e69e05baf8de51152c396b9a"
14ESW_REV[2023.2] = "73f0904e41cc109f18bb19a5329d0e5a66af2434" 14ESW_REV[2023.2] = "73f0904e41cc109f18bb19a5329d0e5a66af2434"
15ESW_REV[2024.1] = "26f1beadc7f3222b69f08683a1c410391352b255" 15ESW_REV[2024.1] = "688e76e473a8936170b1a453f52a751ab64fefda"
16SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}" 16SRCREV ??= "${@d.getVarFlag('ESW_REV', d.getVar('ESW_VER')) or '${AUTOREV}'}"
17 17
18EMBEDDEDSW_BRANCHARG ?= "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH') != '']}" 18EMBEDDEDSW_BRANCHARG ?= "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH') != '']}"