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authorAppana Durga Kedareswara rao <appana.durga.rao@xilinx.com>2020-01-20 21:50:03 +0530
committerMark Hatle <mark.hatle@xilinx.com>2020-02-27 08:33:25 -0800
commit5add1de35e0cca572f746a3222d156932f0abf9b (patch)
treee4525e598c5de353a26267bd11dd34634b6be97c
parent54c9bc703ac1ea3b63d2ca473df9e50bece4bf2f (diff)
downloadmeta-xilinx-5add1de35e0cca572f746a3222d156932f0abf9b.tar.gz
meta-xilinx-standalone: Add support for cortexa72 processor
This patch updates the COMPATIBLE_HOST and COMPATIBLE_MACHINE and DTBFILE variables to compile esw use cases for cortexa72 processor. Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
-rw-r--r--meta-xilinx-bsp/conf/machine/cortexa72-versal.conf2
-rw-r--r--meta-xilinx-standalone/classes/esw.bbclass6
-rw-r--r--meta-xilinx-standalone/recipes-bsp/device-tree/device-tree.bbappend2
3 files changed, 9 insertions, 1 deletions
diff --git a/meta-xilinx-bsp/conf/machine/cortexa72-versal.conf b/meta-xilinx-bsp/conf/machine/cortexa72-versal.conf
index ed93f0cc..7191ac64 100644
--- a/meta-xilinx-bsp/conf/machine/cortexa72-versal.conf
+++ b/meta-xilinx-bsp/conf/machine/cortexa72-versal.conf
@@ -12,6 +12,6 @@ ARMPKGARCH_tune-cortexa72 = "cortexa72"
12TUNE_FEATURES_tune-cortexa72 = "${TUNE_FEATURES_tune-aarch64} cortexa72" 12TUNE_FEATURES_tune-cortexa72 = "${TUNE_FEATURES_tune-aarch64} cortexa72"
13PACKAGE_EXTRA_ARCHS_tune-cortexa72 = "${PACKAGE_EXTRA_ARCHS_tune-aarch64}" 13PACKAGE_EXTRA_ARCHS_tune-cortexa72 = "${PACKAGE_EXTRA_ARCHS_tune-aarch64}"
14 14
15 15SOC_FAMILY = "versal"
16#LANGUAGES_append = ",lto" 16#LANGUAGES_append = ",lto"
17 17
diff --git a/meta-xilinx-standalone/classes/esw.bbclass b/meta-xilinx-standalone/classes/esw.bbclass
index f668a11b..03694d42 100644
--- a/meta-xilinx-standalone/classes/esw.bbclass
+++ b/meta-xilinx-standalone/classes/esw.bbclass
@@ -32,9 +32,13 @@ COMPATIBLE_MACHINE_microblaze-plm = "microblaze-plm"
32COMPATIBLE_HOST_cortexa53-zynqmp = "aarch64.*-elf" 32COMPATIBLE_HOST_cortexa53-zynqmp = "aarch64.*-elf"
33COMPATIBLE_MACHINE_cortexa53-zynqmp = "cortexa53-zynqmp" 33COMPATIBLE_MACHINE_cortexa53-zynqmp = "cortexa53-zynqmp"
34 34
35COMPATIBLE_HOST_cortexa72 = "aarch64.*-elf"
36COMPATIBLE_MACHINE_cortexa72 = "cortexa72"
37
35DTBFILE_microblaze-pmu ?= "${RECIPE_SYSROOT}/boot/devicetree/system-top.dtb" 38DTBFILE_microblaze-pmu ?= "${RECIPE_SYSROOT}/boot/devicetree/system-top.dtb"
36DTBFILE_microblaze-plm ?= "${RECIPE_SYSROOT}/boot/devicetree/system-top.dtb" 39DTBFILE_microblaze-plm ?= "${RECIPE_SYSROOT}/boot/devicetree/system-top.dtb"
37DTBFILE_cortexa53-zynqmp ?= "${RECIPE_SYSROOT}/boot/devicetree/system-top.dtb" 40DTBFILE_cortexa53-zynqmp ?= "${RECIPE_SYSROOT}/boot/devicetree/system-top.dtb"
41DTBFILE_cortexa72 ?= "${RECIPE_SYSROOT}/boot/devicetree/system-top.dtb"
38 42
39def get_xlnx_cmake_machine(fam, d): 43def get_xlnx_cmake_machine(fam, d):
40 if (fam == 'zynqmp'): 44 if (fam == 'zynqmp'):
@@ -50,6 +54,8 @@ def get_xlnx_cmake_processor(machine, d):
50 cmake_processor = 'cortexa53' 54 cmake_processor = 'cortexa53'
51 elif (machine == 'cortexr5'): 55 elif (machine == 'cortexr5'):
52 cmake_processor = 'cortexar5' 56 cmake_processor = 'cortexar5'
57 elif (machine == 'cortexa72'):
58 cmake_processor = 'cortexa72'
53 elif (machine == 'microblaze-pmu'): 59 elif (machine == 'microblaze-pmu'):
54 cmake_processor = 'pmu_microblaze' 60 cmake_processor = 'pmu_microblaze'
55 elif (machine == 'microblaze-plm'): 61 elif (machine == 'microblaze-plm'):
diff --git a/meta-xilinx-standalone/recipes-bsp/device-tree/device-tree.bbappend b/meta-xilinx-standalone/recipes-bsp/device-tree/device-tree.bbappend
index fc98d033..88f89dce 100644
--- a/meta-xilinx-standalone/recipes-bsp/device-tree/device-tree.bbappend
+++ b/meta-xilinx-standalone/recipes-bsp/device-tree/device-tree.bbappend
@@ -1,6 +1,7 @@
1COMPATIBLE_MACHINE_cortexa53-zynqmp = ".*" 1COMPATIBLE_MACHINE_cortexa53-zynqmp = ".*"
2COMPATIBLE_MACHINE_microblaze-pmu = ".*" 2COMPATIBLE_MACHINE_microblaze-pmu = ".*"
3COMPATIBLE_MACHINE_microblaze-plm = ".*" 3COMPATIBLE_MACHINE_microblaze-plm = ".*"
4COMPATIBLE_MACHINE_cortexa72 = ".*"
4 5
5 6
6REPO = "git://gitenterprise.xilinx.com/decoupling/device-tree-xlnx;protocol=https" 7REPO = "git://gitenterprise.xilinx.com/decoupling/device-tree-xlnx;protocol=https"
@@ -12,6 +13,7 @@ SRCREV = "${AUTOREV}"
12 13
13XSCTH_PROC_cortexa53-zynqmp ??= "psu_cortexa53_0" 14XSCTH_PROC_cortexa53-zynqmp ??= "psu_cortexa53_0"
14XSCTH_PROC_microblaze-pmu ??= "psu_pmu_0" 15XSCTH_PROC_microblaze-pmu ??= "psu_pmu_0"
16XSCTH_PROC_cortexa72 ??= "psv_cortexa72_0"
15XSCTH_PROC_microblaze-plm ??= "psv_pmc_0" 17XSCTH_PROC_microblaze-plm ??= "psv_pmc_0"
16 18
17# Enable @ flag on dtc which is required by libxil 19# Enable @ flag on dtc which is required by libxil