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| author | Siva Addepalli <sivaprasad.addepalli@xilinx.com> | 2023-11-16 12:30:11 +0530 |
|---|---|---|
| committer | Siva Addepalli <sivaprasad.addepalli@xilinx.com> | 2023-11-16 12:30:11 +0530 |
| commit | 160623c7afeba04e32bb920374033342b268a529 (patch) | |
| tree | 2d4eab4a59edc6a6c03fbd3ce439ebb97db756a3 | |
| parent | faf21e40ac972e4b9ee3eddb79c5140f03b9364e (diff) | |
| download | meta-xilinx-160623c7afeba04e32bb920374033342b268a529.tar.gz | |
Updated Commit ID
ipinfo.yaml: Add available memory banks for versal-net
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
| m--------- | meta-xilinx-core/gen-machine-conf | 0 |
1 files changed, 0 insertions, 0 deletions
diff --git a/meta-xilinx-core/gen-machine-conf b/meta-xilinx-core/gen-machine-conf | |||
| Subproject 02b9a969a367abb8cfadcf904db612a6eb3fc70 | Subproject f989df5aba4c7215f1e15940c1257a4c5699994 | ||