diff options
| author | rbramand <rahul.bramandlapalli@xilinx.com> | 2023-04-17 22:06:11 +0530 |
|---|---|---|
| committer | Mark Hatle <mark.hatle@amd.com> | 2023-04-20 17:21:19 -0500 |
| commit | 08a707e456c8bbf1f428a5607e673204cfbc7daa (patch) | |
| tree | 417e4e05f46732740a16e133547eb909284ff965 | |
| parent | 9f1a6d2a5d98b8b836c313aa1cde205a990db82a (diff) | |
| download | meta-xilinx-08a707e456c8bbf1f428a5607e673204cfbc7daa.tar.gz | |
Update xrt, zocl commit id
changelog :
CR-1150767 Fix for clock throttling documentation. (#7502) (#7505)
reporting 1 or 2 MEM tile channels (#7497)
Signed-off-by: rbramand <rbramand@xilinx.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
| -rw-r--r-- | meta-xilinx-core/recipes-xrt/xrt/xrt.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/meta-xilinx-core/recipes-xrt/xrt/xrt.inc b/meta-xilinx-core/recipes-xrt/xrt/xrt.inc index 62575ceb..3b150673 100644 --- a/meta-xilinx-core/recipes-xrt/xrt/xrt.inc +++ b/meta-xilinx-core/recipes-xrt/xrt/xrt.inc | |||
| @@ -3,6 +3,6 @@ BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != ' | |||
| 3 | SRC_URI = "${REPO};${BRANCHARG}" | 3 | SRC_URI = "${REPO};${BRANCHARG}" |
| 4 | 4 | ||
| 5 | BRANCH= "2023.1" | 5 | BRANCH= "2023.1" |
| 6 | SRCREV= "67a13ed5a477cfa24a9dd3d58ccb97a910f10dac" | 6 | SRCREV= "64c933573e7e50a8aba939a74209590c2b739e8b" |
| 7 | PV = "202310.2.15.0" | 7 | PV = "202310.2.15.0" |
| 8 | 8 | ||