xvisor: update to v0.3.2-tip

Bumping xvisor to version v0.3.2-57-g1de3ff44, which comprises the following commits:

    1de3ff44 [RISC-V] Fix RVV vlenb probe in cpu_vcpu_rvv_init
    8713a802 [RISC-V] Disable MMU before page table cleanup
    50facff9 [RISC-V] Fix RVV state and dynamically initialize vector registers
    5ec72e10 [RISC-V] Fix RVV context save/restore stride and RV32 compatibility
    0558c348 TESTS: compile with -fno-pic and -Wl,--no-pie
    acea4920 [RISC-V] Replace .word encodings with H-extension mnemonics
    b4f4753e RISC-V: delegate illegal instruction exception by default
    defbff33 RISC-V: introduce RVV_ENABLED macro
    fa393fe8 RISC-V: make dumpreg command sensitive to VLEN
    8a12f4dd RISC-V: add support for RVV
    f9035e95 Fix: Track vcpu after scheduler switch to process correct IRQs
    e6cf23ef CORE: vmm_main: Check aliases node if stdout-path value is not a path
    22a8fe9b TESTS: Use '-std=gnu11' to fix build with GCC 15
    9682e7b5 Makefile: Use '-std=gnu11' to fix build with GCC 15
    355c79a0 irq-riscv-aclint: fix overlapping irqdomains
    37ff69f4 irq-riscv-imsic: fix imsic without handlers
    10a76a80 virtio_host_blk: make device ready before using its virtqueues
    09328306 RISC-V: Pass -1 in hart_mask_base instead of hart_mask in rfence SBI.
    4ac97ff8 RISC-V: Configure Smstateen extension for Guest
    57abfd81 RISC-V: Add Smstateen related CSR defines
    ef0f5b31 RISC-V: Parse Smstateen extension from ISA string
    0d3c1047 CORE: vmm_platform: Fix platform_get_msi_domain() implementation
    2e0ed848 RISC-V: Implement SBI nested acceleration extension
    2f1d7696 RISC-V: Extend nested virtualization for shared memory based HFENCE
    ad0de2db RISC-V: Extend nested virtualization for shared memory based CSR access
    34059f13 RISC-V: Add defines for the SBI nested acceleration extension
    fb46e69f RISC-V: Remove redundant timer event from struct riscv_priv_nested
    a8c5e49d RISC-V: Increase the SWTLB size used for nested virtualization
    50e27aee RISC-V: Use bitfields in struct arch_pgflags
    37b51025 RISC-V: Count the guest page faults redirected to the Guest
    6777a28c x86: Fix linker warning seen with binutils 2.39
    a99eda34 [DRIVERS] virtio: fix virtio test bit
    9b5f55ed DRIVERS: xlnx-uartlite: Add support for Xilinx AXI UART Lite
    c21af932 fix: correct argument for opensbi dbcn console read ecall
    4b27a93d Makefile: Improve dependency files inclusion logic
    f9e95d05 RISC-V: Add sbss section in linker script
    abc9b330 COMMANDS: vserial: Yield the CPU time in cmd_vserial_bind()
    5403f96d RISC-V: Implement SBI debug console extension for Guest
    afd3ba37 RISC-V: Fix how guest vserial instance is located
    b8abc095 RISC-V: Use SBI debug console for defterm whenever available
    0dfef2af RISC-V: Add SBI_SPEC_MK_VERSION() helper macro
    fc818343 RISC-V: Add defines for SBI debug console extension
    9f685732 RISC-V: Change the SBI specification version to v2.0 for guest
    d16db436 RISC-V: Allow disabling SBI extensions based on Guest DT
    7ee4bfde RISC-V: Add option probe() callback for VCPU SBI extensions
    8763c9ed RISC-V: Rename cpu_vcpu_fp_init() to cpu_vcpu_fp_reset()
    08199bd5 RISC-V: Improve timer init and deinit function
    9cd344d0 DOCS: Update qemu-system-riscv[64|32] usage in README files
    abb381cb Makefile: fix grep warning
    0c8bbfe3 Makefile: fix grep warning
    a969f502 RISC-V: Force no-pie code generation and static link
    f5742761 X86: fix some basic error
    3f715f58 RISC-V: Align _start_hang symbol to 4 bytes
    a705b847 TOOLS: memimg.py: explicitly use the python3 interpreter
    888c94e7 TOOLS: d2c.py: explicitly use the python3 interpreter
    1329959e TESTS: common: Fix busybox rootfs configuration for virt32
    2968af2f DOCS: Update commit tag in v0.3.2 release notes

Signed-off-by: Bruce Ashfield <bruce.ashfield@gmail.com>

1 files changed, 1 insertions, 1 deletions

diff --git a/recipes-extended/xvisor/xvisor_git.bb b/recipes-extended/xvisor/xvisor_git.bb
index 097f1531..00141ae3 100644
--- a/recipes-extended/xvisor/xvisor_git.bb
+++ b/recipes-extended/xvisor/xvisor_git.bb
@@ -11,7 +11,7 @@ inherit autotools-brokensep
 PV = "0.3.2+git"
 
 # This version support the RISC-V v0.5.0 Hypervisor extensions
-SRCREV = "355c79a07d9c1b783962ebf47b9b18194b7d40bd"
+SRCREV = "1de3ff44606a663f983969f1a97c045f1baf0094"
 SRC_URI = "git://github.com/xvisor/xvisor.git;branch=master;protocol=https \
     file://0001-TESTS-Don-t-specify-mabi-or-march-for-RISC-V.patch \
 "