ti-sci-fw: now Cortex-R5 SPL can also be provided by u-boot-ti-mainline

Signed-off-by: Denys Dmytriyenko <denys@ti.com>
Signed-off-by: Dan Murphy <dmurphy@ti.com>

2 files changed, 2 insertions, 1 deletions

diff --git a/conf/machine/include/k3r5.inc b/conf/machine/include/k3r5.inc
index 52fcf38b..a32accae 100644
--- a/conf/machine/include/k3r5.inc
+++ b/conf/machine/include/k3r5.inc
@@ -21,3 +21,4 @@ UBOOT_IMAGE = "tiboot3-${MAINMACHINE}-${PV}-${PR}.${UBOOT_SUFFIX}"
 UBOOT_SYMLINK = "tiboot3-${MAINMACHINE}.${UBOOT_SUFFIX}"
 
 PACKAGECONFIG_pn-u-boot-ti-staging = ""
+PACKAGECONFIG_pn-u-boot-ti-mainline = ""
diff --git a/recipes-bsp/ti-sci-fw/ti-sci-fw_git.bb b/recipes-bsp/ti-sci-fw/ti-sci-fw_git.bb
index 458b8921..1239b278 100644
--- a/recipes-bsp/ti-sci-fw/ti-sci-fw_git.bb
+++ b/recipes-bsp/ti-sci-fw/ti-sci-fw_git.bb
@@ -1,7 +1,7 @@
 require recipes-bsp/ti-sci-fw/ti-sci-fw.inc
 
 DEPENDS = "openssl-native u-boot-mkimage-native dtc-native"
-DEPENDS_append_j7200-evm-k3r5 = " u-boot-ti-staging"
+DEPENDS_append_j7200-evm-k3r5 = " virtual/bootloader"
 
 CLEANBROKEN = "1"
 PR = "r1"