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-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106819.patch436
1 files changed, 436 insertions, 0 deletions
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106819.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106819.patch
new file mode 100644
index 0000000000..e097ec27fa
--- /dev/null
+++ b/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106819.patch
@@ -0,0 +1,436 @@
12011-10-03 Richard Sandiford <richard.sandiford@linaro.org>
2
3 gcc/
4 Backport from mainline:
5
6 2011-09-22 Richard Sandiford <richard.sandiford@linaro.org>
7
8 * config/arm/predicates.md (expandable_comparison_operator): New
9 predicate, extracted from...
10 (arm_comparison_operator): ...here.
11 * config/arm/arm.md (cbranchsi4, cbranchsf4, cbranchdf4, cbranchdi4)
12 (cstoresi4, cstoresf4, cstoredf4, cstoredi4, movsicc, movsfcc)
13 (movdfcc): Use expandable_comparison_operator.
14
15 gcc/testsuite/
16 Backport from mainline:
17
18 2011-09-22 Richard Sandiford <richard.sandiford@linaro.org>
19
20 * gcc.target/arm/cmp-1.c: New test.
21 * gcc.target/arm/cmp-2.c: Likewise.
22
232011-10-03 Richard Sandiford <richard.sandiford@linaro.org>
24
25 gcc/
26 Backport from mainline:
27
28 2011-09-07 Richard Sandiford <richard.sandiford@linaro.org>
29
30 PR target/49030
31 * config/arm/arm-protos.h (maybe_get_arm_condition_code): Declare.
32 * config/arm/arm.c (maybe_get_arm_condition_code): New function,
33 reusing the old code from get_arm_condition_code. Return ARM_NV
34 for invalid comparison codes.
35 (get_arm_condition_code): Redefine in terms of
36 maybe_get_arm_condition_code.
37 * config/arm/predicates.md (arm_comparison_operator): Use
38 maybe_get_arm_condition_code.
39
40 gcc/testsuite/
41 Backport from mainline:
42
43 2011-09-07 Richard Sandiford <richard.sandiford@linaro.org>
44
45 PR target/49030
46 * gcc.dg/torture/pr49030.c: New test.
47
48=== modified file 'gcc/config/arm/arm-protos.h'
49--- old/gcc/config/arm/arm-protos.h 2011-09-15 09:45:31 +0000
50+++ new/gcc/config/arm/arm-protos.h 2011-10-03 09:46:40 +0000
51@@ -180,6 +180,7 @@
52 #endif
53 extern int thumb_shiftable_const (unsigned HOST_WIDE_INT);
54 #ifdef RTX_CODE
55+extern enum arm_cond_code maybe_get_arm_condition_code (rtx);
56 extern void thumb1_final_prescan_insn (rtx);
57 extern void thumb2_final_prescan_insn (rtx);
58 extern const char *thumb_load_double_from_address (rtx *);
59
60=== modified file 'gcc/config/arm/arm.c'
61--- old/gcc/config/arm/arm.c 2011-09-19 07:44:24 +0000
62+++ new/gcc/config/arm/arm.c 2011-10-03 09:46:40 +0000
63@@ -17494,10 +17494,10 @@
64 decremented/zeroed by arm_asm_output_opcode as the insns are output. */
65
66 /* Returns the index of the ARM condition code string in
67- `arm_condition_codes'. COMPARISON should be an rtx like
68- `(eq (...) (...))'. */
69-static enum arm_cond_code
70-get_arm_condition_code (rtx comparison)
71+ `arm_condition_codes', or ARM_NV if the comparison is invalid.
72+ COMPARISON should be an rtx like `(eq (...) (...))'. */
73+enum arm_cond_code
74+maybe_get_arm_condition_code (rtx comparison)
75 {
76 enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
77 enum arm_cond_code code;
78@@ -17521,11 +17521,11 @@
79 case CC_DLTUmode: code = ARM_CC;
80
81 dominance:
82- gcc_assert (comp_code == EQ || comp_code == NE);
83-
84 if (comp_code == EQ)
85 return ARM_INVERSE_CONDITION_CODE (code);
86- return code;
87+ if (comp_code == NE)
88+ return code;
89+ return ARM_NV;
90
91 case CC_NOOVmode:
92 switch (comp_code)
93@@ -17534,7 +17534,7 @@
94 case EQ: return ARM_EQ;
95 case GE: return ARM_PL;
96 case LT: return ARM_MI;
97- default: gcc_unreachable ();
98+ default: return ARM_NV;
99 }
100
101 case CC_Zmode:
102@@ -17542,7 +17542,7 @@
103 {
104 case NE: return ARM_NE;
105 case EQ: return ARM_EQ;
106- default: gcc_unreachable ();
107+ default: return ARM_NV;
108 }
109
110 case CC_Nmode:
111@@ -17550,7 +17550,7 @@
112 {
113 case NE: return ARM_MI;
114 case EQ: return ARM_PL;
115- default: gcc_unreachable ();
116+ default: return ARM_NV;
117 }
118
119 case CCFPEmode:
120@@ -17575,7 +17575,7 @@
121 /* UNEQ and LTGT do not have a representation. */
122 case UNEQ: /* Fall through. */
123 case LTGT: /* Fall through. */
124- default: gcc_unreachable ();
125+ default: return ARM_NV;
126 }
127
128 case CC_SWPmode:
129@@ -17591,7 +17591,7 @@
130 case GTU: return ARM_CC;
131 case LEU: return ARM_CS;
132 case LTU: return ARM_HI;
133- default: gcc_unreachable ();
134+ default: return ARM_NV;
135 }
136
137 case CC_Cmode:
138@@ -17599,7 +17599,7 @@
139 {
140 case LTU: return ARM_CS;
141 case GEU: return ARM_CC;
142- default: gcc_unreachable ();
143+ default: return ARM_NV;
144 }
145
146 case CC_CZmode:
147@@ -17611,7 +17611,7 @@
148 case GTU: return ARM_HI;
149 case LEU: return ARM_LS;
150 case LTU: return ARM_CC;
151- default: gcc_unreachable ();
152+ default: return ARM_NV;
153 }
154
155 case CC_NCVmode:
156@@ -17621,7 +17621,7 @@
157 case LT: return ARM_LT;
158 case GEU: return ARM_CS;
159 case LTU: return ARM_CC;
160- default: gcc_unreachable ();
161+ default: return ARM_NV;
162 }
163
164 case CCmode:
165@@ -17637,13 +17637,22 @@
166 case GTU: return ARM_HI;
167 case LEU: return ARM_LS;
168 case LTU: return ARM_CC;
169- default: gcc_unreachable ();
170+ default: return ARM_NV;
171 }
172
173 default: gcc_unreachable ();
174 }
175 }
176
177+/* Like maybe_get_arm_condition_code, but never return ARM_NV. */
178+static enum arm_cond_code
179+get_arm_condition_code (rtx comparison)
180+{
181+ enum arm_cond_code code = maybe_get_arm_condition_code (comparison);
182+ gcc_assert (code != ARM_NV);
183+ return code;
184+}
185+
186 /* Tell arm_asm_output_opcode to output IT blocks for conditionally executed
187 instructions. */
188 void
189
190=== modified file 'gcc/config/arm/arm.md'
191--- old/gcc/config/arm/arm.md 2011-09-12 14:14:00 +0000
192+++ new/gcc/config/arm/arm.md 2011-10-03 09:47:33 +0000
193@@ -6543,7 +6543,7 @@
194
195 (define_expand "cbranchsi4"
196 [(set (pc) (if_then_else
197- (match_operator 0 "arm_comparison_operator"
198+ (match_operator 0 "expandable_comparison_operator"
199 [(match_operand:SI 1 "s_register_operand" "")
200 (match_operand:SI 2 "nonmemory_operand" "")])
201 (label_ref (match_operand 3 "" ""))
202@@ -6594,7 +6594,7 @@
203
204 (define_expand "cbranchsf4"
205 [(set (pc) (if_then_else
206- (match_operator 0 "arm_comparison_operator"
207+ (match_operator 0 "expandable_comparison_operator"
208 [(match_operand:SF 1 "s_register_operand" "")
209 (match_operand:SF 2 "arm_float_compare_operand" "")])
210 (label_ref (match_operand 3 "" ""))
211@@ -6606,7 +6606,7 @@
212
213 (define_expand "cbranchdf4"
214 [(set (pc) (if_then_else
215- (match_operator 0 "arm_comparison_operator"
216+ (match_operator 0 "expandable_comparison_operator"
217 [(match_operand:DF 1 "s_register_operand" "")
218 (match_operand:DF 2 "arm_float_compare_operand" "")])
219 (label_ref (match_operand 3 "" ""))
220@@ -6618,7 +6618,7 @@
221
222 (define_expand "cbranchdi4"
223 [(set (pc) (if_then_else
224- (match_operator 0 "arm_comparison_operator"
225+ (match_operator 0 "expandable_comparison_operator"
226 [(match_operand:DI 1 "cmpdi_operand" "")
227 (match_operand:DI 2 "cmpdi_operand" "")])
228 (label_ref (match_operand 3 "" ""))
229@@ -7473,7 +7473,7 @@
230
231 (define_expand "cstoresi4"
232 [(set (match_operand:SI 0 "s_register_operand" "")
233- (match_operator:SI 1 "arm_comparison_operator"
234+ (match_operator:SI 1 "expandable_comparison_operator"
235 [(match_operand:SI 2 "s_register_operand" "")
236 (match_operand:SI 3 "reg_or_int_operand" "")]))]
237 "TARGET_32BIT || TARGET_THUMB1"
238@@ -7609,7 +7609,7 @@
239
240 (define_expand "cstoresf4"
241 [(set (match_operand:SI 0 "s_register_operand" "")
242- (match_operator:SI 1 "arm_comparison_operator"
243+ (match_operator:SI 1 "expandable_comparison_operator"
244 [(match_operand:SF 2 "s_register_operand" "")
245 (match_operand:SF 3 "arm_float_compare_operand" "")]))]
246 "TARGET_32BIT && TARGET_HARD_FLOAT"
247@@ -7619,7 +7619,7 @@
248
249 (define_expand "cstoredf4"
250 [(set (match_operand:SI 0 "s_register_operand" "")
251- (match_operator:SI 1 "arm_comparison_operator"
252+ (match_operator:SI 1 "expandable_comparison_operator"
253 [(match_operand:DF 2 "s_register_operand" "")
254 (match_operand:DF 3 "arm_float_compare_operand" "")]))]
255 "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
256@@ -7629,7 +7629,7 @@
257
258 (define_expand "cstoredi4"
259 [(set (match_operand:SI 0 "s_register_operand" "")
260- (match_operator:SI 1 "arm_comparison_operator"
261+ (match_operator:SI 1 "expandable_comparison_operator"
262 [(match_operand:DI 2 "cmpdi_operand" "")
263 (match_operand:DI 3 "cmpdi_operand" "")]))]
264 "TARGET_32BIT"
265@@ -7749,7 +7749,7 @@
266
267 (define_expand "movsicc"
268 [(set (match_operand:SI 0 "s_register_operand" "")
269- (if_then_else:SI (match_operand 1 "arm_comparison_operator" "")
270+ (if_then_else:SI (match_operand 1 "expandable_comparison_operator" "")
271 (match_operand:SI 2 "arm_not_operand" "")
272 (match_operand:SI 3 "arm_not_operand" "")))]
273 "TARGET_32BIT"
274@@ -7769,7 +7769,7 @@
275
276 (define_expand "movsfcc"
277 [(set (match_operand:SF 0 "s_register_operand" "")
278- (if_then_else:SF (match_operand 1 "arm_comparison_operator" "")
279+ (if_then_else:SF (match_operand 1 "expandable_comparison_operator" "")
280 (match_operand:SF 2 "s_register_operand" "")
281 (match_operand:SF 3 "nonmemory_operand" "")))]
282 "TARGET_32BIT && TARGET_HARD_FLOAT"
283@@ -7795,7 +7795,7 @@
284
285 (define_expand "movdfcc"
286 [(set (match_operand:DF 0 "s_register_operand" "")
287- (if_then_else:DF (match_operand 1 "arm_comparison_operator" "")
288+ (if_then_else:DF (match_operand 1 "expandable_comparison_operator" "")
289 (match_operand:DF 2 "s_register_operand" "")
290 (match_operand:DF 3 "arm_float_add_operand" "")))]
291 "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP_DOUBLE)"
292
293=== modified file 'gcc/config/arm/predicates.md'
294--- old/gcc/config/arm/predicates.md 2011-09-15 09:45:31 +0000
295+++ new/gcc/config/arm/predicates.md 2011-10-03 09:47:33 +0000
296@@ -242,11 +242,15 @@
297
298 ;; True for integer comparisons and, if FP is active, for comparisons
299 ;; other than LTGT or UNEQ.
300+(define_special_predicate "expandable_comparison_operator"
301+ (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,
302+ unordered,ordered,unlt,unle,unge,ungt"))
303+
304+;; Likewise, but only accept comparisons that are directly supported
305+;; by ARM condition codes.
306 (define_special_predicate "arm_comparison_operator"
307- (ior (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu")
308- (and (match_test "TARGET_32BIT && TARGET_HARD_FLOAT
309- && (TARGET_FPA || TARGET_VFP)")
310- (match_code "unordered,ordered,unlt,unle,unge,ungt"))))
311+ (and (match_operand 0 "expandable_comparison_operator")
312+ (match_test "maybe_get_arm_condition_code (op) != ARM_NV")))
313
314 (define_special_predicate "lt_ge_comparison_operator"
315 (match_code "lt,ge"))
316
317=== added file 'gcc/testsuite/gcc.dg/torture/pr49030.c'
318--- old/gcc/testsuite/gcc.dg/torture/pr49030.c 1970-01-01 00:00:00 +0000
319+++ new/gcc/testsuite/gcc.dg/torture/pr49030.c 2011-10-03 09:46:40 +0000
320@@ -0,0 +1,19 @@
321+void
322+sample_move_d32u24_sS (char *dst, float *src, unsigned long nsamples,
323+ unsigned long dst_skip)
324+{
325+ long long y;
326+ while (nsamples--)
327+ {
328+ y = (long long) (*src * 8388608.0f) << 8;
329+ if (y > 2147483647) {
330+ *(int *) dst = 2147483647;
331+ } else if (y < -2147483647 - 1) {
332+ *(int *) dst = -2147483647 - 1;
333+ } else {
334+ *(int *) dst = (int) y;
335+ }
336+ dst += dst_skip;
337+ src++;
338+ }
339+}
340
341=== added file 'gcc/testsuite/gcc.target/arm/cmp-1.c'
342--- old/gcc/testsuite/gcc.target/arm/cmp-1.c 1970-01-01 00:00:00 +0000
343+++ new/gcc/testsuite/gcc.target/arm/cmp-1.c 2011-10-03 09:47:33 +0000
344@@ -0,0 +1,37 @@
345+/* { dg-do compile } */
346+/* { dg-options "-O" } */
347+/* { dg-final { scan-assembler-not "\tbl\t" } } */
348+/* { dg-final { scan-assembler-not "__aeabi" } } */
349+int x, y;
350+
351+#define TEST_EXPR(NAME, ARGS, EXPR) \
352+ int NAME##1 ARGS { return (EXPR); } \
353+ int NAME##2 ARGS { return !(EXPR); } \
354+ int NAME##3 ARGS { return (EXPR) ? x : y; } \
355+ void NAME##4 ARGS { if (EXPR) x++; } \
356+ void NAME##5 ARGS { if (!(EXPR)) x++; }
357+
358+#define TEST(NAME, TYPE, OPERATOR) \
359+ TEST_EXPR (NAME##_rr, (TYPE a1, TYPE a2), a1 OPERATOR a2) \
360+ TEST_EXPR (NAME##_rm, (TYPE a1, TYPE *a2), a1 OPERATOR *a2) \
361+ TEST_EXPR (NAME##_mr, (TYPE *a1, TYPE a2), *a1 OPERATOR a2) \
362+ TEST_EXPR (NAME##_mm, (TYPE *a1, TYPE *a2), *a1 OPERATOR *a2) \
363+ TEST_EXPR (NAME##_rc, (TYPE a1), a1 OPERATOR 100) \
364+ TEST_EXPR (NAME##_cr, (TYPE a1), 100 OPERATOR a1)
365+
366+#define TEST_OP(NAME, OPERATOR) \
367+ TEST (sc_##NAME, signed char, OPERATOR) \
368+ TEST (uc_##NAME, unsigned char, OPERATOR) \
369+ TEST (ss_##NAME, short, OPERATOR) \
370+ TEST (us_##NAME, unsigned short, OPERATOR) \
371+ TEST (si_##NAME, int, OPERATOR) \
372+ TEST (ui_##NAME, unsigned int, OPERATOR) \
373+ TEST (sll_##NAME, long long, OPERATOR) \
374+ TEST (ull_##NAME, unsigned long long, OPERATOR)
375+
376+TEST_OP (eq, ==)
377+TEST_OP (ne, !=)
378+TEST_OP (lt, <)
379+TEST_OP (gt, >)
380+TEST_OP (le, <=)
381+TEST_OP (ge, >=)
382
383=== added file 'gcc/testsuite/gcc.target/arm/cmp-2.c'
384--- old/gcc/testsuite/gcc.target/arm/cmp-2.c 1970-01-01 00:00:00 +0000
385+++ new/gcc/testsuite/gcc.target/arm/cmp-2.c 2011-10-03 09:47:33 +0000
386@@ -0,0 +1,49 @@
387+/* { dg-do compile } */
388+/* { dg-require-effective-target arm_vfp_ok } */
389+/* { dg-skip-if "need fp instructions" { *-*-* } { "-mfloat-abi=soft" } { "" } } */
390+/* { dg-options "-O -mfpu=vfp -mfloat-abi=softfp" } */
391+/* { dg-final { scan-assembler-not "\tbl\t" } } */
392+/* { dg-final { scan-assembler-not "__aeabi" } } */
393+int x, y;
394+
395+#define EQ(X, Y) ((X) == (Y))
396+#define NE(X, Y) ((X) != (Y))
397+#define LT(X, Y) ((X) < (Y))
398+#define GT(X, Y) ((X) > (Y))
399+#define LE(X, Y) ((X) <= (Y))
400+#define GE(X, Y) ((X) >= (Y))
401+
402+#define TEST_EXPR(NAME, ARGS, EXPR) \
403+ int NAME##1 ARGS { return (EXPR); } \
404+ int NAME##2 ARGS { return !(EXPR); } \
405+ int NAME##3 ARGS { return (EXPR) ? x : y; } \
406+ void NAME##4 ARGS { if (EXPR) x++; } \
407+ void NAME##5 ARGS { if (!(EXPR)) x++; }
408+
409+#define TEST(NAME, TYPE, OPERATOR) \
410+ TEST_EXPR (NAME##_rr, (TYPE a1, TYPE a2), OPERATOR (a1, a2)) \
411+ TEST_EXPR (NAME##_rm, (TYPE a1, TYPE *a2), OPERATOR (a1, *a2)) \
412+ TEST_EXPR (NAME##_mr, (TYPE *a1, TYPE a2), OPERATOR (*a1, a2)) \
413+ TEST_EXPR (NAME##_mm, (TYPE *a1, TYPE *a2), OPERATOR (*a1, *a2)) \
414+ TEST_EXPR (NAME##_rc, (TYPE a1), OPERATOR (a1, 100)) \
415+ TEST_EXPR (NAME##_cr, (TYPE a1), OPERATOR (100, a1))
416+
417+#define TEST_OP(NAME, OPERATOR) \
418+ TEST (f_##NAME, float, OPERATOR) \
419+ TEST (d_##NAME, double, OPERATOR) \
420+ TEST (ld_##NAME, long double, OPERATOR)
421+
422+TEST_OP (eq, EQ)
423+TEST_OP (ne, NE)
424+TEST_OP (lt, LT)
425+TEST_OP (gt, GT)
426+TEST_OP (le, LE)
427+TEST_OP (ge, GE)
428+TEST_OP (blt, __builtin_isless)
429+TEST_OP (bgt, __builtin_isgreater)
430+TEST_OP (ble, __builtin_islessequal)
431+TEST_OP (bge, __builtin_isgreaterequal)
432+/* This one should be expanded into separate ordered and equality
433+ comparisons. */
434+TEST_OP (blg, __builtin_islessgreater)
435+TEST_OP (bun, __builtin_isunordered)
436
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