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-rw-r--r--meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106816.patch387
1 files changed, 387 insertions, 0 deletions
diff --git a/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106816.patch b/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106816.patch
new file mode 100644
index 0000000000..2f70b1b9c2
--- /dev/null
+++ b/meta-oe/recipes-devtools/gcc/gcc-4.6/linaro/gcc-4.6-linaro-r106816.patch
@@ -0,0 +1,387 @@
12011-09-28 Richard Sandiford <richard.sandiford@linaro.org>
2
3 gcc/
4 Backport from mainline:
5
6 2011-09-28 Richard Sandiford <richard.sandiford@linaro.org>
7
8 * config/arm/neon.md (neon_move_lo_quad_<mode>): Delete.
9 (neon_move_hi_quad_<mode>): Likewise.
10 (move_hi_quad_<mode>, move_lo_quad_<mode>): Use subreg moves.
11
122011-09-28 Richard Sandiford <richard.sandiford@linaro.org>
13
14 gcc/
15 Backport from mainline:
16
17 2011-09-27 Richard Sandiford <richard.sandiford@linaro.org>
18
19 * config/arm/neon.md (neon_vget_highv16qi, neon_vget_highv8hi)
20 (neon_vget_highv4si, neon_vget_highv4sf, neon_vget_highv2di)
21 (neon_vget_lowv16qi, neon_vget_lowv8hi, neon_vget_lowv4si)
22 (neon_vget_lowv4sf, neon_vget_lowv2di): Turn into define_expands
23 that produce subreg moves. Define using VQX iterators.
24
252011-09-28 Richard Sandiford <richard.sandiford@linaro.org>
26
27 gcc/
28 Backport from mainline:
29
30 2011-09-14 Richard Sandiford <richard.sandiford@linaro.org>
31
32 * simplify-rtx.c (simplify_subreg): Check that the inner mode is
33 a scalar integer before applying integer-only optimisations to
34 inner arithmetic.
35
36=== modified file 'gcc/config/arm/neon.md'
37--- old/gcc/config/arm/neon.md 2011-07-04 14:03:49 +0000
38+++ new/gcc/config/arm/neon.md 2011-09-28 15:14:59 +0000
39@@ -1235,66 +1235,14 @@
40 (const_string "neon_int_1") (const_string "neon_int_5")))]
41 )
42
43-; FIXME: We wouldn't need the following insns if we could write subregs of
44-; vector registers. Make an attempt at removing unnecessary moves, though
45-; we're really at the mercy of the register allocator.
46-
47-(define_insn "neon_move_lo_quad_<mode>"
48- [(set (match_operand:ANY128 0 "s_register_operand" "+w")
49- (vec_concat:ANY128
50- (match_operand:<V_HALF> 1 "s_register_operand" "w")
51- (vec_select:<V_HALF>
52- (match_dup 0)
53- (match_operand:ANY128 2 "vect_par_constant_high" ""))))]
54- "TARGET_NEON"
55-{
56- int dest = REGNO (operands[0]);
57- int src = REGNO (operands[1]);
58-
59- if (dest != src)
60- return "vmov\t%e0, %P1";
61- else
62- return "";
63-}
64- [(set_attr "neon_type" "neon_bp_simple")]
65-)
66-
67-(define_insn "neon_move_hi_quad_<mode>"
68- [(set (match_operand:ANY128 0 "s_register_operand" "+w")
69- (vec_concat:ANY128
70- (vec_select:<V_HALF>
71- (match_dup 0)
72- (match_operand:ANY128 2 "vect_par_constant_low" ""))
73- (match_operand:<V_HALF> 1 "s_register_operand" "w")))]
74-
75- "TARGET_NEON"
76-{
77- int dest = REGNO (operands[0]);
78- int src = REGNO (operands[1]);
79-
80- if (dest != src)
81- return "vmov\t%f0, %P1";
82- else
83- return "";
84-}
85- [(set_attr "neon_type" "neon_bp_simple")]
86-)
87-
88 (define_expand "move_hi_quad_<mode>"
89 [(match_operand:ANY128 0 "s_register_operand" "")
90 (match_operand:<V_HALF> 1 "s_register_operand" "")]
91 "TARGET_NEON"
92 {
93- rtvec v = rtvec_alloc (<V_mode_nunits>/2);
94- rtx t1;
95- int i;
96-
97- for (i=0; i < (<V_mode_nunits>/2); i++)
98- RTVEC_ELT (v, i) = GEN_INT (i);
99-
100- t1 = gen_rtx_PARALLEL (<MODE>mode, v);
101- emit_insn (gen_neon_move_hi_quad_<mode> (operands[0], operands[1], t1));
102-
103+ emit_move_insn (simplify_gen_subreg (<V_HALF>mode, operands[0], <MODE>mode,
104+ GET_MODE_SIZE (<V_HALF>mode)),
105+ operands[1]);
106 DONE;
107 })
108
109@@ -1303,16 +1251,9 @@
110 (match_operand:<V_HALF> 1 "s_register_operand" "")]
111 "TARGET_NEON"
112 {
113- rtvec v = rtvec_alloc (<V_mode_nunits>/2);
114- rtx t1;
115- int i;
116-
117- for (i=0; i < (<V_mode_nunits>/2); i++)
118- RTVEC_ELT (v, i) = GEN_INT ((<V_mode_nunits>/2) + i);
119-
120- t1 = gen_rtx_PARALLEL (<MODE>mode, v);
121- emit_insn (gen_neon_move_lo_quad_<mode> (operands[0], operands[1], t1));
122-
123+ emit_move_insn (simplify_gen_subreg (<V_HALF>mode, operands[0],
124+ <MODE>mode, 0),
125+ operands[1]);
126 DONE;
127 })
128
129@@ -2950,183 +2891,27 @@
130 (set_attr "neon_type" "neon_bp_simple")]
131 )
132
133-(define_insn "neon_vget_highv16qi"
134- [(set (match_operand:V8QI 0 "s_register_operand" "=w")
135- (vec_select:V8QI (match_operand:V16QI 1 "s_register_operand" "w")
136- (parallel [(const_int 8) (const_int 9)
137- (const_int 10) (const_int 11)
138- (const_int 12) (const_int 13)
139- (const_int 14) (const_int 15)])))]
140- "TARGET_NEON"
141-{
142- int dest = REGNO (operands[0]);
143- int src = REGNO (operands[1]);
144-
145- if (dest != src + 2)
146- return "vmov\t%P0, %f1";
147- else
148- return "";
149-}
150- [(set_attr "neon_type" "neon_bp_simple")]
151-)
152-
153-(define_insn "neon_vget_highv8hi"
154- [(set (match_operand:V4HI 0 "s_register_operand" "=w")
155- (vec_select:V4HI (match_operand:V8HI 1 "s_register_operand" "w")
156- (parallel [(const_int 4) (const_int 5)
157- (const_int 6) (const_int 7)])))]
158- "TARGET_NEON"
159-{
160- int dest = REGNO (operands[0]);
161- int src = REGNO (operands[1]);
162-
163- if (dest != src + 2)
164- return "vmov\t%P0, %f1";
165- else
166- return "";
167-}
168- [(set_attr "neon_type" "neon_bp_simple")]
169-)
170-
171-(define_insn "neon_vget_highv4si"
172- [(set (match_operand:V2SI 0 "s_register_operand" "=w")
173- (vec_select:V2SI (match_operand:V4SI 1 "s_register_operand" "w")
174- (parallel [(const_int 2) (const_int 3)])))]
175- "TARGET_NEON"
176-{
177- int dest = REGNO (operands[0]);
178- int src = REGNO (operands[1]);
179-
180- if (dest != src + 2)
181- return "vmov\t%P0, %f1";
182- else
183- return "";
184-}
185- [(set_attr "neon_type" "neon_bp_simple")]
186-)
187-
188-(define_insn "neon_vget_highv4sf"
189- [(set (match_operand:V2SF 0 "s_register_operand" "=w")
190- (vec_select:V2SF (match_operand:V4SF 1 "s_register_operand" "w")
191- (parallel [(const_int 2) (const_int 3)])))]
192- "TARGET_NEON"
193-{
194- int dest = REGNO (operands[0]);
195- int src = REGNO (operands[1]);
196-
197- if (dest != src + 2)
198- return "vmov\t%P0, %f1";
199- else
200- return "";
201-}
202- [(set_attr "neon_type" "neon_bp_simple")]
203-)
204-
205-(define_insn "neon_vget_highv2di"
206- [(set (match_operand:DI 0 "s_register_operand" "=w")
207- (vec_select:DI (match_operand:V2DI 1 "s_register_operand" "w")
208- (parallel [(const_int 1)])))]
209- "TARGET_NEON"
210-{
211- int dest = REGNO (operands[0]);
212- int src = REGNO (operands[1]);
213-
214- if (dest != src + 2)
215- return "vmov\t%P0, %f1";
216- else
217- return "";
218-}
219- [(set_attr "neon_type" "neon_bp_simple")]
220-)
221-
222-(define_insn "neon_vget_lowv16qi"
223- [(set (match_operand:V8QI 0 "s_register_operand" "=w")
224- (vec_select:V8QI (match_operand:V16QI 1 "s_register_operand" "w")
225- (parallel [(const_int 0) (const_int 1)
226- (const_int 2) (const_int 3)
227- (const_int 4) (const_int 5)
228- (const_int 6) (const_int 7)])))]
229- "TARGET_NEON"
230-{
231- int dest = REGNO (operands[0]);
232- int src = REGNO (operands[1]);
233-
234- if (dest != src)
235- return "vmov\t%P0, %e1";
236- else
237- return "";
238-}
239- [(set_attr "neon_type" "neon_bp_simple")]
240-)
241-
242-(define_insn "neon_vget_lowv8hi"
243- [(set (match_operand:V4HI 0 "s_register_operand" "=w")
244- (vec_select:V4HI (match_operand:V8HI 1 "s_register_operand" "w")
245- (parallel [(const_int 0) (const_int 1)
246- (const_int 2) (const_int 3)])))]
247- "TARGET_NEON"
248-{
249- int dest = REGNO (operands[0]);
250- int src = REGNO (operands[1]);
251-
252- if (dest != src)
253- return "vmov\t%P0, %e1";
254- else
255- return "";
256-}
257- [(set_attr "neon_type" "neon_bp_simple")]
258-)
259-
260-(define_insn "neon_vget_lowv4si"
261- [(set (match_operand:V2SI 0 "s_register_operand" "=w")
262- (vec_select:V2SI (match_operand:V4SI 1 "s_register_operand" "w")
263- (parallel [(const_int 0) (const_int 1)])))]
264- "TARGET_NEON"
265-{
266- int dest = REGNO (operands[0]);
267- int src = REGNO (operands[1]);
268-
269- if (dest != src)
270- return "vmov\t%P0, %e1";
271- else
272- return "";
273-}
274- [(set_attr "neon_type" "neon_bp_simple")]
275-)
276-
277-(define_insn "neon_vget_lowv4sf"
278- [(set (match_operand:V2SF 0 "s_register_operand" "=w")
279- (vec_select:V2SF (match_operand:V4SF 1 "s_register_operand" "w")
280- (parallel [(const_int 0) (const_int 1)])))]
281- "TARGET_NEON"
282-{
283- int dest = REGNO (operands[0]);
284- int src = REGNO (operands[1]);
285-
286- if (dest != src)
287- return "vmov\t%P0, %e1";
288- else
289- return "";
290-}
291- [(set_attr "neon_type" "neon_bp_simple")]
292-)
293-
294-(define_insn "neon_vget_lowv2di"
295- [(set (match_operand:DI 0 "s_register_operand" "=w")
296- (vec_select:DI (match_operand:V2DI 1 "s_register_operand" "w")
297- (parallel [(const_int 0)])))]
298- "TARGET_NEON"
299-{
300- int dest = REGNO (operands[0]);
301- int src = REGNO (operands[1]);
302-
303- if (dest != src)
304- return "vmov\t%P0, %e1";
305- else
306- return "";
307-}
308- [(set_attr "neon_type" "neon_bp_simple")]
309-)
310+(define_expand "neon_vget_high<mode>"
311+ [(match_operand:<V_HALF> 0 "s_register_operand")
312+ (match_operand:VQX 1 "s_register_operand")]
313+ "TARGET_NEON"
314+{
315+ emit_move_insn (operands[0],
316+ simplify_gen_subreg (<V_HALF>mode, operands[1], <MODE>mode,
317+ GET_MODE_SIZE (<V_HALF>mode)));
318+ DONE;
319+})
320+
321+(define_expand "neon_vget_low<mode>"
322+ [(match_operand:<V_HALF> 0 "s_register_operand")
323+ (match_operand:VQX 1 "s_register_operand")]
324+ "TARGET_NEON"
325+{
326+ emit_move_insn (operands[0],
327+ simplify_gen_subreg (<V_HALF>mode, operands[1],
328+ <MODE>mode, 0));
329+ DONE;
330+})
331
332 (define_insn "neon_vcvt<mode>"
333 [(set (match_operand:<V_CVTTO> 0 "s_register_operand" "=w")
334
335=== modified file 'gcc/simplify-rtx.c'
336--- old/gcc/simplify-rtx.c 2011-08-13 08:32:32 +0000
337+++ new/gcc/simplify-rtx.c 2011-09-28 15:11:59 +0000
338@@ -5567,6 +5567,7 @@
339 /* Optimize SUBREG truncations of zero and sign extended values. */
340 if ((GET_CODE (op) == ZERO_EXTEND
341 || GET_CODE (op) == SIGN_EXTEND)
342+ && SCALAR_INT_MODE_P (innermode)
343 && GET_MODE_BITSIZE (outermode) < GET_MODE_BITSIZE (innermode))
344 {
345 unsigned int bitpos = subreg_lsb_1 (outermode, innermode, byte);
346@@ -5605,6 +5606,7 @@
347 if ((GET_CODE (op) == LSHIFTRT
348 || GET_CODE (op) == ASHIFTRT)
349 && SCALAR_INT_MODE_P (outermode)
350+ && SCALAR_INT_MODE_P (innermode)
351 /* Ensure that OUTERMODE is at least twice as wide as the INNERMODE
352 to avoid the possibility that an outer LSHIFTRT shifts by more
353 than the sign extension's sign_bit_copies and introduces zeros
354@@ -5624,6 +5626,7 @@
355 if ((GET_CODE (op) == LSHIFTRT
356 || GET_CODE (op) == ASHIFTRT)
357 && SCALAR_INT_MODE_P (outermode)
358+ && SCALAR_INT_MODE_P (innermode)
359 && GET_MODE_BITSIZE (outermode) < GET_MODE_BITSIZE (innermode)
360 && CONST_INT_P (XEXP (op, 1))
361 && GET_CODE (XEXP (op, 0)) == ZERO_EXTEND
362@@ -5638,6 +5641,7 @@
363 the outer subreg is effectively a truncation to the original mode. */
364 if (GET_CODE (op) == ASHIFT
365 && SCALAR_INT_MODE_P (outermode)
366+ && SCALAR_INT_MODE_P (innermode)
367 && GET_MODE_BITSIZE (outermode) < GET_MODE_BITSIZE (innermode)
368 && CONST_INT_P (XEXP (op, 1))
369 && (GET_CODE (XEXP (op, 0)) == ZERO_EXTEND
370@@ -5651,7 +5655,7 @@
371 /* Recognize a word extraction from a multi-word subreg. */
372 if ((GET_CODE (op) == LSHIFTRT
373 || GET_CODE (op) == ASHIFTRT)
374- && SCALAR_INT_MODE_P (outermode)
375+ && SCALAR_INT_MODE_P (innermode)
376 && GET_MODE_BITSIZE (outermode) >= BITS_PER_WORD
377 && GET_MODE_BITSIZE (innermode) >= (2 * GET_MODE_BITSIZE (outermode))
378 && CONST_INT_P (XEXP (op, 1))
379@@ -5673,6 +5677,7 @@
380
381 if ((GET_CODE (op) == LSHIFTRT
382 || GET_CODE (op) == ASHIFTRT)
383+ && SCALAR_INT_MODE_P (innermode)
384 && MEM_P (XEXP (op, 0))
385 && CONST_INT_P (XEXP (op, 1))
386 && GET_MODE_SIZE (outermode) < GET_MODE_SIZE (GET_MODE (op))
387
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